1 /* 2 * ARM PrimeCell Timer modules. 3 * 4 * Copyright (c) 2005-2006 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "hw/sysbus.h" 12 #include "migration/vmstate.h" 13 #include "qemu/timer.h" 14 #include "hw/irq.h" 15 #include "hw/ptimer.h" 16 #include "hw/qdev-properties.h" 17 #include "qemu/main-loop.h" 18 #include "qemu/module.h" 19 #include "qemu/log.h" 20 21 /* Common timer implementation. */ 22 23 #define TIMER_CTRL_ONESHOT (1 << 0) 24 #define TIMER_CTRL_32BIT (1 << 1) 25 #define TIMER_CTRL_DIV1 (0 << 2) 26 #define TIMER_CTRL_DIV16 (1 << 2) 27 #define TIMER_CTRL_DIV256 (2 << 2) 28 #define TIMER_CTRL_IE (1 << 5) 29 #define TIMER_CTRL_PERIODIC (1 << 6) 30 #define TIMER_CTRL_ENABLE (1 << 7) 31 32 typedef struct { 33 ptimer_state *timer; 34 uint32_t control; 35 uint32_t limit; 36 int freq; 37 int int_level; 38 qemu_irq irq; 39 } arm_timer_state; 40 41 /* Check all active timers, and schedule the next timer interrupt. */ 42 43 static void arm_timer_update(arm_timer_state *s) 44 { 45 /* Update interrupts. */ 46 if (s->int_level && (s->control & TIMER_CTRL_IE)) { 47 qemu_irq_raise(s->irq); 48 } else { 49 qemu_irq_lower(s->irq); 50 } 51 } 52 53 static uint32_t arm_timer_read(void *opaque, hwaddr offset) 54 { 55 arm_timer_state *s = (arm_timer_state *)opaque; 56 57 switch (offset >> 2) { 58 case 0: /* TimerLoad */ 59 case 6: /* TimerBGLoad */ 60 return s->limit; 61 case 1: /* TimerValue */ 62 return ptimer_get_count(s->timer); 63 case 2: /* TimerControl */ 64 return s->control; 65 case 4: /* TimerRIS */ 66 return s->int_level; 67 case 5: /* TimerMIS */ 68 if ((s->control & TIMER_CTRL_IE) == 0) 69 return 0; 70 return s->int_level; 71 default: 72 qemu_log_mask(LOG_GUEST_ERROR, 73 "%s: Bad offset %x\n", __func__, (int)offset); 74 return 0; 75 } 76 } 77 78 /* Reset the timer limit after settings have changed. */ 79 static void arm_timer_recalibrate(arm_timer_state *s, int reload) 80 { 81 uint32_t limit; 82 83 if ((s->control & (TIMER_CTRL_PERIODIC | TIMER_CTRL_ONESHOT)) == 0) { 84 /* Free running. */ 85 if (s->control & TIMER_CTRL_32BIT) 86 limit = 0xffffffff; 87 else 88 limit = 0xffff; 89 } else { 90 /* Periodic. */ 91 limit = s->limit; 92 } 93 ptimer_set_limit(s->timer, limit, reload); 94 } 95 96 static void arm_timer_write(void *opaque, hwaddr offset, 97 uint32_t value) 98 { 99 arm_timer_state *s = (arm_timer_state *)opaque; 100 int freq; 101 102 switch (offset >> 2) { 103 case 0: /* TimerLoad */ 104 s->limit = value; 105 arm_timer_recalibrate(s, 1); 106 break; 107 case 1: /* TimerValue */ 108 /* ??? Linux seems to want to write to this readonly register. 109 Ignore it. */ 110 break; 111 case 2: /* TimerControl */ 112 if (s->control & TIMER_CTRL_ENABLE) { 113 /* Pause the timer if it is running. This may cause some 114 inaccuracy dure to rounding, but avoids a whole lot of other 115 messyness. */ 116 ptimer_stop(s->timer); 117 } 118 s->control = value; 119 freq = s->freq; 120 /* ??? Need to recalculate expiry time after changing divisor. */ 121 switch ((value >> 2) & 3) { 122 case 1: freq >>= 4; break; 123 case 2: freq >>= 8; break; 124 } 125 arm_timer_recalibrate(s, s->control & TIMER_CTRL_ENABLE); 126 ptimer_set_freq(s->timer, freq); 127 if (s->control & TIMER_CTRL_ENABLE) { 128 /* Restart the timer if still enabled. */ 129 ptimer_run(s->timer, (s->control & TIMER_CTRL_ONESHOT) != 0); 130 } 131 break; 132 case 3: /* TimerIntClr */ 133 s->int_level = 0; 134 break; 135 case 6: /* TimerBGLoad */ 136 s->limit = value; 137 arm_timer_recalibrate(s, 0); 138 break; 139 default: 140 qemu_log_mask(LOG_GUEST_ERROR, 141 "%s: Bad offset %x\n", __func__, (int)offset); 142 } 143 arm_timer_update(s); 144 } 145 146 static void arm_timer_tick(void *opaque) 147 { 148 arm_timer_state *s = (arm_timer_state *)opaque; 149 s->int_level = 1; 150 arm_timer_update(s); 151 } 152 153 static const VMStateDescription vmstate_arm_timer = { 154 .name = "arm_timer", 155 .version_id = 1, 156 .minimum_version_id = 1, 157 .fields = (VMStateField[]) { 158 VMSTATE_UINT32(control, arm_timer_state), 159 VMSTATE_UINT32(limit, arm_timer_state), 160 VMSTATE_INT32(int_level, arm_timer_state), 161 VMSTATE_PTIMER(timer, arm_timer_state), 162 VMSTATE_END_OF_LIST() 163 } 164 }; 165 166 static arm_timer_state *arm_timer_init(uint32_t freq) 167 { 168 arm_timer_state *s; 169 QEMUBH *bh; 170 171 s = (arm_timer_state *)g_malloc0(sizeof(arm_timer_state)); 172 s->freq = freq; 173 s->control = TIMER_CTRL_IE; 174 175 bh = qemu_bh_new(arm_timer_tick, s); 176 s->timer = ptimer_init(bh, PTIMER_POLICY_DEFAULT); 177 vmstate_register(NULL, -1, &vmstate_arm_timer, s); 178 return s; 179 } 180 181 /* ARM PrimeCell SP804 dual timer module. 182 * Docs at 183 * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0271d/index.html 184 */ 185 186 #define TYPE_SP804 "sp804" 187 #define SP804(obj) OBJECT_CHECK(SP804State, (obj), TYPE_SP804) 188 189 typedef struct SP804State { 190 SysBusDevice parent_obj; 191 192 MemoryRegion iomem; 193 arm_timer_state *timer[2]; 194 uint32_t freq0, freq1; 195 int level[2]; 196 qemu_irq irq; 197 } SP804State; 198 199 static const uint8_t sp804_ids[] = { 200 /* Timer ID */ 201 0x04, 0x18, 0x14, 0, 202 /* PrimeCell ID */ 203 0xd, 0xf0, 0x05, 0xb1 204 }; 205 206 /* Merge the IRQs from the two component devices. */ 207 static void sp804_set_irq(void *opaque, int irq, int level) 208 { 209 SP804State *s = (SP804State *)opaque; 210 211 s->level[irq] = level; 212 qemu_set_irq(s->irq, s->level[0] || s->level[1]); 213 } 214 215 static uint64_t sp804_read(void *opaque, hwaddr offset, 216 unsigned size) 217 { 218 SP804State *s = (SP804State *)opaque; 219 220 if (offset < 0x20) { 221 return arm_timer_read(s->timer[0], offset); 222 } 223 if (offset < 0x40) { 224 return arm_timer_read(s->timer[1], offset - 0x20); 225 } 226 227 /* TimerPeriphID */ 228 if (offset >= 0xfe0 && offset <= 0xffc) { 229 return sp804_ids[(offset - 0xfe0) >> 2]; 230 } 231 232 switch (offset) { 233 /* Integration Test control registers, which we won't support */ 234 case 0xf00: /* TimerITCR */ 235 case 0xf04: /* TimerITOP (strictly write only but..) */ 236 qemu_log_mask(LOG_UNIMP, 237 "%s: integration test registers unimplemented\n", 238 __func__); 239 return 0; 240 } 241 242 qemu_log_mask(LOG_GUEST_ERROR, 243 "%s: Bad offset %x\n", __func__, (int)offset); 244 return 0; 245 } 246 247 static void sp804_write(void *opaque, hwaddr offset, 248 uint64_t value, unsigned size) 249 { 250 SP804State *s = (SP804State *)opaque; 251 252 if (offset < 0x20) { 253 arm_timer_write(s->timer[0], offset, value); 254 return; 255 } 256 257 if (offset < 0x40) { 258 arm_timer_write(s->timer[1], offset - 0x20, value); 259 return; 260 } 261 262 /* Technically we could be writing to the Test Registers, but not likely */ 263 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %x\n", 264 __func__, (int)offset); 265 } 266 267 static const MemoryRegionOps sp804_ops = { 268 .read = sp804_read, 269 .write = sp804_write, 270 .endianness = DEVICE_NATIVE_ENDIAN, 271 }; 272 273 static const VMStateDescription vmstate_sp804 = { 274 .name = "sp804", 275 .version_id = 1, 276 .minimum_version_id = 1, 277 .fields = (VMStateField[]) { 278 VMSTATE_INT32_ARRAY(level, SP804State, 2), 279 VMSTATE_END_OF_LIST() 280 } 281 }; 282 283 static void sp804_init(Object *obj) 284 { 285 SP804State *s = SP804(obj); 286 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 287 288 sysbus_init_irq(sbd, &s->irq); 289 memory_region_init_io(&s->iomem, obj, &sp804_ops, s, 290 "sp804", 0x1000); 291 sysbus_init_mmio(sbd, &s->iomem); 292 } 293 294 static void sp804_realize(DeviceState *dev, Error **errp) 295 { 296 SP804State *s = SP804(dev); 297 298 s->timer[0] = arm_timer_init(s->freq0); 299 s->timer[1] = arm_timer_init(s->freq1); 300 s->timer[0]->irq = qemu_allocate_irq(sp804_set_irq, s, 0); 301 s->timer[1]->irq = qemu_allocate_irq(sp804_set_irq, s, 1); 302 } 303 304 /* Integrator/CP timer module. */ 305 306 #define TYPE_INTEGRATOR_PIT "integrator_pit" 307 #define INTEGRATOR_PIT(obj) \ 308 OBJECT_CHECK(icp_pit_state, (obj), TYPE_INTEGRATOR_PIT) 309 310 typedef struct { 311 SysBusDevice parent_obj; 312 313 MemoryRegion iomem; 314 arm_timer_state *timer[3]; 315 } icp_pit_state; 316 317 static uint64_t icp_pit_read(void *opaque, hwaddr offset, 318 unsigned size) 319 { 320 icp_pit_state *s = (icp_pit_state *)opaque; 321 int n; 322 323 /* ??? Don't know the PrimeCell ID for this device. */ 324 n = offset >> 8; 325 if (n > 2) { 326 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad timer %d\n", __func__, n); 327 return 0; 328 } 329 330 return arm_timer_read(s->timer[n], offset & 0xff); 331 } 332 333 static void icp_pit_write(void *opaque, hwaddr offset, 334 uint64_t value, unsigned size) 335 { 336 icp_pit_state *s = (icp_pit_state *)opaque; 337 int n; 338 339 n = offset >> 8; 340 if (n > 2) { 341 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad timer %d\n", __func__, n); 342 return; 343 } 344 345 arm_timer_write(s->timer[n], offset & 0xff, value); 346 } 347 348 static const MemoryRegionOps icp_pit_ops = { 349 .read = icp_pit_read, 350 .write = icp_pit_write, 351 .endianness = DEVICE_NATIVE_ENDIAN, 352 }; 353 354 static void icp_pit_init(Object *obj) 355 { 356 icp_pit_state *s = INTEGRATOR_PIT(obj); 357 SysBusDevice *dev = SYS_BUS_DEVICE(obj); 358 359 /* Timer 0 runs at the system clock speed (40MHz). */ 360 s->timer[0] = arm_timer_init(40000000); 361 /* The other two timers run at 1MHz. */ 362 s->timer[1] = arm_timer_init(1000000); 363 s->timer[2] = arm_timer_init(1000000); 364 365 sysbus_init_irq(dev, &s->timer[0]->irq); 366 sysbus_init_irq(dev, &s->timer[1]->irq); 367 sysbus_init_irq(dev, &s->timer[2]->irq); 368 369 memory_region_init_io(&s->iomem, obj, &icp_pit_ops, s, 370 "icp_pit", 0x1000); 371 sysbus_init_mmio(dev, &s->iomem); 372 /* This device has no state to save/restore. The component timers will 373 save themselves. */ 374 } 375 376 static const TypeInfo icp_pit_info = { 377 .name = TYPE_INTEGRATOR_PIT, 378 .parent = TYPE_SYS_BUS_DEVICE, 379 .instance_size = sizeof(icp_pit_state), 380 .instance_init = icp_pit_init, 381 }; 382 383 static Property sp804_properties[] = { 384 DEFINE_PROP_UINT32("freq0", SP804State, freq0, 1000000), 385 DEFINE_PROP_UINT32("freq1", SP804State, freq1, 1000000), 386 DEFINE_PROP_END_OF_LIST(), 387 }; 388 389 static void sp804_class_init(ObjectClass *klass, void *data) 390 { 391 DeviceClass *k = DEVICE_CLASS(klass); 392 393 k->realize = sp804_realize; 394 k->props = sp804_properties; 395 k->vmsd = &vmstate_sp804; 396 } 397 398 static const TypeInfo sp804_info = { 399 .name = TYPE_SP804, 400 .parent = TYPE_SYS_BUS_DEVICE, 401 .instance_size = sizeof(SP804State), 402 .instance_init = sp804_init, 403 .class_init = sp804_class_init, 404 }; 405 406 static void arm_timer_register_types(void) 407 { 408 type_register_static(&icp_pit_info); 409 type_register_static(&sp804_info); 410 } 411 412 type_init(arm_timer_register_types) 413