1 /* 2 * ARM PrimeCell Timer modules. 3 * 4 * Copyright (c) 2005-2006 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 #include "hw/sysbus.h" 11 #include "qemu/timer.h" 12 #include "qemu-common.h" 13 #include "hw/qdev.h" 14 #include "hw/ptimer.h" 15 #include "qemu/main-loop.h" 16 17 /* Common timer implementation. */ 18 19 #define TIMER_CTRL_ONESHOT (1 << 0) 20 #define TIMER_CTRL_32BIT (1 << 1) 21 #define TIMER_CTRL_DIV1 (0 << 2) 22 #define TIMER_CTRL_DIV16 (1 << 2) 23 #define TIMER_CTRL_DIV256 (2 << 2) 24 #define TIMER_CTRL_IE (1 << 5) 25 #define TIMER_CTRL_PERIODIC (1 << 6) 26 #define TIMER_CTRL_ENABLE (1 << 7) 27 28 typedef struct { 29 ptimer_state *timer; 30 uint32_t control; 31 uint32_t limit; 32 int freq; 33 int int_level; 34 qemu_irq irq; 35 } arm_timer_state; 36 37 /* Check all active timers, and schedule the next timer interrupt. */ 38 39 static void arm_timer_update(arm_timer_state *s) 40 { 41 /* Update interrupts. */ 42 if (s->int_level && (s->control & TIMER_CTRL_IE)) { 43 qemu_irq_raise(s->irq); 44 } else { 45 qemu_irq_lower(s->irq); 46 } 47 } 48 49 static uint32_t arm_timer_read(void *opaque, hwaddr offset) 50 { 51 arm_timer_state *s = (arm_timer_state *)opaque; 52 53 switch (offset >> 2) { 54 case 0: /* TimerLoad */ 55 case 6: /* TimerBGLoad */ 56 return s->limit; 57 case 1: /* TimerValue */ 58 return ptimer_get_count(s->timer); 59 case 2: /* TimerControl */ 60 return s->control; 61 case 4: /* TimerRIS */ 62 return s->int_level; 63 case 5: /* TimerMIS */ 64 if ((s->control & TIMER_CTRL_IE) == 0) 65 return 0; 66 return s->int_level; 67 default: 68 qemu_log_mask(LOG_GUEST_ERROR, 69 "%s: Bad offset %x\n", __func__, (int)offset); 70 return 0; 71 } 72 } 73 74 /* Reset the timer limit after settings have changed. */ 75 static void arm_timer_recalibrate(arm_timer_state *s, int reload) 76 { 77 uint32_t limit; 78 79 if ((s->control & (TIMER_CTRL_PERIODIC | TIMER_CTRL_ONESHOT)) == 0) { 80 /* Free running. */ 81 if (s->control & TIMER_CTRL_32BIT) 82 limit = 0xffffffff; 83 else 84 limit = 0xffff; 85 } else { 86 /* Periodic. */ 87 limit = s->limit; 88 } 89 ptimer_set_limit(s->timer, limit, reload); 90 } 91 92 static void arm_timer_write(void *opaque, hwaddr offset, 93 uint32_t value) 94 { 95 arm_timer_state *s = (arm_timer_state *)opaque; 96 int freq; 97 98 switch (offset >> 2) { 99 case 0: /* TimerLoad */ 100 s->limit = value; 101 arm_timer_recalibrate(s, 1); 102 break; 103 case 1: /* TimerValue */ 104 /* ??? Linux seems to want to write to this readonly register. 105 Ignore it. */ 106 break; 107 case 2: /* TimerControl */ 108 if (s->control & TIMER_CTRL_ENABLE) { 109 /* Pause the timer if it is running. This may cause some 110 inaccuracy dure to rounding, but avoids a whole lot of other 111 messyness. */ 112 ptimer_stop(s->timer); 113 } 114 s->control = value; 115 freq = s->freq; 116 /* ??? Need to recalculate expiry time after changing divisor. */ 117 switch ((value >> 2) & 3) { 118 case 1: freq >>= 4; break; 119 case 2: freq >>= 8; break; 120 } 121 arm_timer_recalibrate(s, s->control & TIMER_CTRL_ENABLE); 122 ptimer_set_freq(s->timer, freq); 123 if (s->control & TIMER_CTRL_ENABLE) { 124 /* Restart the timer if still enabled. */ 125 ptimer_run(s->timer, (s->control & TIMER_CTRL_ONESHOT) != 0); 126 } 127 break; 128 case 3: /* TimerIntClr */ 129 s->int_level = 0; 130 break; 131 case 6: /* TimerBGLoad */ 132 s->limit = value; 133 arm_timer_recalibrate(s, 0); 134 break; 135 default: 136 qemu_log_mask(LOG_GUEST_ERROR, 137 "%s: Bad offset %x\n", __func__, (int)offset); 138 } 139 arm_timer_update(s); 140 } 141 142 static void arm_timer_tick(void *opaque) 143 { 144 arm_timer_state *s = (arm_timer_state *)opaque; 145 s->int_level = 1; 146 arm_timer_update(s); 147 } 148 149 static const VMStateDescription vmstate_arm_timer = { 150 .name = "arm_timer", 151 .version_id = 1, 152 .minimum_version_id = 1, 153 .minimum_version_id_old = 1, 154 .fields = (VMStateField[]) { 155 VMSTATE_UINT32(control, arm_timer_state), 156 VMSTATE_UINT32(limit, arm_timer_state), 157 VMSTATE_INT32(int_level, arm_timer_state), 158 VMSTATE_PTIMER(timer, arm_timer_state), 159 VMSTATE_END_OF_LIST() 160 } 161 }; 162 163 static arm_timer_state *arm_timer_init(uint32_t freq) 164 { 165 arm_timer_state *s; 166 QEMUBH *bh; 167 168 s = (arm_timer_state *)g_malloc0(sizeof(arm_timer_state)); 169 s->freq = freq; 170 s->control = TIMER_CTRL_IE; 171 172 bh = qemu_bh_new(arm_timer_tick, s); 173 s->timer = ptimer_init(bh); 174 vmstate_register(NULL, -1, &vmstate_arm_timer, s); 175 return s; 176 } 177 178 /* ARM PrimeCell SP804 dual timer module. 179 * Docs at 180 * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0271d/index.html 181 */ 182 183 #define TYPE_SP804 "sp804" 184 #define SP804(obj) OBJECT_CHECK(SP804State, (obj), TYPE_SP804) 185 186 typedef struct SP804State { 187 SysBusDevice parent_obj; 188 189 MemoryRegion iomem; 190 arm_timer_state *timer[2]; 191 uint32_t freq0, freq1; 192 int level[2]; 193 qemu_irq irq; 194 } SP804State; 195 196 static const uint8_t sp804_ids[] = { 197 /* Timer ID */ 198 0x04, 0x18, 0x14, 0, 199 /* PrimeCell ID */ 200 0xd, 0xf0, 0x05, 0xb1 201 }; 202 203 /* Merge the IRQs from the two component devices. */ 204 static void sp804_set_irq(void *opaque, int irq, int level) 205 { 206 SP804State *s = (SP804State *)opaque; 207 208 s->level[irq] = level; 209 qemu_set_irq(s->irq, s->level[0] || s->level[1]); 210 } 211 212 static uint64_t sp804_read(void *opaque, hwaddr offset, 213 unsigned size) 214 { 215 SP804State *s = (SP804State *)opaque; 216 217 if (offset < 0x20) { 218 return arm_timer_read(s->timer[0], offset); 219 } 220 if (offset < 0x40) { 221 return arm_timer_read(s->timer[1], offset - 0x20); 222 } 223 224 /* TimerPeriphID */ 225 if (offset >= 0xfe0 && offset <= 0xffc) { 226 return sp804_ids[(offset - 0xfe0) >> 2]; 227 } 228 229 switch (offset) { 230 /* Integration Test control registers, which we won't support */ 231 case 0xf00: /* TimerITCR */ 232 case 0xf04: /* TimerITOP (strictly write only but..) */ 233 qemu_log_mask(LOG_UNIMP, 234 "%s: integration test registers unimplemented\n", 235 __func__); 236 return 0; 237 } 238 239 qemu_log_mask(LOG_GUEST_ERROR, 240 "%s: Bad offset %x\n", __func__, (int)offset); 241 return 0; 242 } 243 244 static void sp804_write(void *opaque, hwaddr offset, 245 uint64_t value, unsigned size) 246 { 247 SP804State *s = (SP804State *)opaque; 248 249 if (offset < 0x20) { 250 arm_timer_write(s->timer[0], offset, value); 251 return; 252 } 253 254 if (offset < 0x40) { 255 arm_timer_write(s->timer[1], offset - 0x20, value); 256 return; 257 } 258 259 /* Technically we could be writing to the Test Registers, but not likely */ 260 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %x\n", 261 __func__, (int)offset); 262 } 263 264 static const MemoryRegionOps sp804_ops = { 265 .read = sp804_read, 266 .write = sp804_write, 267 .endianness = DEVICE_NATIVE_ENDIAN, 268 }; 269 270 static const VMStateDescription vmstate_sp804 = { 271 .name = "sp804", 272 .version_id = 1, 273 .minimum_version_id = 1, 274 .minimum_version_id_old = 1, 275 .fields = (VMStateField[]) { 276 VMSTATE_INT32_ARRAY(level, SP804State, 2), 277 VMSTATE_END_OF_LIST() 278 } 279 }; 280 281 static int sp804_init(SysBusDevice *sbd) 282 { 283 DeviceState *dev = DEVICE(sbd); 284 SP804State *s = SP804(dev); 285 qemu_irq *qi; 286 287 qi = qemu_allocate_irqs(sp804_set_irq, s, 2); 288 sysbus_init_irq(sbd, &s->irq); 289 s->timer[0] = arm_timer_init(s->freq0); 290 s->timer[1] = arm_timer_init(s->freq1); 291 s->timer[0]->irq = qi[0]; 292 s->timer[1]->irq = qi[1]; 293 memory_region_init_io(&s->iomem, OBJECT(s), &sp804_ops, s, 294 "sp804", 0x1000); 295 sysbus_init_mmio(sbd, &s->iomem); 296 vmstate_register(dev, -1, &vmstate_sp804, s); 297 return 0; 298 } 299 300 /* Integrator/CP timer module. */ 301 302 #define TYPE_INTEGRATOR_PIT "integrator_pit" 303 #define INTEGRATOR_PIT(obj) \ 304 OBJECT_CHECK(icp_pit_state, (obj), TYPE_INTEGRATOR_PIT) 305 306 typedef struct { 307 SysBusDevice parent_obj; 308 309 MemoryRegion iomem; 310 arm_timer_state *timer[3]; 311 } icp_pit_state; 312 313 static uint64_t icp_pit_read(void *opaque, hwaddr offset, 314 unsigned size) 315 { 316 icp_pit_state *s = (icp_pit_state *)opaque; 317 int n; 318 319 /* ??? Don't know the PrimeCell ID for this device. */ 320 n = offset >> 8; 321 if (n > 2) { 322 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad timer %d\n", __func__, n); 323 return 0; 324 } 325 326 return arm_timer_read(s->timer[n], offset & 0xff); 327 } 328 329 static void icp_pit_write(void *opaque, hwaddr offset, 330 uint64_t value, unsigned size) 331 { 332 icp_pit_state *s = (icp_pit_state *)opaque; 333 int n; 334 335 n = offset >> 8; 336 if (n > 2) { 337 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad timer %d\n", __func__, n); 338 return; 339 } 340 341 arm_timer_write(s->timer[n], offset & 0xff, value); 342 } 343 344 static const MemoryRegionOps icp_pit_ops = { 345 .read = icp_pit_read, 346 .write = icp_pit_write, 347 .endianness = DEVICE_NATIVE_ENDIAN, 348 }; 349 350 static int icp_pit_init(SysBusDevice *dev) 351 { 352 icp_pit_state *s = INTEGRATOR_PIT(dev); 353 354 /* Timer 0 runs at the system clock speed (40MHz). */ 355 s->timer[0] = arm_timer_init(40000000); 356 /* The other two timers run at 1MHz. */ 357 s->timer[1] = arm_timer_init(1000000); 358 s->timer[2] = arm_timer_init(1000000); 359 360 sysbus_init_irq(dev, &s->timer[0]->irq); 361 sysbus_init_irq(dev, &s->timer[1]->irq); 362 sysbus_init_irq(dev, &s->timer[2]->irq); 363 364 memory_region_init_io(&s->iomem, OBJECT(s), &icp_pit_ops, s, 365 "icp_pit", 0x1000); 366 sysbus_init_mmio(dev, &s->iomem); 367 /* This device has no state to save/restore. The component timers will 368 save themselves. */ 369 return 0; 370 } 371 372 static void icp_pit_class_init(ObjectClass *klass, void *data) 373 { 374 SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass); 375 376 sdc->init = icp_pit_init; 377 } 378 379 static const TypeInfo icp_pit_info = { 380 .name = TYPE_INTEGRATOR_PIT, 381 .parent = TYPE_SYS_BUS_DEVICE, 382 .instance_size = sizeof(icp_pit_state), 383 .class_init = icp_pit_class_init, 384 }; 385 386 static Property sp804_properties[] = { 387 DEFINE_PROP_UINT32("freq0", SP804State, freq0, 1000000), 388 DEFINE_PROP_UINT32("freq1", SP804State, freq1, 1000000), 389 DEFINE_PROP_END_OF_LIST(), 390 }; 391 392 static void sp804_class_init(ObjectClass *klass, void *data) 393 { 394 SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass); 395 DeviceClass *k = DEVICE_CLASS(klass); 396 397 sdc->init = sp804_init; 398 k->props = sp804_properties; 399 } 400 401 static const TypeInfo sp804_info = { 402 .name = TYPE_SP804, 403 .parent = TYPE_SYS_BUS_DEVICE, 404 .instance_size = sizeof(SP804State), 405 .class_init = sp804_class_init, 406 }; 407 408 static void arm_timer_register_types(void) 409 { 410 type_register_static(&icp_pit_info); 411 type_register_static(&sp804_info); 412 } 413 414 type_init(arm_timer_register_types) 415