1 /* 2 * Private peripheral timer/watchdog blocks for ARM 11MPCore and A9MP 3 * 4 * Copyright (c) 2006-2007 CodeSourcery. 5 * Copyright (c) 2011 Linaro Limited 6 * Written by Paul Brook, Peter Maydell 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License 10 * as published by the Free Software Foundation; either version 11 * 2 of the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License along 19 * with this program; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #include "qemu/osdep.h" 23 #include "hw/hw.h" 24 #include "hw/irq.h" 25 #include "hw/ptimer.h" 26 #include "hw/qdev-properties.h" 27 #include "hw/timer/arm_mptimer.h" 28 #include "migration/vmstate.h" 29 #include "qapi/error.h" 30 #include "qemu/module.h" 31 #include "hw/core/cpu.h" 32 33 #define PTIMER_POLICY \ 34 (PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD | \ 35 PTIMER_POLICY_CONTINUOUS_TRIGGER | \ 36 PTIMER_POLICY_NO_IMMEDIATE_TRIGGER | \ 37 PTIMER_POLICY_NO_IMMEDIATE_RELOAD | \ 38 PTIMER_POLICY_NO_COUNTER_ROUND_DOWN) 39 40 /* This device implements the per-cpu private timer and watchdog block 41 * which is used in both the ARM11MPCore and Cortex-A9MP. 42 */ 43 44 static inline int get_current_cpu(ARMMPTimerState *s) 45 { 46 int cpu_id = current_cpu ? current_cpu->cpu_index : 0; 47 48 if (cpu_id >= s->num_cpu) { 49 hw_error("arm_mptimer: num-cpu %d but this cpu is %d!\n", 50 s->num_cpu, cpu_id); 51 } 52 53 return cpu_id; 54 } 55 56 static inline void timerblock_update_irq(TimerBlock *tb) 57 { 58 qemu_set_irq(tb->irq, tb->status && (tb->control & 4)); 59 } 60 61 /* Return conversion factor from mpcore timer ticks to qemu timer ticks. */ 62 static inline uint32_t timerblock_scale(uint32_t control) 63 { 64 return (((control >> 8) & 0xff) + 1) * 10; 65 } 66 67 /* Must be called within a ptimer transaction block */ 68 static inline void timerblock_set_count(struct ptimer_state *timer, 69 uint32_t control, uint64_t *count) 70 { 71 /* PTimer would trigger interrupt for periodic timer when counter set 72 * to 0, MPtimer under certain condition only. 73 */ 74 if ((control & 3) == 3 && (control & 0xff00) == 0 && *count == 0) { 75 *count = ptimer_get_limit(timer); 76 } 77 ptimer_set_count(timer, *count); 78 } 79 80 /* Must be called within a ptimer transaction block */ 81 static inline void timerblock_run(struct ptimer_state *timer, 82 uint32_t control, uint32_t load) 83 { 84 if ((control & 1) && ((control & 0xff00) || load != 0)) { 85 ptimer_run(timer, !(control & 2)); 86 } 87 } 88 89 static void timerblock_tick(void *opaque) 90 { 91 TimerBlock *tb = (TimerBlock *)opaque; 92 /* Periodic timer with load = 0 and prescaler != 0 would re-trigger 93 * IRQ after one period, otherwise it either stops or wraps around. 94 */ 95 if ((tb->control & 2) && (tb->control & 0xff00) == 0 && 96 ptimer_get_limit(tb->timer) == 0) { 97 ptimer_stop(tb->timer); 98 } 99 tb->status = 1; 100 timerblock_update_irq(tb); 101 } 102 103 static uint64_t timerblock_read(void *opaque, hwaddr addr, 104 unsigned size) 105 { 106 TimerBlock *tb = (TimerBlock *)opaque; 107 switch (addr) { 108 case 0: /* Load */ 109 return ptimer_get_limit(tb->timer); 110 case 4: /* Counter. */ 111 return ptimer_get_count(tb->timer); 112 case 8: /* Control. */ 113 return tb->control; 114 case 12: /* Interrupt status. */ 115 return tb->status; 116 default: 117 return 0; 118 } 119 } 120 121 static void timerblock_write(void *opaque, hwaddr addr, 122 uint64_t value, unsigned size) 123 { 124 TimerBlock *tb = (TimerBlock *)opaque; 125 uint32_t control = tb->control; 126 switch (addr) { 127 case 0: /* Load */ 128 ptimer_transaction_begin(tb->timer); 129 /* Setting load to 0 stops the timer without doing the tick if 130 * prescaler = 0. 131 */ 132 if ((control & 1) && (control & 0xff00) == 0 && value == 0) { 133 ptimer_stop(tb->timer); 134 } 135 ptimer_set_limit(tb->timer, value, 1); 136 timerblock_run(tb->timer, control, value); 137 ptimer_transaction_commit(tb->timer); 138 break; 139 case 4: /* Counter. */ 140 ptimer_transaction_begin(tb->timer); 141 /* Setting counter to 0 stops the one-shot timer, or periodic with 142 * load = 0, without doing the tick if prescaler = 0. 143 */ 144 if ((control & 1) && (control & 0xff00) == 0 && value == 0 && 145 (!(control & 2) || ptimer_get_limit(tb->timer) == 0)) { 146 ptimer_stop(tb->timer); 147 } 148 timerblock_set_count(tb->timer, control, &value); 149 timerblock_run(tb->timer, control, value); 150 ptimer_transaction_commit(tb->timer); 151 break; 152 case 8: /* Control. */ 153 ptimer_transaction_begin(tb->timer); 154 if ((control & 3) != (value & 3)) { 155 ptimer_stop(tb->timer); 156 } 157 if ((control & 0xff00) != (value & 0xff00)) { 158 ptimer_set_period(tb->timer, timerblock_scale(value)); 159 } 160 if (value & 1) { 161 uint64_t count = ptimer_get_count(tb->timer); 162 /* Re-load periodic timer counter if needed. */ 163 if ((value & 2) && count == 0) { 164 timerblock_set_count(tb->timer, value, &count); 165 } 166 timerblock_run(tb->timer, value, count); 167 } 168 tb->control = value; 169 ptimer_transaction_commit(tb->timer); 170 break; 171 case 12: /* Interrupt status. */ 172 tb->status &= ~value; 173 timerblock_update_irq(tb); 174 break; 175 } 176 } 177 178 /* Wrapper functions to implement the "read timer/watchdog for 179 * the current CPU" memory regions. 180 */ 181 static uint64_t arm_thistimer_read(void *opaque, hwaddr addr, 182 unsigned size) 183 { 184 ARMMPTimerState *s = (ARMMPTimerState *)opaque; 185 int id = get_current_cpu(s); 186 return timerblock_read(&s->timerblock[id], addr, size); 187 } 188 189 static void arm_thistimer_write(void *opaque, hwaddr addr, 190 uint64_t value, unsigned size) 191 { 192 ARMMPTimerState *s = (ARMMPTimerState *)opaque; 193 int id = get_current_cpu(s); 194 timerblock_write(&s->timerblock[id], addr, value, size); 195 } 196 197 static const MemoryRegionOps arm_thistimer_ops = { 198 .read = arm_thistimer_read, 199 .write = arm_thistimer_write, 200 .valid = { 201 .min_access_size = 4, 202 .max_access_size = 4, 203 }, 204 .endianness = DEVICE_NATIVE_ENDIAN, 205 }; 206 207 static const MemoryRegionOps timerblock_ops = { 208 .read = timerblock_read, 209 .write = timerblock_write, 210 .valid = { 211 .min_access_size = 4, 212 .max_access_size = 4, 213 }, 214 .endianness = DEVICE_NATIVE_ENDIAN, 215 }; 216 217 static void timerblock_reset(TimerBlock *tb) 218 { 219 tb->control = 0; 220 tb->status = 0; 221 if (tb->timer) { 222 ptimer_transaction_begin(tb->timer); 223 ptimer_stop(tb->timer); 224 ptimer_set_limit(tb->timer, 0, 1); 225 ptimer_set_period(tb->timer, timerblock_scale(0)); 226 ptimer_transaction_commit(tb->timer); 227 } 228 } 229 230 static void arm_mptimer_reset(DeviceState *dev) 231 { 232 ARMMPTimerState *s = ARM_MPTIMER(dev); 233 int i; 234 235 for (i = 0; i < ARRAY_SIZE(s->timerblock); i++) { 236 timerblock_reset(&s->timerblock[i]); 237 } 238 } 239 240 static void arm_mptimer_init(Object *obj) 241 { 242 ARMMPTimerState *s = ARM_MPTIMER(obj); 243 244 memory_region_init_io(&s->iomem, obj, &arm_thistimer_ops, s, 245 "arm_mptimer_timer", 0x20); 246 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem); 247 } 248 249 static void arm_mptimer_realize(DeviceState *dev, Error **errp) 250 { 251 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 252 ARMMPTimerState *s = ARM_MPTIMER(dev); 253 int i; 254 255 if (s->num_cpu < 1 || s->num_cpu > ARM_MPTIMER_MAX_CPUS) { 256 error_setg(errp, "num-cpu must be between 1 and %d", 257 ARM_MPTIMER_MAX_CPUS); 258 return; 259 } 260 /* We implement one timer block per CPU, and expose multiple MMIO regions: 261 * * region 0 is "timer for this core" 262 * * region 1 is "timer for core 0" 263 * * region 2 is "timer for core 1" 264 * and so on. 265 * The outgoing interrupt lines are 266 * * timer for core 0 267 * * timer for core 1 268 * and so on. 269 */ 270 for (i = 0; i < s->num_cpu; i++) { 271 TimerBlock *tb = &s->timerblock[i]; 272 tb->timer = ptimer_init(timerblock_tick, tb, PTIMER_POLICY); 273 sysbus_init_irq(sbd, &tb->irq); 274 memory_region_init_io(&tb->iomem, OBJECT(s), &timerblock_ops, tb, 275 "arm_mptimer_timerblock", 0x20); 276 sysbus_init_mmio(sbd, &tb->iomem); 277 } 278 } 279 280 static const VMStateDescription vmstate_timerblock = { 281 .name = "arm_mptimer_timerblock", 282 .version_id = 3, 283 .minimum_version_id = 3, 284 .fields = (VMStateField[]) { 285 VMSTATE_UINT32(control, TimerBlock), 286 VMSTATE_UINT32(status, TimerBlock), 287 VMSTATE_PTIMER(timer, TimerBlock), 288 VMSTATE_END_OF_LIST() 289 } 290 }; 291 292 static const VMStateDescription vmstate_arm_mptimer = { 293 .name = "arm_mptimer", 294 .version_id = 3, 295 .minimum_version_id = 3, 296 .fields = (VMStateField[]) { 297 VMSTATE_STRUCT_VARRAY_UINT32(timerblock, ARMMPTimerState, num_cpu, 298 3, vmstate_timerblock, TimerBlock), 299 VMSTATE_END_OF_LIST() 300 } 301 }; 302 303 static Property arm_mptimer_properties[] = { 304 DEFINE_PROP_UINT32("num-cpu", ARMMPTimerState, num_cpu, 0), 305 DEFINE_PROP_END_OF_LIST() 306 }; 307 308 static void arm_mptimer_class_init(ObjectClass *klass, void *data) 309 { 310 DeviceClass *dc = DEVICE_CLASS(klass); 311 312 dc->realize = arm_mptimer_realize; 313 dc->vmsd = &vmstate_arm_mptimer; 314 dc->reset = arm_mptimer_reset; 315 dc->props = arm_mptimer_properties; 316 } 317 318 static const TypeInfo arm_mptimer_info = { 319 .name = TYPE_ARM_MPTIMER, 320 .parent = TYPE_SYS_BUS_DEVICE, 321 .instance_size = sizeof(ARMMPTimerState), 322 .instance_init = arm_mptimer_init, 323 .class_init = arm_mptimer_class_init, 324 }; 325 326 static void arm_mptimer_register_types(void) 327 { 328 type_register_static(&arm_mptimer_info); 329 } 330 331 type_init(arm_mptimer_register_types) 332