1 /* 2 * Allwinner A10 timer device emulation 3 * 4 * Copyright (C) 2013 Li Guang 5 * Written by Li Guang <lig.fnst@cn.fujitsu.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15 * for more details. 16 */ 17 18 #include "qemu/osdep.h" 19 #include "hw/irq.h" 20 #include "hw/sysbus.h" 21 #include "sysemu/sysemu.h" 22 #include "hw/timer/allwinner-a10-pit.h" 23 #include "migration/vmstate.h" 24 #include "qemu/log.h" 25 #include "qemu/module.h" 26 27 static void a10_pit_update_irq(AwA10PITState *s) 28 { 29 int i; 30 31 for (i = 0; i < AW_A10_PIT_TIMER_NR; i++) { 32 qemu_set_irq(s->irq[i], !!(s->irq_status & s->irq_enable & (1 << i))); 33 } 34 } 35 36 static uint64_t a10_pit_read(void *opaque, hwaddr offset, unsigned size) 37 { 38 AwA10PITState *s = AW_A10_PIT(opaque); 39 uint8_t index; 40 41 switch (offset) { 42 case AW_A10_PIT_TIMER_IRQ_EN: 43 return s->irq_enable; 44 case AW_A10_PIT_TIMER_IRQ_ST: 45 return s->irq_status; 46 case AW_A10_PIT_TIMER_BASE ... AW_A10_PIT_TIMER_BASE_END: 47 index = offset & 0xf0; 48 index >>= 4; 49 index -= 1; 50 switch (offset & 0x0f) { 51 case AW_A10_PIT_TIMER_CONTROL: 52 return s->control[index]; 53 case AW_A10_PIT_TIMER_INTERVAL: 54 return s->interval[index]; 55 case AW_A10_PIT_TIMER_COUNT: 56 s->count[index] = ptimer_get_count(s->timer[index]); 57 return s->count[index]; 58 default: 59 qemu_log_mask(LOG_GUEST_ERROR, 60 "%s: Bad offset 0x%x\n", __func__, (int)offset); 61 break; 62 } 63 case AW_A10_PIT_WDOG_CONTROL: 64 break; 65 case AW_A10_PIT_WDOG_MODE: 66 break; 67 case AW_A10_PIT_COUNT_LO: 68 return s->count_lo; 69 case AW_A10_PIT_COUNT_HI: 70 return s->count_hi; 71 case AW_A10_PIT_COUNT_CTL: 72 return s->count_ctl; 73 default: 74 qemu_log_mask(LOG_GUEST_ERROR, 75 "%s: Bad offset 0x%x\n", __func__, (int)offset); 76 break; 77 } 78 79 return 0; 80 } 81 82 static void a10_pit_set_freq(AwA10PITState *s, int index) 83 { 84 uint32_t prescaler, source, source_freq; 85 86 prescaler = 1 << extract32(s->control[index], 4, 3); 87 source = extract32(s->control[index], 2, 2); 88 source_freq = s->clk_freq[source]; 89 90 if (source_freq) { 91 ptimer_set_freq(s->timer[index], source_freq / prescaler); 92 } else { 93 qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid clock source %u\n", 94 __func__, source); 95 } 96 } 97 98 static void a10_pit_write(void *opaque, hwaddr offset, uint64_t value, 99 unsigned size) 100 { 101 AwA10PITState *s = AW_A10_PIT(opaque); 102 uint8_t index; 103 104 switch (offset) { 105 case AW_A10_PIT_TIMER_IRQ_EN: 106 s->irq_enable = value; 107 a10_pit_update_irq(s); 108 break; 109 case AW_A10_PIT_TIMER_IRQ_ST: 110 s->irq_status &= ~value; 111 a10_pit_update_irq(s); 112 break; 113 case AW_A10_PIT_TIMER_BASE ... AW_A10_PIT_TIMER_BASE_END: 114 index = offset & 0xf0; 115 index >>= 4; 116 index -= 1; 117 switch (offset & 0x0f) { 118 case AW_A10_PIT_TIMER_CONTROL: 119 s->control[index] = value; 120 a10_pit_set_freq(s, index); 121 if (s->control[index] & AW_A10_PIT_TIMER_RELOAD) { 122 ptimer_set_count(s->timer[index], s->interval[index]); 123 } 124 if (s->control[index] & AW_A10_PIT_TIMER_EN) { 125 int oneshot = 0; 126 if (s->control[index] & AW_A10_PIT_TIMER_MODE) { 127 oneshot = 1; 128 } 129 ptimer_run(s->timer[index], oneshot); 130 } else { 131 ptimer_stop(s->timer[index]); 132 } 133 break; 134 case AW_A10_PIT_TIMER_INTERVAL: 135 s->interval[index] = value; 136 ptimer_set_limit(s->timer[index], s->interval[index], 1); 137 break; 138 case AW_A10_PIT_TIMER_COUNT: 139 s->count[index] = value; 140 break; 141 default: 142 qemu_log_mask(LOG_GUEST_ERROR, 143 "%s: Bad offset 0x%x\n", __func__, (int)offset); 144 } 145 break; 146 case AW_A10_PIT_WDOG_CONTROL: 147 s->watch_dog_control = value; 148 break; 149 case AW_A10_PIT_WDOG_MODE: 150 s->watch_dog_mode = value; 151 break; 152 case AW_A10_PIT_COUNT_LO: 153 s->count_lo = value; 154 break; 155 case AW_A10_PIT_COUNT_HI: 156 s->count_hi = value; 157 break; 158 case AW_A10_PIT_COUNT_CTL: 159 s->count_ctl = value; 160 if (s->count_ctl & AW_A10_PIT_COUNT_RL_EN) { 161 uint64_t tmp_count = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 162 163 s->count_lo = tmp_count; 164 s->count_hi = tmp_count >> 32; 165 s->count_ctl &= ~AW_A10_PIT_COUNT_RL_EN; 166 } 167 if (s->count_ctl & AW_A10_PIT_COUNT_CLR_EN) { 168 s->count_lo = 0; 169 s->count_hi = 0; 170 s->count_ctl &= ~AW_A10_PIT_COUNT_CLR_EN; 171 } 172 break; 173 default: 174 qemu_log_mask(LOG_GUEST_ERROR, 175 "%s: Bad offset 0x%x\n", __func__, (int)offset); 176 break; 177 } 178 } 179 180 static const MemoryRegionOps a10_pit_ops = { 181 .read = a10_pit_read, 182 .write = a10_pit_write, 183 .endianness = DEVICE_NATIVE_ENDIAN, 184 }; 185 186 static Property a10_pit_properties[] = { 187 DEFINE_PROP_UINT32("clk0-freq", AwA10PITState, clk_freq[0], 0), 188 DEFINE_PROP_UINT32("clk1-freq", AwA10PITState, clk_freq[1], 0), 189 DEFINE_PROP_UINT32("clk2-freq", AwA10PITState, clk_freq[2], 0), 190 DEFINE_PROP_UINT32("clk3-freq", AwA10PITState, clk_freq[3], 0), 191 DEFINE_PROP_END_OF_LIST(), 192 }; 193 194 static const VMStateDescription vmstate_a10_pit = { 195 .name = "a10.pit", 196 .version_id = 1, 197 .minimum_version_id = 1, 198 .fields = (VMStateField[]) { 199 VMSTATE_UINT32(irq_enable, AwA10PITState), 200 VMSTATE_UINT32(irq_status, AwA10PITState), 201 VMSTATE_UINT32_ARRAY(control, AwA10PITState, AW_A10_PIT_TIMER_NR), 202 VMSTATE_UINT32_ARRAY(interval, AwA10PITState, AW_A10_PIT_TIMER_NR), 203 VMSTATE_UINT32_ARRAY(count, AwA10PITState, AW_A10_PIT_TIMER_NR), 204 VMSTATE_UINT32(watch_dog_mode, AwA10PITState), 205 VMSTATE_UINT32(watch_dog_control, AwA10PITState), 206 VMSTATE_UINT32(count_lo, AwA10PITState), 207 VMSTATE_UINT32(count_hi, AwA10PITState), 208 VMSTATE_UINT32(count_ctl, AwA10PITState), 209 VMSTATE_PTIMER_ARRAY(timer, AwA10PITState, AW_A10_PIT_TIMER_NR), 210 VMSTATE_END_OF_LIST() 211 } 212 }; 213 214 static void a10_pit_reset(DeviceState *dev) 215 { 216 AwA10PITState *s = AW_A10_PIT(dev); 217 uint8_t i; 218 219 s->irq_enable = 0; 220 s->irq_status = 0; 221 a10_pit_update_irq(s); 222 223 for (i = 0; i < 6; i++) { 224 s->control[i] = AW_A10_PIT_DEFAULT_CLOCK; 225 s->interval[i] = 0; 226 s->count[i] = 0; 227 ptimer_stop(s->timer[i]); 228 a10_pit_set_freq(s, i); 229 } 230 s->watch_dog_mode = 0; 231 s->watch_dog_control = 0; 232 s->count_lo = 0; 233 s->count_hi = 0; 234 s->count_ctl = 0; 235 } 236 237 static void a10_pit_timer_cb(void *opaque) 238 { 239 AwA10TimerContext *tc = opaque; 240 AwA10PITState *s = tc->container; 241 uint8_t i = tc->index; 242 243 if (s->control[i] & AW_A10_PIT_TIMER_EN) { 244 s->irq_status |= 1 << i; 245 if (s->control[i] & AW_A10_PIT_TIMER_MODE) { 246 ptimer_stop(s->timer[i]); 247 s->control[i] &= ~AW_A10_PIT_TIMER_EN; 248 } 249 a10_pit_update_irq(s); 250 } 251 } 252 253 static void a10_pit_init(Object *obj) 254 { 255 AwA10PITState *s = AW_A10_PIT(obj); 256 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 257 QEMUBH * bh[AW_A10_PIT_TIMER_NR]; 258 uint8_t i; 259 260 for (i = 0; i < AW_A10_PIT_TIMER_NR; i++) { 261 sysbus_init_irq(sbd, &s->irq[i]); 262 } 263 memory_region_init_io(&s->iomem, OBJECT(s), &a10_pit_ops, s, 264 TYPE_AW_A10_PIT, 0x400); 265 sysbus_init_mmio(sbd, &s->iomem); 266 267 for (i = 0; i < AW_A10_PIT_TIMER_NR; i++) { 268 AwA10TimerContext *tc = &s->timer_context[i]; 269 270 tc->container = s; 271 tc->index = i; 272 bh[i] = qemu_bh_new(a10_pit_timer_cb, tc); 273 s->timer[i] = ptimer_init(bh[i], PTIMER_POLICY_DEFAULT); 274 } 275 } 276 277 static void a10_pit_class_init(ObjectClass *klass, void *data) 278 { 279 DeviceClass *dc = DEVICE_CLASS(klass); 280 281 dc->reset = a10_pit_reset; 282 dc->props = a10_pit_properties; 283 dc->desc = "allwinner a10 timer"; 284 dc->vmsd = &vmstate_a10_pit; 285 } 286 287 static const TypeInfo a10_pit_info = { 288 .name = TYPE_AW_A10_PIT, 289 .parent = TYPE_SYS_BUS_DEVICE, 290 .instance_size = sizeof(AwA10PITState), 291 .instance_init = a10_pit_init, 292 .class_init = a10_pit_class_init, 293 }; 294 295 static void a10_register_types(void) 296 { 297 type_register_static(&a10_pit_info); 298 } 299 300 type_init(a10_register_types); 301