1 /* 2 * Allwinner A10 timer device emulation 3 * 4 * Copyright (C) 2013 Li Guang 5 * Written by Li Guang <lig.fnst@cn.fujitsu.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15 * for more details. 16 */ 17 18 #include "qemu/osdep.h" 19 #include "hw/sysbus.h" 20 #include "sysemu/sysemu.h" 21 #include "hw/timer/allwinner-a10-pit.h" 22 #include "qemu/log.h" 23 24 static void a10_pit_update_irq(AwA10PITState *s) 25 { 26 int i; 27 28 for (i = 0; i < AW_A10_PIT_TIMER_NR; i++) { 29 qemu_set_irq(s->irq[i], !!(s->irq_status & s->irq_enable & (1 << i))); 30 } 31 } 32 33 static uint64_t a10_pit_read(void *opaque, hwaddr offset, unsigned size) 34 { 35 AwA10PITState *s = AW_A10_PIT(opaque); 36 uint8_t index; 37 38 switch (offset) { 39 case AW_A10_PIT_TIMER_IRQ_EN: 40 return s->irq_enable; 41 case AW_A10_PIT_TIMER_IRQ_ST: 42 return s->irq_status; 43 case AW_A10_PIT_TIMER_BASE ... AW_A10_PIT_TIMER_BASE_END: 44 index = offset & 0xf0; 45 index >>= 4; 46 index -= 1; 47 switch (offset & 0x0f) { 48 case AW_A10_PIT_TIMER_CONTROL: 49 return s->control[index]; 50 case AW_A10_PIT_TIMER_INTERVAL: 51 return s->interval[index]; 52 case AW_A10_PIT_TIMER_COUNT: 53 s->count[index] = ptimer_get_count(s->timer[index]); 54 return s->count[index]; 55 default: 56 qemu_log_mask(LOG_GUEST_ERROR, 57 "%s: Bad offset 0x%x\n", __func__, (int)offset); 58 break; 59 } 60 case AW_A10_PIT_WDOG_CONTROL: 61 break; 62 case AW_A10_PIT_WDOG_MODE: 63 break; 64 case AW_A10_PIT_COUNT_LO: 65 return s->count_lo; 66 case AW_A10_PIT_COUNT_HI: 67 return s->count_hi; 68 case AW_A10_PIT_COUNT_CTL: 69 return s->count_ctl; 70 default: 71 qemu_log_mask(LOG_GUEST_ERROR, 72 "%s: Bad offset 0x%x\n", __func__, (int)offset); 73 break; 74 } 75 76 return 0; 77 } 78 79 static void a10_pit_set_freq(AwA10PITState *s, int index) 80 { 81 uint32_t prescaler, source, source_freq; 82 83 prescaler = 1 << extract32(s->control[index], 4, 3); 84 source = extract32(s->control[index], 2, 2); 85 source_freq = s->clk_freq[source]; 86 87 if (source_freq) { 88 ptimer_set_freq(s->timer[index], source_freq / prescaler); 89 } else { 90 qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid clock source %u\n", 91 __func__, source); 92 } 93 } 94 95 static void a10_pit_write(void *opaque, hwaddr offset, uint64_t value, 96 unsigned size) 97 { 98 AwA10PITState *s = AW_A10_PIT(opaque); 99 uint8_t index; 100 101 switch (offset) { 102 case AW_A10_PIT_TIMER_IRQ_EN: 103 s->irq_enable = value; 104 a10_pit_update_irq(s); 105 break; 106 case AW_A10_PIT_TIMER_IRQ_ST: 107 s->irq_status &= ~value; 108 a10_pit_update_irq(s); 109 break; 110 case AW_A10_PIT_TIMER_BASE ... AW_A10_PIT_TIMER_BASE_END: 111 index = offset & 0xf0; 112 index >>= 4; 113 index -= 1; 114 switch (offset & 0x0f) { 115 case AW_A10_PIT_TIMER_CONTROL: 116 s->control[index] = value; 117 a10_pit_set_freq(s, index); 118 if (s->control[index] & AW_A10_PIT_TIMER_RELOAD) { 119 ptimer_set_count(s->timer[index], s->interval[index]); 120 } 121 if (s->control[index] & AW_A10_PIT_TIMER_EN) { 122 int oneshot = 0; 123 if (s->control[index] & AW_A10_PIT_TIMER_MODE) { 124 oneshot = 1; 125 } 126 ptimer_run(s->timer[index], oneshot); 127 } else { 128 ptimer_stop(s->timer[index]); 129 } 130 break; 131 case AW_A10_PIT_TIMER_INTERVAL: 132 s->interval[index] = value; 133 ptimer_set_limit(s->timer[index], s->interval[index], 1); 134 break; 135 case AW_A10_PIT_TIMER_COUNT: 136 s->count[index] = value; 137 break; 138 default: 139 qemu_log_mask(LOG_GUEST_ERROR, 140 "%s: Bad offset 0x%x\n", __func__, (int)offset); 141 } 142 break; 143 case AW_A10_PIT_WDOG_CONTROL: 144 s->watch_dog_control = value; 145 break; 146 case AW_A10_PIT_WDOG_MODE: 147 s->watch_dog_mode = value; 148 break; 149 case AW_A10_PIT_COUNT_LO: 150 s->count_lo = value; 151 break; 152 case AW_A10_PIT_COUNT_HI: 153 s->count_hi = value; 154 break; 155 case AW_A10_PIT_COUNT_CTL: 156 s->count_ctl = value; 157 if (s->count_ctl & AW_A10_PIT_COUNT_RL_EN) { 158 uint64_t tmp_count = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 159 160 s->count_lo = tmp_count; 161 s->count_hi = tmp_count >> 32; 162 s->count_ctl &= ~AW_A10_PIT_COUNT_RL_EN; 163 } 164 if (s->count_ctl & AW_A10_PIT_COUNT_CLR_EN) { 165 s->count_lo = 0; 166 s->count_hi = 0; 167 s->count_ctl &= ~AW_A10_PIT_COUNT_CLR_EN; 168 } 169 break; 170 default: 171 qemu_log_mask(LOG_GUEST_ERROR, 172 "%s: Bad offset 0x%x\n", __func__, (int)offset); 173 break; 174 } 175 } 176 177 static const MemoryRegionOps a10_pit_ops = { 178 .read = a10_pit_read, 179 .write = a10_pit_write, 180 .endianness = DEVICE_NATIVE_ENDIAN, 181 }; 182 183 static Property a10_pit_properties[] = { 184 DEFINE_PROP_UINT32("clk0-freq", AwA10PITState, clk_freq[0], 0), 185 DEFINE_PROP_UINT32("clk1-freq", AwA10PITState, clk_freq[1], 0), 186 DEFINE_PROP_UINT32("clk2-freq", AwA10PITState, clk_freq[2], 0), 187 DEFINE_PROP_UINT32("clk3-freq", AwA10PITState, clk_freq[3], 0), 188 DEFINE_PROP_END_OF_LIST(), 189 }; 190 191 static const VMStateDescription vmstate_a10_pit = { 192 .name = "a10.pit", 193 .version_id = 1, 194 .minimum_version_id = 1, 195 .fields = (VMStateField[]) { 196 VMSTATE_UINT32(irq_enable, AwA10PITState), 197 VMSTATE_UINT32(irq_status, AwA10PITState), 198 VMSTATE_UINT32_ARRAY(control, AwA10PITState, AW_A10_PIT_TIMER_NR), 199 VMSTATE_UINT32_ARRAY(interval, AwA10PITState, AW_A10_PIT_TIMER_NR), 200 VMSTATE_UINT32_ARRAY(count, AwA10PITState, AW_A10_PIT_TIMER_NR), 201 VMSTATE_UINT32(watch_dog_mode, AwA10PITState), 202 VMSTATE_UINT32(watch_dog_control, AwA10PITState), 203 VMSTATE_UINT32(count_lo, AwA10PITState), 204 VMSTATE_UINT32(count_hi, AwA10PITState), 205 VMSTATE_UINT32(count_ctl, AwA10PITState), 206 VMSTATE_PTIMER_ARRAY(timer, AwA10PITState, AW_A10_PIT_TIMER_NR), 207 VMSTATE_END_OF_LIST() 208 } 209 }; 210 211 static void a10_pit_reset(DeviceState *dev) 212 { 213 AwA10PITState *s = AW_A10_PIT(dev); 214 uint8_t i; 215 216 s->irq_enable = 0; 217 s->irq_status = 0; 218 a10_pit_update_irq(s); 219 220 for (i = 0; i < 6; i++) { 221 s->control[i] = AW_A10_PIT_DEFAULT_CLOCK; 222 s->interval[i] = 0; 223 s->count[i] = 0; 224 ptimer_stop(s->timer[i]); 225 a10_pit_set_freq(s, i); 226 } 227 s->watch_dog_mode = 0; 228 s->watch_dog_control = 0; 229 s->count_lo = 0; 230 s->count_hi = 0; 231 s->count_ctl = 0; 232 } 233 234 static void a10_pit_timer_cb(void *opaque) 235 { 236 AwA10TimerContext *tc = opaque; 237 AwA10PITState *s = tc->container; 238 uint8_t i = tc->index; 239 240 if (s->control[i] & AW_A10_PIT_TIMER_EN) { 241 s->irq_status |= 1 << i; 242 if (s->control[i] & AW_A10_PIT_TIMER_MODE) { 243 ptimer_stop(s->timer[i]); 244 s->control[i] &= ~AW_A10_PIT_TIMER_EN; 245 } 246 a10_pit_update_irq(s); 247 } 248 } 249 250 static void a10_pit_init(Object *obj) 251 { 252 AwA10PITState *s = AW_A10_PIT(obj); 253 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 254 QEMUBH * bh[AW_A10_PIT_TIMER_NR]; 255 uint8_t i; 256 257 for (i = 0; i < AW_A10_PIT_TIMER_NR; i++) { 258 sysbus_init_irq(sbd, &s->irq[i]); 259 } 260 memory_region_init_io(&s->iomem, OBJECT(s), &a10_pit_ops, s, 261 TYPE_AW_A10_PIT, 0x400); 262 sysbus_init_mmio(sbd, &s->iomem); 263 264 for (i = 0; i < AW_A10_PIT_TIMER_NR; i++) { 265 AwA10TimerContext *tc = &s->timer_context[i]; 266 267 tc->container = s; 268 tc->index = i; 269 bh[i] = qemu_bh_new(a10_pit_timer_cb, tc); 270 s->timer[i] = ptimer_init(bh[i], PTIMER_POLICY_DEFAULT); 271 } 272 } 273 274 static void a10_pit_class_init(ObjectClass *klass, void *data) 275 { 276 DeviceClass *dc = DEVICE_CLASS(klass); 277 278 dc->reset = a10_pit_reset; 279 dc->props = a10_pit_properties; 280 dc->desc = "allwinner a10 timer"; 281 dc->vmsd = &vmstate_a10_pit; 282 } 283 284 static const TypeInfo a10_pit_info = { 285 .name = TYPE_AW_A10_PIT, 286 .parent = TYPE_SYS_BUS_DEVICE, 287 .instance_size = sizeof(AwA10PITState), 288 .instance_init = a10_pit_init, 289 .class_init = a10_pit_class_init, 290 }; 291 292 static void a10_register_types(void) 293 { 294 type_register_static(&a10_pit_info); 295 } 296 297 type_init(a10_register_types); 298