1 /* 2 * Allwinner A10 timer device emulation 3 * 4 * Copyright (C) 2013 Li Guang 5 * Written by Li Guang <lig.fnst@cn.fujitsu.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15 * for more details. 16 */ 17 18 #include "hw/sysbus.h" 19 #include "sysemu/sysemu.h" 20 #include "hw/timer/allwinner-a10-pit.h" 21 22 static void a10_pit_update_irq(AwA10PITState *s) 23 { 24 int i; 25 26 for (i = 0; i < AW_A10_PIT_TIMER_NR; i++) { 27 qemu_set_irq(s->irq[i], !!(s->irq_status & s->irq_enable & (1 << i))); 28 } 29 } 30 31 static uint64_t a10_pit_read(void *opaque, hwaddr offset, unsigned size) 32 { 33 AwA10PITState *s = AW_A10_PIT(opaque); 34 uint8_t index; 35 36 switch (offset) { 37 case AW_A10_PIT_TIMER_IRQ_EN: 38 return s->irq_enable; 39 case AW_A10_PIT_TIMER_IRQ_ST: 40 return s->irq_status; 41 case AW_A10_PIT_TIMER_BASE ... AW_A10_PIT_TIMER_BASE_END: 42 index = offset & 0xf0; 43 index >>= 4; 44 index -= 1; 45 switch (offset & 0x0f) { 46 case AW_A10_PIT_TIMER_CONTROL: 47 return s->control[index]; 48 case AW_A10_PIT_TIMER_INTERVAL: 49 return s->interval[index]; 50 case AW_A10_PIT_TIMER_COUNT: 51 s->count[index] = ptimer_get_count(s->timer[index]); 52 return s->count[index]; 53 default: 54 qemu_log_mask(LOG_GUEST_ERROR, 55 "%s: Bad offset 0x%x\n", __func__, (int)offset); 56 break; 57 } 58 case AW_A10_PIT_WDOG_CONTROL: 59 break; 60 case AW_A10_PIT_WDOG_MODE: 61 break; 62 case AW_A10_PIT_COUNT_LO: 63 return s->count_lo; 64 case AW_A10_PIT_COUNT_HI: 65 return s->count_hi; 66 case AW_A10_PIT_COUNT_CTL: 67 return s->count_ctl; 68 default: 69 qemu_log_mask(LOG_GUEST_ERROR, 70 "%s: Bad offset 0x%x\n", __func__, (int)offset); 71 break; 72 } 73 74 return 0; 75 } 76 77 static void a10_pit_set_freq(AwA10PITState *s, int index) 78 { 79 uint32_t prescaler, source, source_freq; 80 81 prescaler = 1 << extract32(s->control[index], 4, 3); 82 source = extract32(s->control[index], 2, 2); 83 source_freq = s->clk_freq[source]; 84 85 if (source_freq) { 86 ptimer_set_freq(s->timer[index], source_freq / prescaler); 87 } else { 88 qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid clock source %u\n", 89 __func__, source); 90 } 91 } 92 93 static void a10_pit_write(void *opaque, hwaddr offset, uint64_t value, 94 unsigned size) 95 { 96 AwA10PITState *s = AW_A10_PIT(opaque); 97 uint8_t index; 98 99 switch (offset) { 100 case AW_A10_PIT_TIMER_IRQ_EN: 101 s->irq_enable = value; 102 a10_pit_update_irq(s); 103 break; 104 case AW_A10_PIT_TIMER_IRQ_ST: 105 s->irq_status &= ~value; 106 a10_pit_update_irq(s); 107 break; 108 case AW_A10_PIT_TIMER_BASE ... AW_A10_PIT_TIMER_BASE_END: 109 index = offset & 0xf0; 110 index >>= 4; 111 index -= 1; 112 switch (offset & 0x0f) { 113 case AW_A10_PIT_TIMER_CONTROL: 114 s->control[index] = value; 115 a10_pit_set_freq(s, index); 116 if (s->control[index] & AW_A10_PIT_TIMER_RELOAD) { 117 ptimer_set_count(s->timer[index], s->interval[index]); 118 } 119 if (s->control[index] & AW_A10_PIT_TIMER_EN) { 120 int oneshot = 0; 121 if (s->control[index] & AW_A10_PIT_TIMER_MODE) { 122 oneshot = 1; 123 } 124 ptimer_run(s->timer[index], oneshot); 125 } else { 126 ptimer_stop(s->timer[index]); 127 } 128 break; 129 case AW_A10_PIT_TIMER_INTERVAL: 130 s->interval[index] = value; 131 ptimer_set_limit(s->timer[index], s->interval[index], 1); 132 break; 133 case AW_A10_PIT_TIMER_COUNT: 134 s->count[index] = value; 135 break; 136 default: 137 qemu_log_mask(LOG_GUEST_ERROR, 138 "%s: Bad offset 0x%x\n", __func__, (int)offset); 139 } 140 break; 141 case AW_A10_PIT_WDOG_CONTROL: 142 s->watch_dog_control = value; 143 break; 144 case AW_A10_PIT_WDOG_MODE: 145 s->watch_dog_mode = value; 146 break; 147 case AW_A10_PIT_COUNT_LO: 148 s->count_lo = value; 149 break; 150 case AW_A10_PIT_COUNT_HI: 151 s->count_hi = value; 152 break; 153 case AW_A10_PIT_COUNT_CTL: 154 s->count_ctl = value; 155 if (s->count_ctl & AW_A10_PIT_COUNT_RL_EN) { 156 uint64_t tmp_count = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 157 158 s->count_lo = tmp_count; 159 s->count_hi = tmp_count >> 32; 160 s->count_ctl &= ~AW_A10_PIT_COUNT_RL_EN; 161 } 162 if (s->count_ctl & AW_A10_PIT_COUNT_CLR_EN) { 163 s->count_lo = 0; 164 s->count_hi = 0; 165 s->count_ctl &= ~AW_A10_PIT_COUNT_CLR_EN; 166 } 167 break; 168 default: 169 qemu_log_mask(LOG_GUEST_ERROR, 170 "%s: Bad offset 0x%x\n", __func__, (int)offset); 171 break; 172 } 173 } 174 175 static const MemoryRegionOps a10_pit_ops = { 176 .read = a10_pit_read, 177 .write = a10_pit_write, 178 .endianness = DEVICE_NATIVE_ENDIAN, 179 }; 180 181 static Property a10_pit_properties[] = { 182 DEFINE_PROP_UINT32("clk0-freq", AwA10PITState, clk_freq[0], 0), 183 DEFINE_PROP_UINT32("clk1-freq", AwA10PITState, clk_freq[1], 0), 184 DEFINE_PROP_UINT32("clk2-freq", AwA10PITState, clk_freq[2], 0), 185 DEFINE_PROP_UINT32("clk3-freq", AwA10PITState, clk_freq[3], 0), 186 DEFINE_PROP_END_OF_LIST(), 187 }; 188 189 static const VMStateDescription vmstate_a10_pit = { 190 .name = "a10.pit", 191 .version_id = 1, 192 .minimum_version_id = 1, 193 .minimum_version_id_old = 1, 194 .fields = (VMStateField[]) { 195 VMSTATE_UINT32(irq_enable, AwA10PITState), 196 VMSTATE_UINT32(irq_status, AwA10PITState), 197 VMSTATE_UINT32_ARRAY(control, AwA10PITState, AW_A10_PIT_TIMER_NR), 198 VMSTATE_UINT32_ARRAY(interval, AwA10PITState, AW_A10_PIT_TIMER_NR), 199 VMSTATE_UINT32_ARRAY(count, AwA10PITState, AW_A10_PIT_TIMER_NR), 200 VMSTATE_UINT32(watch_dog_mode, AwA10PITState), 201 VMSTATE_UINT32(watch_dog_control, AwA10PITState), 202 VMSTATE_UINT32(count_lo, AwA10PITState), 203 VMSTATE_UINT32(count_hi, AwA10PITState), 204 VMSTATE_UINT32(count_ctl, AwA10PITState), 205 VMSTATE_PTIMER_ARRAY(timer, AwA10PITState, AW_A10_PIT_TIMER_NR), 206 VMSTATE_END_OF_LIST() 207 } 208 }; 209 210 static void a10_pit_reset(DeviceState *dev) 211 { 212 AwA10PITState *s = AW_A10_PIT(dev); 213 uint8_t i; 214 215 s->irq_enable = 0; 216 s->irq_status = 0; 217 a10_pit_update_irq(s); 218 219 for (i = 0; i < 6; i++) { 220 s->control[i] = AW_A10_PIT_DEFAULT_CLOCK; 221 s->interval[i] = 0; 222 s->count[i] = 0; 223 ptimer_stop(s->timer[i]); 224 a10_pit_set_freq(s, i); 225 } 226 s->watch_dog_mode = 0; 227 s->watch_dog_control = 0; 228 s->count_lo = 0; 229 s->count_hi = 0; 230 s->count_ctl = 0; 231 } 232 233 static void a10_pit_timer_cb(void *opaque) 234 { 235 AwA10TimerContext *tc = opaque; 236 AwA10PITState *s = tc->container; 237 uint8_t i = tc->index; 238 239 if (s->control[i] & AW_A10_PIT_TIMER_EN) { 240 s->irq_status |= 1 << i; 241 if (s->control[i] & AW_A10_PIT_TIMER_MODE) { 242 ptimer_stop(s->timer[i]); 243 s->control[i] &= ~AW_A10_PIT_TIMER_EN; 244 } 245 a10_pit_update_irq(s); 246 } 247 } 248 249 static void a10_pit_init(Object *obj) 250 { 251 AwA10PITState *s = AW_A10_PIT(obj); 252 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 253 QEMUBH * bh[AW_A10_PIT_TIMER_NR]; 254 uint8_t i; 255 256 for (i = 0; i < AW_A10_PIT_TIMER_NR; i++) { 257 sysbus_init_irq(sbd, &s->irq[i]); 258 } 259 memory_region_init_io(&s->iomem, OBJECT(s), &a10_pit_ops, s, 260 TYPE_AW_A10_PIT, 0x400); 261 sysbus_init_mmio(sbd, &s->iomem); 262 263 for (i = 0; i < AW_A10_PIT_TIMER_NR; i++) { 264 AwA10TimerContext *tc = &s->timer_context[i]; 265 266 tc->container = s; 267 tc->index = i; 268 bh[i] = qemu_bh_new(a10_pit_timer_cb, tc); 269 s->timer[i] = ptimer_init(bh[i]); 270 } 271 } 272 273 static void a10_pit_class_init(ObjectClass *klass, void *data) 274 { 275 DeviceClass *dc = DEVICE_CLASS(klass); 276 277 dc->reset = a10_pit_reset; 278 dc->props = a10_pit_properties; 279 dc->desc = "allwinner a10 timer"; 280 dc->vmsd = &vmstate_a10_pit; 281 } 282 283 static const TypeInfo a10_pit_info = { 284 .name = TYPE_AW_A10_PIT, 285 .parent = TYPE_SYS_BUS_DEVICE, 286 .instance_size = sizeof(AwA10PITState), 287 .instance_init = a10_pit_init, 288 .class_init = a10_pit_class_init, 289 }; 290 291 static void a10_register_types(void) 292 { 293 type_register_static(&a10_pit_info); 294 } 295 296 type_init(a10_register_types); 297