1 /* 2 * QEMU model of the Xilinx Zynq SPI controller 3 * 4 * Copyright (c) 2012 Peter A. G. Crosthwaite 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "hw/sysbus.h" 26 #include "sysemu/sysemu.h" 27 #include "hw/ptimer.h" 28 #include "qemu/log.h" 29 #include "qemu/fifo8.h" 30 #include "hw/ssi/ssi.h" 31 #include "qemu/bitops.h" 32 #include "hw/ssi/xilinx_spips.h" 33 34 #ifndef XILINX_SPIPS_ERR_DEBUG 35 #define XILINX_SPIPS_ERR_DEBUG 0 36 #endif 37 38 #define DB_PRINT_L(level, ...) do { \ 39 if (XILINX_SPIPS_ERR_DEBUG > (level)) { \ 40 fprintf(stderr, ": %s: ", __func__); \ 41 fprintf(stderr, ## __VA_ARGS__); \ 42 } \ 43 } while (0); 44 45 /* config register */ 46 #define R_CONFIG (0x00 / 4) 47 #define IFMODE (1U << 31) 48 #define ENDIAN (1 << 26) 49 #define MODEFAIL_GEN_EN (1 << 17) 50 #define MAN_START_COM (1 << 16) 51 #define MAN_START_EN (1 << 15) 52 #define MANUAL_CS (1 << 14) 53 #define CS (0xF << 10) 54 #define CS_SHIFT (10) 55 #define PERI_SEL (1 << 9) 56 #define REF_CLK (1 << 8) 57 #define FIFO_WIDTH (3 << 6) 58 #define BAUD_RATE_DIV (7 << 3) 59 #define CLK_PH (1 << 2) 60 #define CLK_POL (1 << 1) 61 #define MODE_SEL (1 << 0) 62 #define R_CONFIG_RSVD (0x7bf40000) 63 64 /* interrupt mechanism */ 65 #define R_INTR_STATUS (0x04 / 4) 66 #define R_INTR_EN (0x08 / 4) 67 #define R_INTR_DIS (0x0C / 4) 68 #define R_INTR_MASK (0x10 / 4) 69 #define IXR_TX_FIFO_UNDERFLOW (1 << 6) 70 #define IXR_RX_FIFO_FULL (1 << 5) 71 #define IXR_RX_FIFO_NOT_EMPTY (1 << 4) 72 #define IXR_TX_FIFO_FULL (1 << 3) 73 #define IXR_TX_FIFO_NOT_FULL (1 << 2) 74 #define IXR_TX_FIFO_MODE_FAIL (1 << 1) 75 #define IXR_RX_FIFO_OVERFLOW (1 << 0) 76 #define IXR_ALL ((IXR_TX_FIFO_UNDERFLOW<<1)-1) 77 78 #define R_EN (0x14 / 4) 79 #define R_DELAY (0x18 / 4) 80 #define R_TX_DATA (0x1C / 4) 81 #define R_RX_DATA (0x20 / 4) 82 #define R_SLAVE_IDLE_COUNT (0x24 / 4) 83 #define R_TX_THRES (0x28 / 4) 84 #define R_RX_THRES (0x2C / 4) 85 #define R_TXD1 (0x80 / 4) 86 #define R_TXD2 (0x84 / 4) 87 #define R_TXD3 (0x88 / 4) 88 89 #define R_LQSPI_CFG (0xa0 / 4) 90 #define R_LQSPI_CFG_RESET 0x03A002EB 91 #define LQSPI_CFG_LQ_MODE (1U << 31) 92 #define LQSPI_CFG_TWO_MEM (1 << 30) 93 #define LQSPI_CFG_SEP_BUS (1 << 30) 94 #define LQSPI_CFG_U_PAGE (1 << 28) 95 #define LQSPI_CFG_MODE_EN (1 << 25) 96 #define LQSPI_CFG_MODE_WIDTH 8 97 #define LQSPI_CFG_MODE_SHIFT 16 98 #define LQSPI_CFG_DUMMY_WIDTH 3 99 #define LQSPI_CFG_DUMMY_SHIFT 8 100 #define LQSPI_CFG_INST_CODE 0xFF 101 102 #define R_LQSPI_STS (0xA4 / 4) 103 #define LQSPI_STS_WR_RECVD (1 << 1) 104 105 #define R_MOD_ID (0xFC / 4) 106 107 /* size of TXRX FIFOs */ 108 #define RXFF_A 32 109 #define TXFF_A 32 110 111 #define RXFF_A_Q (64 * 4) 112 #define TXFF_A_Q (64 * 4) 113 114 /* 16MB per linear region */ 115 #define LQSPI_ADDRESS_BITS 24 116 /* Bite off 4k chunks at a time */ 117 #define LQSPI_CACHE_SIZE 1024 118 119 #define SNOOP_CHECKING 0xFF 120 #define SNOOP_NONE 0xFE 121 #define SNOOP_STRIPING 0 122 123 typedef enum { 124 READ = 0x3, 125 FAST_READ = 0xb, 126 DOR = 0x3b, 127 QOR = 0x6b, 128 DIOR = 0xbb, 129 QIOR = 0xeb, 130 131 PP = 0x2, 132 DPP = 0xa2, 133 QPP = 0x32, 134 } FlashCMD; 135 136 typedef struct { 137 XilinxSPIPS parent_obj; 138 139 uint8_t lqspi_buf[LQSPI_CACHE_SIZE]; 140 hwaddr lqspi_cached_addr; 141 } XilinxQSPIPS; 142 143 typedef struct XilinxSPIPSClass { 144 SysBusDeviceClass parent_class; 145 146 const MemoryRegionOps *reg_ops; 147 148 uint32_t rx_fifo_size; 149 uint32_t tx_fifo_size; 150 } XilinxSPIPSClass; 151 152 static inline int num_effective_busses(XilinxSPIPS *s) 153 { 154 return (s->regs[R_LQSPI_CFG] & LQSPI_CFG_SEP_BUS && 155 s->regs[R_LQSPI_CFG] & LQSPI_CFG_TWO_MEM) ? s->num_busses : 1; 156 } 157 158 static inline bool xilinx_spips_cs_is_set(XilinxSPIPS *s, int i, int field) 159 { 160 return ~field & (1 << i) && (s->regs[R_CONFIG] & MANUAL_CS 161 || !fifo8_is_empty(&s->tx_fifo)); 162 } 163 164 static void xilinx_spips_update_cs_lines(XilinxSPIPS *s) 165 { 166 int i, j; 167 bool found = false; 168 int field = s->regs[R_CONFIG] >> CS_SHIFT; 169 170 for (i = 0; i < s->num_cs; i++) { 171 for (j = 0; j < num_effective_busses(s); j++) { 172 int upage = !!(s->regs[R_LQSPI_STS] & LQSPI_CFG_U_PAGE); 173 int cs_to_set = (j * s->num_cs + i + upage) % 174 (s->num_cs * s->num_busses); 175 176 if (xilinx_spips_cs_is_set(s, i, field) && !found) { 177 DB_PRINT_L(0, "selecting slave %d\n", i); 178 qemu_set_irq(s->cs_lines[cs_to_set], 0); 179 } else { 180 DB_PRINT_L(0, "deselecting slave %d\n", i); 181 qemu_set_irq(s->cs_lines[cs_to_set], 1); 182 } 183 } 184 if (xilinx_spips_cs_is_set(s, i, field)) { 185 found = true; 186 } 187 } 188 if (!found) { 189 s->snoop_state = SNOOP_CHECKING; 190 DB_PRINT_L(1, "moving to snoop check state\n"); 191 } 192 } 193 194 static void xilinx_spips_update_ixr(XilinxSPIPS *s) 195 { 196 if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_LQ_MODE) { 197 return; 198 } 199 /* These are set/cleared as they occur */ 200 s->regs[R_INTR_STATUS] &= (IXR_TX_FIFO_UNDERFLOW | IXR_RX_FIFO_OVERFLOW | 201 IXR_TX_FIFO_MODE_FAIL); 202 /* these are pure functions of fifo state, set them here */ 203 s->regs[R_INTR_STATUS] |= 204 (fifo8_is_full(&s->rx_fifo) ? IXR_RX_FIFO_FULL : 0) | 205 (s->rx_fifo.num >= s->regs[R_RX_THRES] ? IXR_RX_FIFO_NOT_EMPTY : 0) | 206 (fifo8_is_full(&s->tx_fifo) ? IXR_TX_FIFO_FULL : 0) | 207 (s->tx_fifo.num < s->regs[R_TX_THRES] ? IXR_TX_FIFO_NOT_FULL : 0); 208 /* drive external interrupt pin */ 209 int new_irqline = !!(s->regs[R_INTR_MASK] & s->regs[R_INTR_STATUS] & 210 IXR_ALL); 211 if (new_irqline != s->irqline) { 212 s->irqline = new_irqline; 213 qemu_set_irq(s->irq, s->irqline); 214 } 215 } 216 217 static void xilinx_spips_reset(DeviceState *d) 218 { 219 XilinxSPIPS *s = XILINX_SPIPS(d); 220 221 int i; 222 for (i = 0; i < XLNX_SPIPS_R_MAX; i++) { 223 s->regs[i] = 0; 224 } 225 226 fifo8_reset(&s->rx_fifo); 227 fifo8_reset(&s->rx_fifo); 228 /* non zero resets */ 229 s->regs[R_CONFIG] |= MODEFAIL_GEN_EN; 230 s->regs[R_SLAVE_IDLE_COUNT] = 0xFF; 231 s->regs[R_TX_THRES] = 1; 232 s->regs[R_RX_THRES] = 1; 233 /* FIXME: move magic number definition somewhere sensible */ 234 s->regs[R_MOD_ID] = 0x01090106; 235 s->regs[R_LQSPI_CFG] = R_LQSPI_CFG_RESET; 236 s->snoop_state = SNOOP_CHECKING; 237 xilinx_spips_update_ixr(s); 238 xilinx_spips_update_cs_lines(s); 239 } 240 241 /* N way (num) in place bit striper. Lay out row wise bits (LSB to MSB) 242 * column wise (from element 0 to N-1). num is the length of x, and dir 243 * reverses the direction of the transform. Best illustrated by example: 244 * Each digit in the below array is a single bit (num == 3): 245 * 246 * {{ 76543210, } ----- stripe (dir == false) -----> {{ FCheb630, } 247 * { hgfedcba, } { GDAfc741, } 248 * { HGFEDCBA, }} <---- upstripe (dir == true) ----- { HEBgda52, }} 249 */ 250 251 static inline void stripe8(uint8_t *x, int num, bool dir) 252 { 253 uint8_t r[num]; 254 memset(r, 0, sizeof(uint8_t) * num); 255 int idx[2] = {0, 0}; 256 int bit[2] = {0, 0}; 257 int d = dir; 258 259 for (idx[0] = 0; idx[0] < num; ++idx[0]) { 260 for (bit[0] = 0; bit[0] < 8; ++bit[0]) { 261 r[idx[d]] |= x[idx[!d]] & 1 << bit[!d] ? 1 << bit[d] : 0; 262 idx[1] = (idx[1] + 1) % num; 263 if (!idx[1]) { 264 bit[1]++; 265 } 266 } 267 } 268 memcpy(x, r, sizeof(uint8_t) * num); 269 } 270 271 static void xilinx_spips_flush_txfifo(XilinxSPIPS *s) 272 { 273 int debug_level = 0; 274 275 for (;;) { 276 int i; 277 uint8_t tx = 0; 278 uint8_t tx_rx[num_effective_busses(s)]; 279 280 if (fifo8_is_empty(&s->tx_fifo)) { 281 if (!(s->regs[R_LQSPI_CFG] & LQSPI_CFG_LQ_MODE)) { 282 s->regs[R_INTR_STATUS] |= IXR_TX_FIFO_UNDERFLOW; 283 } 284 xilinx_spips_update_ixr(s); 285 return; 286 } else if (s->snoop_state == SNOOP_STRIPING) { 287 for (i = 0; i < num_effective_busses(s); ++i) { 288 tx_rx[i] = fifo8_pop(&s->tx_fifo); 289 } 290 stripe8(tx_rx, num_effective_busses(s), false); 291 } else { 292 tx = fifo8_pop(&s->tx_fifo); 293 for (i = 0; i < num_effective_busses(s); ++i) { 294 tx_rx[i] = tx; 295 } 296 } 297 298 for (i = 0; i < num_effective_busses(s); ++i) { 299 DB_PRINT_L(debug_level, "tx = %02x\n", tx_rx[i]); 300 tx_rx[i] = ssi_transfer(s->spi[i], (uint32_t)tx_rx[i]); 301 DB_PRINT_L(debug_level, "rx = %02x\n", tx_rx[i]); 302 } 303 304 if (fifo8_is_full(&s->rx_fifo)) { 305 s->regs[R_INTR_STATUS] |= IXR_RX_FIFO_OVERFLOW; 306 DB_PRINT_L(0, "rx FIFO overflow"); 307 } else if (s->snoop_state == SNOOP_STRIPING) { 308 stripe8(tx_rx, num_effective_busses(s), true); 309 for (i = 0; i < num_effective_busses(s); ++i) { 310 fifo8_push(&s->rx_fifo, (uint8_t)tx_rx[i]); 311 } 312 } else { 313 fifo8_push(&s->rx_fifo, (uint8_t)tx_rx[0]); 314 } 315 316 DB_PRINT_L(debug_level, "initial snoop state: %x\n", 317 (unsigned)s->snoop_state); 318 switch (s->snoop_state) { 319 case (SNOOP_CHECKING): 320 switch (tx) { /* new instruction code */ 321 case READ: /* 3 address bytes, no dummy bytes/cycles */ 322 case PP: 323 case DPP: 324 case QPP: 325 s->snoop_state = 3; 326 break; 327 case FAST_READ: /* 3 address bytes, 1 dummy byte */ 328 case DOR: 329 case QOR: 330 case DIOR: /* FIXME: these vary between vendor - set to spansion */ 331 s->snoop_state = 4; 332 break; 333 case QIOR: /* 3 address bytes, 2 dummy bytes */ 334 s->snoop_state = 6; 335 break; 336 default: 337 s->snoop_state = SNOOP_NONE; 338 } 339 break; 340 case (SNOOP_STRIPING): 341 case (SNOOP_NONE): 342 /* Once we hit the boring stuff - squelch debug noise */ 343 if (!debug_level) { 344 DB_PRINT_L(0, "squelching debug info ....\n"); 345 debug_level = 1; 346 } 347 break; 348 default: 349 s->snoop_state--; 350 } 351 DB_PRINT_L(debug_level, "final snoop state: %x\n", 352 (unsigned)s->snoop_state); 353 } 354 } 355 356 static inline void rx_data_bytes(XilinxSPIPS *s, uint8_t *value, int max) 357 { 358 int i; 359 360 for (i = 0; i < max && !fifo8_is_empty(&s->rx_fifo); ++i) { 361 value[i] = fifo8_pop(&s->rx_fifo); 362 } 363 } 364 365 static uint64_t xilinx_spips_read(void *opaque, hwaddr addr, 366 unsigned size) 367 { 368 XilinxSPIPS *s = opaque; 369 uint32_t mask = ~0; 370 uint32_t ret; 371 uint8_t rx_buf[4]; 372 373 addr >>= 2; 374 switch (addr) { 375 case R_CONFIG: 376 mask = ~(R_CONFIG_RSVD | MAN_START_COM); 377 break; 378 case R_INTR_STATUS: 379 ret = s->regs[addr] & IXR_ALL; 380 s->regs[addr] = 0; 381 DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret); 382 return ret; 383 case R_INTR_MASK: 384 mask = IXR_ALL; 385 break; 386 case R_EN: 387 mask = 0x1; 388 break; 389 case R_SLAVE_IDLE_COUNT: 390 mask = 0xFF; 391 break; 392 case R_MOD_ID: 393 mask = 0x01FFFFFF; 394 break; 395 case R_INTR_EN: 396 case R_INTR_DIS: 397 case R_TX_DATA: 398 mask = 0; 399 break; 400 case R_RX_DATA: 401 memset(rx_buf, 0, sizeof(rx_buf)); 402 rx_data_bytes(s, rx_buf, s->num_txrx_bytes); 403 ret = s->regs[R_CONFIG] & ENDIAN ? cpu_to_be32(*(uint32_t *)rx_buf) 404 : cpu_to_le32(*(uint32_t *)rx_buf); 405 DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret); 406 xilinx_spips_update_ixr(s); 407 return ret; 408 } 409 DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4, 410 s->regs[addr] & mask); 411 return s->regs[addr] & mask; 412 413 } 414 415 static inline void tx_data_bytes(XilinxSPIPS *s, uint32_t value, int num) 416 { 417 int i; 418 for (i = 0; i < num && !fifo8_is_full(&s->tx_fifo); ++i) { 419 if (s->regs[R_CONFIG] & ENDIAN) { 420 fifo8_push(&s->tx_fifo, (uint8_t)(value >> 24)); 421 value <<= 8; 422 } else { 423 fifo8_push(&s->tx_fifo, (uint8_t)value); 424 value >>= 8; 425 } 426 } 427 } 428 429 static void xilinx_spips_write(void *opaque, hwaddr addr, 430 uint64_t value, unsigned size) 431 { 432 int mask = ~0; 433 int man_start_com = 0; 434 XilinxSPIPS *s = opaque; 435 436 DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr, (unsigned)value); 437 addr >>= 2; 438 switch (addr) { 439 case R_CONFIG: 440 mask = ~(R_CONFIG_RSVD | MAN_START_COM); 441 if (value & MAN_START_COM) { 442 man_start_com = 1; 443 } 444 break; 445 case R_INTR_STATUS: 446 mask = IXR_ALL; 447 s->regs[R_INTR_STATUS] &= ~(mask & value); 448 goto no_reg_update; 449 case R_INTR_DIS: 450 mask = IXR_ALL; 451 s->regs[R_INTR_MASK] &= ~(mask & value); 452 goto no_reg_update; 453 case R_INTR_EN: 454 mask = IXR_ALL; 455 s->regs[R_INTR_MASK] |= mask & value; 456 goto no_reg_update; 457 case R_EN: 458 mask = 0x1; 459 break; 460 case R_SLAVE_IDLE_COUNT: 461 mask = 0xFF; 462 break; 463 case R_RX_DATA: 464 case R_INTR_MASK: 465 case R_MOD_ID: 466 mask = 0; 467 break; 468 case R_TX_DATA: 469 tx_data_bytes(s, (uint32_t)value, s->num_txrx_bytes); 470 goto no_reg_update; 471 case R_TXD1: 472 tx_data_bytes(s, (uint32_t)value, 1); 473 goto no_reg_update; 474 case R_TXD2: 475 tx_data_bytes(s, (uint32_t)value, 2); 476 goto no_reg_update; 477 case R_TXD3: 478 tx_data_bytes(s, (uint32_t)value, 3); 479 goto no_reg_update; 480 } 481 s->regs[addr] = (s->regs[addr] & ~mask) | (value & mask); 482 no_reg_update: 483 xilinx_spips_update_cs_lines(s); 484 if ((man_start_com && s->regs[R_CONFIG] & MAN_START_EN) || 485 (fifo8_is_empty(&s->tx_fifo) && s->regs[R_CONFIG] & MAN_START_EN)) { 486 xilinx_spips_flush_txfifo(s); 487 } 488 xilinx_spips_update_cs_lines(s); 489 xilinx_spips_update_ixr(s); 490 } 491 492 static const MemoryRegionOps spips_ops = { 493 .read = xilinx_spips_read, 494 .write = xilinx_spips_write, 495 .endianness = DEVICE_LITTLE_ENDIAN, 496 }; 497 498 static void xilinx_qspips_write(void *opaque, hwaddr addr, 499 uint64_t value, unsigned size) 500 { 501 XilinxQSPIPS *q = XILINX_QSPIPS(opaque); 502 503 xilinx_spips_write(opaque, addr, value, size); 504 addr >>= 2; 505 506 if (addr == R_LQSPI_CFG) { 507 q->lqspi_cached_addr = ~0ULL; 508 } 509 } 510 511 static const MemoryRegionOps qspips_ops = { 512 .read = xilinx_spips_read, 513 .write = xilinx_qspips_write, 514 .endianness = DEVICE_LITTLE_ENDIAN, 515 }; 516 517 #define LQSPI_CACHE_SIZE 1024 518 519 static uint64_t 520 lqspi_read(void *opaque, hwaddr addr, unsigned int size) 521 { 522 int i; 523 XilinxQSPIPS *q = opaque; 524 XilinxSPIPS *s = opaque; 525 uint32_t ret; 526 527 if (addr >= q->lqspi_cached_addr && 528 addr <= q->lqspi_cached_addr + LQSPI_CACHE_SIZE - 4) { 529 uint8_t *retp = &q->lqspi_buf[addr - q->lqspi_cached_addr]; 530 ret = cpu_to_le32(*(uint32_t *)retp); 531 DB_PRINT_L(1, "addr: %08x, data: %08x\n", (unsigned)addr, 532 (unsigned)ret); 533 return ret; 534 } else { 535 int flash_addr = (addr / num_effective_busses(s)); 536 int slave = flash_addr >> LQSPI_ADDRESS_BITS; 537 int cache_entry = 0; 538 uint32_t u_page_save = s->regs[R_LQSPI_STS] & ~LQSPI_CFG_U_PAGE; 539 540 s->regs[R_LQSPI_STS] &= ~LQSPI_CFG_U_PAGE; 541 s->regs[R_LQSPI_STS] |= slave ? LQSPI_CFG_U_PAGE : 0; 542 543 DB_PRINT_L(0, "config reg status: %08x\n", s->regs[R_LQSPI_CFG]); 544 545 fifo8_reset(&s->tx_fifo); 546 fifo8_reset(&s->rx_fifo); 547 548 /* instruction */ 549 DB_PRINT_L(0, "pushing read instruction: %02x\n", 550 (unsigned)(uint8_t)(s->regs[R_LQSPI_CFG] & 551 LQSPI_CFG_INST_CODE)); 552 fifo8_push(&s->tx_fifo, s->regs[R_LQSPI_CFG] & LQSPI_CFG_INST_CODE); 553 /* read address */ 554 DB_PRINT_L(0, "pushing read address %06x\n", flash_addr); 555 fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 16)); 556 fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 8)); 557 fifo8_push(&s->tx_fifo, (uint8_t)flash_addr); 558 /* mode bits */ 559 if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_MODE_EN) { 560 fifo8_push(&s->tx_fifo, extract32(s->regs[R_LQSPI_CFG], 561 LQSPI_CFG_MODE_SHIFT, 562 LQSPI_CFG_MODE_WIDTH)); 563 } 564 /* dummy bytes */ 565 for (i = 0; i < (extract32(s->regs[R_LQSPI_CFG], LQSPI_CFG_DUMMY_SHIFT, 566 LQSPI_CFG_DUMMY_WIDTH)); ++i) { 567 DB_PRINT_L(0, "pushing dummy byte\n"); 568 fifo8_push(&s->tx_fifo, 0); 569 } 570 xilinx_spips_update_cs_lines(s); 571 xilinx_spips_flush_txfifo(s); 572 fifo8_reset(&s->rx_fifo); 573 574 DB_PRINT_L(0, "starting QSPI data read\n"); 575 576 while (cache_entry < LQSPI_CACHE_SIZE) { 577 for (i = 0; i < 64; ++i) { 578 tx_data_bytes(s, 0, 1); 579 } 580 xilinx_spips_flush_txfifo(s); 581 for (i = 0; i < 64; ++i) { 582 rx_data_bytes(s, &q->lqspi_buf[cache_entry++], 1); 583 } 584 } 585 586 s->regs[R_LQSPI_STS] &= ~LQSPI_CFG_U_PAGE; 587 s->regs[R_LQSPI_STS] |= u_page_save; 588 xilinx_spips_update_cs_lines(s); 589 590 q->lqspi_cached_addr = flash_addr * num_effective_busses(s); 591 return lqspi_read(opaque, addr, size); 592 } 593 } 594 595 static const MemoryRegionOps lqspi_ops = { 596 .read = lqspi_read, 597 .endianness = DEVICE_NATIVE_ENDIAN, 598 .valid = { 599 .min_access_size = 1, 600 .max_access_size = 4 601 } 602 }; 603 604 static void xilinx_spips_realize(DeviceState *dev, Error **errp) 605 { 606 XilinxSPIPS *s = XILINX_SPIPS(dev); 607 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 608 XilinxSPIPSClass *xsc = XILINX_SPIPS_GET_CLASS(s); 609 int i; 610 611 DB_PRINT_L(0, "realized spips\n"); 612 613 s->spi = g_new(SSIBus *, s->num_busses); 614 for (i = 0; i < s->num_busses; ++i) { 615 char bus_name[16]; 616 snprintf(bus_name, 16, "spi%d", i); 617 s->spi[i] = ssi_create_bus(dev, bus_name); 618 } 619 620 s->cs_lines = g_new0(qemu_irq, s->num_cs * s->num_busses); 621 ssi_auto_connect_slaves(DEVICE(s), s->cs_lines, s->spi[0]); 622 ssi_auto_connect_slaves(DEVICE(s), s->cs_lines, s->spi[1]); 623 sysbus_init_irq(sbd, &s->irq); 624 for (i = 0; i < s->num_cs * s->num_busses; ++i) { 625 sysbus_init_irq(sbd, &s->cs_lines[i]); 626 } 627 628 memory_region_init_io(&s->iomem, OBJECT(s), xsc->reg_ops, s, 629 "spi", XLNX_SPIPS_R_MAX * 4); 630 sysbus_init_mmio(sbd, &s->iomem); 631 632 s->irqline = -1; 633 634 fifo8_create(&s->rx_fifo, xsc->rx_fifo_size); 635 fifo8_create(&s->tx_fifo, xsc->tx_fifo_size); 636 } 637 638 static void xilinx_qspips_realize(DeviceState *dev, Error **errp) 639 { 640 XilinxSPIPS *s = XILINX_SPIPS(dev); 641 XilinxQSPIPS *q = XILINX_QSPIPS(dev); 642 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 643 644 DB_PRINT_L(0, "realized qspips\n"); 645 646 s->num_busses = 2; 647 s->num_cs = 2; 648 s->num_txrx_bytes = 4; 649 650 xilinx_spips_realize(dev, errp); 651 memory_region_init_io(&s->mmlqspi, OBJECT(s), &lqspi_ops, s, "lqspi", 652 (1 << LQSPI_ADDRESS_BITS) * 2); 653 sysbus_init_mmio(sbd, &s->mmlqspi); 654 655 q->lqspi_cached_addr = ~0ULL; 656 } 657 658 static int xilinx_spips_post_load(void *opaque, int version_id) 659 { 660 xilinx_spips_update_ixr((XilinxSPIPS *)opaque); 661 xilinx_spips_update_cs_lines((XilinxSPIPS *)opaque); 662 return 0; 663 } 664 665 static const VMStateDescription vmstate_xilinx_spips = { 666 .name = "xilinx_spips", 667 .version_id = 2, 668 .minimum_version_id = 2, 669 .post_load = xilinx_spips_post_load, 670 .fields = (VMStateField[]) { 671 VMSTATE_FIFO8(tx_fifo, XilinxSPIPS), 672 VMSTATE_FIFO8(rx_fifo, XilinxSPIPS), 673 VMSTATE_UINT32_ARRAY(regs, XilinxSPIPS, XLNX_SPIPS_R_MAX), 674 VMSTATE_UINT8(snoop_state, XilinxSPIPS), 675 VMSTATE_END_OF_LIST() 676 } 677 }; 678 679 static Property xilinx_spips_properties[] = { 680 DEFINE_PROP_UINT8("num-busses", XilinxSPIPS, num_busses, 1), 681 DEFINE_PROP_UINT8("num-ss-bits", XilinxSPIPS, num_cs, 4), 682 DEFINE_PROP_UINT8("num-txrx-bytes", XilinxSPIPS, num_txrx_bytes, 1), 683 DEFINE_PROP_END_OF_LIST(), 684 }; 685 686 static void xilinx_qspips_class_init(ObjectClass *klass, void * data) 687 { 688 DeviceClass *dc = DEVICE_CLASS(klass); 689 XilinxSPIPSClass *xsc = XILINX_SPIPS_CLASS(klass); 690 691 dc->realize = xilinx_qspips_realize; 692 xsc->reg_ops = &qspips_ops; 693 xsc->rx_fifo_size = RXFF_A_Q; 694 xsc->tx_fifo_size = TXFF_A_Q; 695 } 696 697 static void xilinx_spips_class_init(ObjectClass *klass, void *data) 698 { 699 DeviceClass *dc = DEVICE_CLASS(klass); 700 XilinxSPIPSClass *xsc = XILINX_SPIPS_CLASS(klass); 701 702 dc->realize = xilinx_spips_realize; 703 dc->reset = xilinx_spips_reset; 704 dc->props = xilinx_spips_properties; 705 dc->vmsd = &vmstate_xilinx_spips; 706 707 xsc->reg_ops = &spips_ops; 708 xsc->rx_fifo_size = RXFF_A; 709 xsc->tx_fifo_size = TXFF_A; 710 } 711 712 static const TypeInfo xilinx_spips_info = { 713 .name = TYPE_XILINX_SPIPS, 714 .parent = TYPE_SYS_BUS_DEVICE, 715 .instance_size = sizeof(XilinxSPIPS), 716 .class_init = xilinx_spips_class_init, 717 .class_size = sizeof(XilinxSPIPSClass), 718 }; 719 720 static const TypeInfo xilinx_qspips_info = { 721 .name = TYPE_XILINX_QSPIPS, 722 .parent = TYPE_XILINX_SPIPS, 723 .instance_size = sizeof(XilinxQSPIPS), 724 .class_init = xilinx_qspips_class_init, 725 }; 726 727 static void xilinx_spips_register_types(void) 728 { 729 type_register_static(&xilinx_spips_info); 730 type_register_static(&xilinx_qspips_info); 731 } 732 733 type_init(xilinx_spips_register_types) 734