1 /* 2 * QEMU model of the Xilinx Zynq SPI controller 3 * 4 * Copyright (c) 2012 Peter A. G. Crosthwaite 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "hw/sysbus.h" 27 #include "sysemu/sysemu.h" 28 #include "hw/ptimer.h" 29 #include "qemu/log.h" 30 #include "qemu/bitops.h" 31 #include "hw/ssi/xilinx_spips.h" 32 #include "qapi/error.h" 33 #include "hw/register.h" 34 #include "sysemu/dma.h" 35 #include "migration/blocker.h" 36 37 #ifndef XILINX_SPIPS_ERR_DEBUG 38 #define XILINX_SPIPS_ERR_DEBUG 0 39 #endif 40 41 #define DB_PRINT_L(level, ...) do { \ 42 if (XILINX_SPIPS_ERR_DEBUG > (level)) { \ 43 fprintf(stderr, ": %s: ", __func__); \ 44 fprintf(stderr, ## __VA_ARGS__); \ 45 } \ 46 } while (0) 47 48 /* config register */ 49 #define R_CONFIG (0x00 / 4) 50 #define IFMODE (1U << 31) 51 #define R_CONFIG_ENDIAN (1 << 26) 52 #define MODEFAIL_GEN_EN (1 << 17) 53 #define MAN_START_COM (1 << 16) 54 #define MAN_START_EN (1 << 15) 55 #define MANUAL_CS (1 << 14) 56 #define CS (0xF << 10) 57 #define CS_SHIFT (10) 58 #define PERI_SEL (1 << 9) 59 #define REF_CLK (1 << 8) 60 #define FIFO_WIDTH (3 << 6) 61 #define BAUD_RATE_DIV (7 << 3) 62 #define CLK_PH (1 << 2) 63 #define CLK_POL (1 << 1) 64 #define MODE_SEL (1 << 0) 65 #define R_CONFIG_RSVD (0x7bf40000) 66 67 /* interrupt mechanism */ 68 #define R_INTR_STATUS (0x04 / 4) 69 #define R_INTR_STATUS_RESET (0x104) 70 #define R_INTR_EN (0x08 / 4) 71 #define R_INTR_DIS (0x0C / 4) 72 #define R_INTR_MASK (0x10 / 4) 73 #define IXR_TX_FIFO_UNDERFLOW (1 << 6) 74 /* Poll timeout not implemented */ 75 #define IXR_RX_FIFO_EMPTY (1 << 11) 76 #define IXR_GENERIC_FIFO_FULL (1 << 10) 77 #define IXR_GENERIC_FIFO_NOT_FULL (1 << 9) 78 #define IXR_TX_FIFO_EMPTY (1 << 8) 79 #define IXR_GENERIC_FIFO_EMPTY (1 << 7) 80 #define IXR_RX_FIFO_FULL (1 << 5) 81 #define IXR_RX_FIFO_NOT_EMPTY (1 << 4) 82 #define IXR_TX_FIFO_FULL (1 << 3) 83 #define IXR_TX_FIFO_NOT_FULL (1 << 2) 84 #define IXR_TX_FIFO_MODE_FAIL (1 << 1) 85 #define IXR_RX_FIFO_OVERFLOW (1 << 0) 86 #define IXR_ALL ((1 << 13) - 1) 87 #define GQSPI_IXR_MASK 0xFBE 88 #define IXR_SELF_CLEAR \ 89 (IXR_GENERIC_FIFO_EMPTY \ 90 | IXR_GENERIC_FIFO_FULL \ 91 | IXR_GENERIC_FIFO_NOT_FULL \ 92 | IXR_TX_FIFO_EMPTY \ 93 | IXR_TX_FIFO_FULL \ 94 | IXR_TX_FIFO_NOT_FULL \ 95 | IXR_RX_FIFO_EMPTY \ 96 | IXR_RX_FIFO_FULL \ 97 | IXR_RX_FIFO_NOT_EMPTY) 98 99 #define R_EN (0x14 / 4) 100 #define R_DELAY (0x18 / 4) 101 #define R_TX_DATA (0x1C / 4) 102 #define R_RX_DATA (0x20 / 4) 103 #define R_SLAVE_IDLE_COUNT (0x24 / 4) 104 #define R_TX_THRES (0x28 / 4) 105 #define R_RX_THRES (0x2C / 4) 106 #define R_GPIO (0x30 / 4) 107 #define R_LPBK_DLY_ADJ (0x38 / 4) 108 #define R_LPBK_DLY_ADJ_RESET (0x33) 109 #define R_TXD1 (0x80 / 4) 110 #define R_TXD2 (0x84 / 4) 111 #define R_TXD3 (0x88 / 4) 112 113 #define R_LQSPI_CFG (0xa0 / 4) 114 #define R_LQSPI_CFG_RESET 0x03A002EB 115 #define LQSPI_CFG_LQ_MODE (1U << 31) 116 #define LQSPI_CFG_TWO_MEM (1 << 30) 117 #define LQSPI_CFG_SEP_BUS (1 << 29) 118 #define LQSPI_CFG_U_PAGE (1 << 28) 119 #define LQSPI_CFG_ADDR4 (1 << 27) 120 #define LQSPI_CFG_MODE_EN (1 << 25) 121 #define LQSPI_CFG_MODE_WIDTH 8 122 #define LQSPI_CFG_MODE_SHIFT 16 123 #define LQSPI_CFG_DUMMY_WIDTH 3 124 #define LQSPI_CFG_DUMMY_SHIFT 8 125 #define LQSPI_CFG_INST_CODE 0xFF 126 127 #define R_CMND (0xc0 / 4) 128 #define R_CMND_RXFIFO_DRAIN (1 << 19) 129 FIELD(CMND, PARTIAL_BYTE_LEN, 16, 3) 130 #define R_CMND_EXT_ADD (1 << 15) 131 FIELD(CMND, RX_DISCARD, 8, 7) 132 FIELD(CMND, DUMMY_CYCLES, 2, 6) 133 #define R_CMND_DMA_EN (1 << 1) 134 #define R_CMND_PUSH_WAIT (1 << 0) 135 #define R_TRANSFER_SIZE (0xc4 / 4) 136 #define R_LQSPI_STS (0xA4 / 4) 137 #define LQSPI_STS_WR_RECVD (1 << 1) 138 139 #define R_MOD_ID (0xFC / 4) 140 141 #define R_GQSPI_SELECT (0x144 / 4) 142 FIELD(GQSPI_SELECT, GENERIC_QSPI_EN, 0, 1) 143 #define R_GQSPI_ISR (0x104 / 4) 144 #define R_GQSPI_IER (0x108 / 4) 145 #define R_GQSPI_IDR (0x10c / 4) 146 #define R_GQSPI_IMR (0x110 / 4) 147 #define R_GQSPI_IMR_RESET (0xfbe) 148 #define R_GQSPI_TX_THRESH (0x128 / 4) 149 #define R_GQSPI_RX_THRESH (0x12c / 4) 150 #define R_GQSPI_GPIO (0x130 / 4) 151 #define R_GQSPI_LPBK_DLY_ADJ (0x138 / 4) 152 #define R_GQSPI_LPBK_DLY_ADJ_RESET (0x33) 153 #define R_GQSPI_CNFG (0x100 / 4) 154 FIELD(GQSPI_CNFG, MODE_EN, 30, 2) 155 FIELD(GQSPI_CNFG, GEN_FIFO_START_MODE, 29, 1) 156 FIELD(GQSPI_CNFG, GEN_FIFO_START, 28, 1) 157 FIELD(GQSPI_CNFG, ENDIAN, 26, 1) 158 /* Poll timeout not implemented */ 159 FIELD(GQSPI_CNFG, EN_POLL_TIMEOUT, 20, 1) 160 /* QEMU doesnt care about any of these last three */ 161 FIELD(GQSPI_CNFG, BR, 3, 3) 162 FIELD(GQSPI_CNFG, CPH, 2, 1) 163 FIELD(GQSPI_CNFG, CPL, 1, 1) 164 #define R_GQSPI_GEN_FIFO (0x140 / 4) 165 #define R_GQSPI_TXD (0x11c / 4) 166 #define R_GQSPI_RXD (0x120 / 4) 167 #define R_GQSPI_FIFO_CTRL (0x14c / 4) 168 FIELD(GQSPI_FIFO_CTRL, RX_FIFO_RESET, 2, 1) 169 FIELD(GQSPI_FIFO_CTRL, TX_FIFO_RESET, 1, 1) 170 FIELD(GQSPI_FIFO_CTRL, GENERIC_FIFO_RESET, 0, 1) 171 #define R_GQSPI_GFIFO_THRESH (0x150 / 4) 172 #define R_GQSPI_DATA_STS (0x15c / 4) 173 /* We use the snapshot register to hold the core state for the currently 174 * or most recently executed command. So the generic fifo format is defined 175 * for the snapshot register 176 */ 177 #define R_GQSPI_GF_SNAPSHOT (0x160 / 4) 178 FIELD(GQSPI_GF_SNAPSHOT, POLL, 19, 1) 179 FIELD(GQSPI_GF_SNAPSHOT, STRIPE, 18, 1) 180 FIELD(GQSPI_GF_SNAPSHOT, RECIEVE, 17, 1) 181 FIELD(GQSPI_GF_SNAPSHOT, TRANSMIT, 16, 1) 182 FIELD(GQSPI_GF_SNAPSHOT, DATA_BUS_SELECT, 14, 2) 183 FIELD(GQSPI_GF_SNAPSHOT, CHIP_SELECT, 12, 2) 184 FIELD(GQSPI_GF_SNAPSHOT, SPI_MODE, 10, 2) 185 FIELD(GQSPI_GF_SNAPSHOT, EXPONENT, 9, 1) 186 FIELD(GQSPI_GF_SNAPSHOT, DATA_XFER, 8, 1) 187 FIELD(GQSPI_GF_SNAPSHOT, IMMEDIATE_DATA, 0, 8) 188 #define R_GQSPI_MOD_ID (0x1fc / 4) 189 #define R_GQSPI_MOD_ID_RESET (0x10a0000) 190 191 #define R_QSPIDMA_DST_CTRL (0x80c / 4) 192 #define R_QSPIDMA_DST_CTRL_RESET (0x803ffa00) 193 #define R_QSPIDMA_DST_I_MASK (0x820 / 4) 194 #define R_QSPIDMA_DST_I_MASK_RESET (0xfe) 195 #define R_QSPIDMA_DST_CTRL2 (0x824 / 4) 196 #define R_QSPIDMA_DST_CTRL2_RESET (0x081bfff8) 197 198 /* size of TXRX FIFOs */ 199 #define RXFF_A (128) 200 #define TXFF_A (128) 201 202 #define RXFF_A_Q (64 * 4) 203 #define TXFF_A_Q (64 * 4) 204 205 /* 16MB per linear region */ 206 #define LQSPI_ADDRESS_BITS 24 207 208 #define SNOOP_CHECKING 0xFF 209 #define SNOOP_ADDR 0xF0 210 #define SNOOP_NONE 0xEE 211 #define SNOOP_STRIPING 0 212 213 #define MIN_NUM_BUSSES 1 214 #define MAX_NUM_BUSSES 2 215 216 static inline int num_effective_busses(XilinxSPIPS *s) 217 { 218 return (s->regs[R_LQSPI_CFG] & LQSPI_CFG_SEP_BUS && 219 s->regs[R_LQSPI_CFG] & LQSPI_CFG_TWO_MEM) ? s->num_busses : 1; 220 } 221 222 static void xilinx_spips_update_cs(XilinxSPIPS *s, int field) 223 { 224 int i; 225 226 for (i = 0; i < s->num_cs * s->num_busses; i++) { 227 bool old_state = s->cs_lines_state[i]; 228 bool new_state = field & (1 << i); 229 230 if (old_state != new_state) { 231 s->cs_lines_state[i] = new_state; 232 s->rx_discard = ARRAY_FIELD_EX32(s->regs, CMND, RX_DISCARD); 233 DB_PRINT_L(1, "%sselecting slave %d\n", new_state ? "" : "de", i); 234 } 235 qemu_set_irq(s->cs_lines[i], !new_state); 236 } 237 if (!(field & ((1 << (s->num_cs * s->num_busses)) - 1))) { 238 s->snoop_state = SNOOP_CHECKING; 239 s->cmd_dummies = 0; 240 s->link_state = 1; 241 s->link_state_next = 1; 242 s->link_state_next_when = 0; 243 DB_PRINT_L(1, "moving to snoop check state\n"); 244 } 245 } 246 247 static void xlnx_zynqmp_qspips_update_cs_lines(XlnxZynqMPQSPIPS *s) 248 { 249 if (s->regs[R_GQSPI_GF_SNAPSHOT]) { 250 int field = ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, CHIP_SELECT); 251 bool upper_cs_sel = field & (1 << 1); 252 bool lower_cs_sel = field & 1; 253 bool bus0_enabled; 254 bool bus1_enabled; 255 uint8_t buses; 256 int cs = 0; 257 258 buses = ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, DATA_BUS_SELECT); 259 bus0_enabled = buses & 1; 260 bus1_enabled = buses & (1 << 1); 261 262 if (bus0_enabled && bus1_enabled) { 263 if (lower_cs_sel) { 264 cs |= 1; 265 } 266 if (upper_cs_sel) { 267 cs |= 1 << 3; 268 } 269 } else if (bus0_enabled) { 270 if (lower_cs_sel) { 271 cs |= 1; 272 } 273 if (upper_cs_sel) { 274 cs |= 1 << 1; 275 } 276 } else if (bus1_enabled) { 277 if (lower_cs_sel) { 278 cs |= 1 << 2; 279 } 280 if (upper_cs_sel) { 281 cs |= 1 << 3; 282 } 283 } 284 xilinx_spips_update_cs(XILINX_SPIPS(s), cs); 285 } 286 } 287 288 static void xilinx_spips_update_cs_lines(XilinxSPIPS *s) 289 { 290 int field = ~((s->regs[R_CONFIG] & CS) >> CS_SHIFT); 291 292 /* In dual parallel, mirror low CS to both */ 293 if (num_effective_busses(s) == 2) { 294 /* Single bit chip-select for qspi */ 295 field &= 0x1; 296 field |= field << 3; 297 /* Dual stack U-Page */ 298 } else if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_TWO_MEM && 299 s->regs[R_LQSPI_STS] & LQSPI_CFG_U_PAGE) { 300 /* Single bit chip-select for qspi */ 301 field &= 0x1; 302 /* change from CS0 to CS1 */ 303 field <<= 1; 304 } 305 /* Auto CS */ 306 if (!(s->regs[R_CONFIG] & MANUAL_CS) && 307 fifo8_is_empty(&s->tx_fifo)) { 308 field = 0; 309 } 310 xilinx_spips_update_cs(s, field); 311 } 312 313 static void xilinx_spips_update_ixr(XilinxSPIPS *s) 314 { 315 if (!(s->regs[R_LQSPI_CFG] & LQSPI_CFG_LQ_MODE)) { 316 s->regs[R_INTR_STATUS] &= ~IXR_SELF_CLEAR; 317 s->regs[R_INTR_STATUS] |= 318 (fifo8_is_full(&s->rx_fifo) ? IXR_RX_FIFO_FULL : 0) | 319 (s->rx_fifo.num >= s->regs[R_RX_THRES] ? 320 IXR_RX_FIFO_NOT_EMPTY : 0) | 321 (fifo8_is_full(&s->tx_fifo) ? IXR_TX_FIFO_FULL : 0) | 322 (fifo8_is_empty(&s->tx_fifo) ? IXR_TX_FIFO_EMPTY : 0) | 323 (s->tx_fifo.num < s->regs[R_TX_THRES] ? IXR_TX_FIFO_NOT_FULL : 0); 324 } 325 int new_irqline = !!(s->regs[R_INTR_MASK] & s->regs[R_INTR_STATUS] & 326 IXR_ALL); 327 if (new_irqline != s->irqline) { 328 s->irqline = new_irqline; 329 qemu_set_irq(s->irq, s->irqline); 330 } 331 } 332 333 static void xlnx_zynqmp_qspips_update_ixr(XlnxZynqMPQSPIPS *s) 334 { 335 uint32_t gqspi_int; 336 int new_irqline; 337 338 s->regs[R_GQSPI_ISR] &= ~IXR_SELF_CLEAR; 339 s->regs[R_GQSPI_ISR] |= 340 (fifo32_is_empty(&s->fifo_g) ? IXR_GENERIC_FIFO_EMPTY : 0) | 341 (fifo32_is_full(&s->fifo_g) ? IXR_GENERIC_FIFO_FULL : 0) | 342 (s->fifo_g.fifo.num < s->regs[R_GQSPI_GFIFO_THRESH] ? 343 IXR_GENERIC_FIFO_NOT_FULL : 0) | 344 (fifo8_is_empty(&s->rx_fifo_g) ? IXR_RX_FIFO_EMPTY : 0) | 345 (fifo8_is_full(&s->rx_fifo_g) ? IXR_RX_FIFO_FULL : 0) | 346 (s->rx_fifo_g.num >= s->regs[R_GQSPI_RX_THRESH] ? 347 IXR_RX_FIFO_NOT_EMPTY : 0) | 348 (fifo8_is_empty(&s->tx_fifo_g) ? IXR_TX_FIFO_EMPTY : 0) | 349 (fifo8_is_full(&s->tx_fifo_g) ? IXR_TX_FIFO_FULL : 0) | 350 (s->tx_fifo_g.num < s->regs[R_GQSPI_TX_THRESH] ? 351 IXR_TX_FIFO_NOT_FULL : 0); 352 353 /* GQSPI Interrupt Trigger Status */ 354 gqspi_int = (~s->regs[R_GQSPI_IMR]) & s->regs[R_GQSPI_ISR] & GQSPI_IXR_MASK; 355 new_irqline = !!(gqspi_int & IXR_ALL); 356 357 /* drive external interrupt pin */ 358 if (new_irqline != s->gqspi_irqline) { 359 s->gqspi_irqline = new_irqline; 360 qemu_set_irq(XILINX_SPIPS(s)->irq, s->gqspi_irqline); 361 } 362 } 363 364 static void xilinx_spips_reset(DeviceState *d) 365 { 366 XilinxSPIPS *s = XILINX_SPIPS(d); 367 368 memset(s->regs, 0, sizeof(s->regs)); 369 370 fifo8_reset(&s->rx_fifo); 371 fifo8_reset(&s->rx_fifo); 372 /* non zero resets */ 373 s->regs[R_CONFIG] |= MODEFAIL_GEN_EN; 374 s->regs[R_SLAVE_IDLE_COUNT] = 0xFF; 375 s->regs[R_TX_THRES] = 1; 376 s->regs[R_RX_THRES] = 1; 377 /* FIXME: move magic number definition somewhere sensible */ 378 s->regs[R_MOD_ID] = 0x01090106; 379 s->regs[R_LQSPI_CFG] = R_LQSPI_CFG_RESET; 380 s->link_state = 1; 381 s->link_state_next = 1; 382 s->link_state_next_when = 0; 383 s->snoop_state = SNOOP_CHECKING; 384 s->cmd_dummies = 0; 385 s->man_start_com = false; 386 xilinx_spips_update_ixr(s); 387 xilinx_spips_update_cs_lines(s); 388 } 389 390 static void xlnx_zynqmp_qspips_reset(DeviceState *d) 391 { 392 XlnxZynqMPQSPIPS *s = XLNX_ZYNQMP_QSPIPS(d); 393 394 xilinx_spips_reset(d); 395 396 memset(s->regs, 0, sizeof(s->regs)); 397 398 fifo8_reset(&s->rx_fifo_g); 399 fifo8_reset(&s->rx_fifo_g); 400 fifo32_reset(&s->fifo_g); 401 s->regs[R_INTR_STATUS] = R_INTR_STATUS_RESET; 402 s->regs[R_GPIO] = 1; 403 s->regs[R_LPBK_DLY_ADJ] = R_LPBK_DLY_ADJ_RESET; 404 s->regs[R_GQSPI_GFIFO_THRESH] = 0x10; 405 s->regs[R_MOD_ID] = 0x01090101; 406 s->regs[R_GQSPI_IMR] = R_GQSPI_IMR_RESET; 407 s->regs[R_GQSPI_TX_THRESH] = 1; 408 s->regs[R_GQSPI_RX_THRESH] = 1; 409 s->regs[R_GQSPI_GPIO] = 1; 410 s->regs[R_GQSPI_LPBK_DLY_ADJ] = R_GQSPI_LPBK_DLY_ADJ_RESET; 411 s->regs[R_GQSPI_MOD_ID] = R_GQSPI_MOD_ID_RESET; 412 s->regs[R_QSPIDMA_DST_CTRL] = R_QSPIDMA_DST_CTRL_RESET; 413 s->regs[R_QSPIDMA_DST_I_MASK] = R_QSPIDMA_DST_I_MASK_RESET; 414 s->regs[R_QSPIDMA_DST_CTRL2] = R_QSPIDMA_DST_CTRL2_RESET; 415 s->man_start_com_g = false; 416 s->gqspi_irqline = 0; 417 xlnx_zynqmp_qspips_update_ixr(s); 418 } 419 420 /* N way (num) in place bit striper. Lay out row wise bits (MSB to LSB) 421 * column wise (from element 0 to N-1). num is the length of x, and dir 422 * reverses the direction of the transform. Best illustrated by example: 423 * Each digit in the below array is a single bit (num == 3): 424 * 425 * {{ 76543210, } ----- stripe (dir == false) -----> {{ 741gdaFC, } 426 * { hgfedcba, } { 630fcHEB, } 427 * { HGFEDCBA, }} <---- upstripe (dir == true) ----- { 52hebGDA, }} 428 */ 429 430 static inline void stripe8(uint8_t *x, int num, bool dir) 431 { 432 uint8_t r[MAX_NUM_BUSSES]; 433 int idx[2] = {0, 0}; 434 int bit[2] = {0, 7}; 435 int d = dir; 436 437 assert(num <= MAX_NUM_BUSSES); 438 memset(r, 0, sizeof(uint8_t) * num); 439 440 for (idx[0] = 0; idx[0] < num; ++idx[0]) { 441 for (bit[0] = 7; bit[0] >= 0; bit[0]--) { 442 r[idx[!d]] |= x[idx[d]] & 1 << bit[d] ? 1 << bit[!d] : 0; 443 idx[1] = (idx[1] + 1) % num; 444 if (!idx[1]) { 445 bit[1]--; 446 } 447 } 448 } 449 memcpy(x, r, sizeof(uint8_t) * num); 450 } 451 452 static void xlnx_zynqmp_qspips_flush_fifo_g(XlnxZynqMPQSPIPS *s) 453 { 454 while (s->regs[R_GQSPI_DATA_STS] || !fifo32_is_empty(&s->fifo_g)) { 455 uint8_t tx_rx[2] = { 0 }; 456 int num_stripes = 1; 457 uint8_t busses; 458 int i; 459 460 if (!s->regs[R_GQSPI_DATA_STS]) { 461 uint8_t imm; 462 463 s->regs[R_GQSPI_GF_SNAPSHOT] = fifo32_pop(&s->fifo_g); 464 DB_PRINT_L(0, "GQSPI command: %x\n", s->regs[R_GQSPI_GF_SNAPSHOT]); 465 if (!s->regs[R_GQSPI_GF_SNAPSHOT]) { 466 DB_PRINT_L(0, "Dummy GQSPI Delay Command Entry, Do nothing"); 467 continue; 468 } 469 xlnx_zynqmp_qspips_update_cs_lines(s); 470 471 imm = ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, IMMEDIATE_DATA); 472 if (!ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, DATA_XFER)) { 473 /* immedate transfer */ 474 if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, TRANSMIT) || 475 ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, RECIEVE)) { 476 s->regs[R_GQSPI_DATA_STS] = 1; 477 /* CS setup/hold - do nothing */ 478 } else { 479 s->regs[R_GQSPI_DATA_STS] = 0; 480 } 481 } else if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, EXPONENT)) { 482 if (imm > 31) { 483 qemu_log_mask(LOG_UNIMP, "QSPI exponential transfer too" 484 " long - 2 ^ %" PRId8 " requested\n", imm); 485 } 486 s->regs[R_GQSPI_DATA_STS] = 1ul << imm; 487 } else { 488 s->regs[R_GQSPI_DATA_STS] = imm; 489 } 490 } 491 /* Zero length transfer check */ 492 if (!s->regs[R_GQSPI_DATA_STS]) { 493 continue; 494 } 495 if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, RECIEVE) && 496 fifo8_is_full(&s->rx_fifo_g)) { 497 /* No space in RX fifo for transfer - try again later */ 498 return; 499 } 500 if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, STRIPE) && 501 (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, TRANSMIT) || 502 ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, RECIEVE))) { 503 num_stripes = 2; 504 } 505 if (!ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, DATA_XFER)) { 506 tx_rx[0] = ARRAY_FIELD_EX32(s->regs, 507 GQSPI_GF_SNAPSHOT, IMMEDIATE_DATA); 508 } else if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, TRANSMIT)) { 509 for (i = 0; i < num_stripes; ++i) { 510 if (!fifo8_is_empty(&s->tx_fifo_g)) { 511 tx_rx[i] = fifo8_pop(&s->tx_fifo_g); 512 s->tx_fifo_g_align++; 513 } else { 514 return; 515 } 516 } 517 } 518 if (num_stripes == 1) { 519 /* mirror */ 520 tx_rx[1] = tx_rx[0]; 521 } 522 busses = ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, DATA_BUS_SELECT); 523 for (i = 0; i < 2; ++i) { 524 DB_PRINT_L(1, "bus %d tx = %02x\n", i, tx_rx[i]); 525 tx_rx[i] = ssi_transfer(XILINX_SPIPS(s)->spi[i], tx_rx[i]); 526 DB_PRINT_L(1, "bus %d rx = %02x\n", i, tx_rx[i]); 527 } 528 if (s->regs[R_GQSPI_DATA_STS] > 1 && 529 busses == 0x3 && num_stripes == 2) { 530 s->regs[R_GQSPI_DATA_STS] -= 2; 531 } else if (s->regs[R_GQSPI_DATA_STS] > 0) { 532 s->regs[R_GQSPI_DATA_STS]--; 533 } 534 if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, RECIEVE)) { 535 for (i = 0; i < 2; ++i) { 536 if (busses & (1 << i)) { 537 DB_PRINT_L(1, "bus %d push_byte = %02x\n", i, tx_rx[i]); 538 fifo8_push(&s->rx_fifo_g, tx_rx[i]); 539 s->rx_fifo_g_align++; 540 } 541 } 542 } 543 if (!s->regs[R_GQSPI_DATA_STS]) { 544 for (; s->tx_fifo_g_align % 4; s->tx_fifo_g_align++) { 545 fifo8_pop(&s->tx_fifo_g); 546 } 547 for (; s->rx_fifo_g_align % 4; s->rx_fifo_g_align++) { 548 fifo8_push(&s->rx_fifo_g, 0); 549 } 550 } 551 } 552 } 553 554 static int xilinx_spips_num_dummies(XilinxQSPIPS *qs, uint8_t command) 555 { 556 if (!qs) { 557 /* The SPI device is not a QSPI device */ 558 return -1; 559 } 560 561 switch (command) { /* check for dummies */ 562 case READ: /* no dummy bytes/cycles */ 563 case PP: 564 case DPP: 565 case QPP: 566 case READ_4: 567 case PP_4: 568 case QPP_4: 569 return 0; 570 case FAST_READ: 571 case DOR: 572 case QOR: 573 case DOR_4: 574 case QOR_4: 575 return 1; 576 case DIOR: 577 case FAST_READ_4: 578 case DIOR_4: 579 return 2; 580 case QIOR: 581 case QIOR_4: 582 return 4; 583 default: 584 return -1; 585 } 586 } 587 588 static inline uint8_t get_addr_length(XilinxSPIPS *s, uint8_t cmd) 589 { 590 switch (cmd) { 591 case PP_4: 592 case QPP_4: 593 case READ_4: 594 case QIOR_4: 595 case FAST_READ_4: 596 case DOR_4: 597 case QOR_4: 598 case DIOR_4: 599 return 4; 600 default: 601 return (s->regs[R_CMND] & R_CMND_EXT_ADD) ? 4 : 3; 602 } 603 } 604 605 static void xilinx_spips_flush_txfifo(XilinxSPIPS *s) 606 { 607 int debug_level = 0; 608 XilinxQSPIPS *q = (XilinxQSPIPS *) object_dynamic_cast(OBJECT(s), 609 TYPE_XILINX_QSPIPS); 610 611 for (;;) { 612 int i; 613 uint8_t tx = 0; 614 uint8_t tx_rx[MAX_NUM_BUSSES] = { 0 }; 615 uint8_t dummy_cycles = 0; 616 uint8_t addr_length; 617 618 if (fifo8_is_empty(&s->tx_fifo)) { 619 xilinx_spips_update_ixr(s); 620 return; 621 } else if (s->snoop_state == SNOOP_STRIPING || 622 s->snoop_state == SNOOP_NONE) { 623 for (i = 0; i < num_effective_busses(s); ++i) { 624 tx_rx[i] = fifo8_pop(&s->tx_fifo); 625 } 626 stripe8(tx_rx, num_effective_busses(s), false); 627 } else if (s->snoop_state >= SNOOP_ADDR) { 628 tx = fifo8_pop(&s->tx_fifo); 629 for (i = 0; i < num_effective_busses(s); ++i) { 630 tx_rx[i] = tx; 631 } 632 } else { 633 /* Extract a dummy byte and generate dummy cycles according to the 634 * link state */ 635 tx = fifo8_pop(&s->tx_fifo); 636 dummy_cycles = 8 / s->link_state; 637 } 638 639 for (i = 0; i < num_effective_busses(s); ++i) { 640 int bus = num_effective_busses(s) - 1 - i; 641 if (dummy_cycles) { 642 int d; 643 for (d = 0; d < dummy_cycles; ++d) { 644 tx_rx[0] = ssi_transfer(s->spi[bus], (uint32_t)tx_rx[0]); 645 } 646 } else { 647 DB_PRINT_L(debug_level, "tx = %02x\n", tx_rx[i]); 648 tx_rx[i] = ssi_transfer(s->spi[bus], (uint32_t)tx_rx[i]); 649 DB_PRINT_L(debug_level, "rx = %02x\n", tx_rx[i]); 650 } 651 } 652 653 if (s->regs[R_CMND] & R_CMND_RXFIFO_DRAIN) { 654 DB_PRINT_L(debug_level, "dircarding drained rx byte\n"); 655 /* Do nothing */ 656 } else if (s->rx_discard) { 657 DB_PRINT_L(debug_level, "dircarding discarded rx byte\n"); 658 s->rx_discard -= 8 / s->link_state; 659 } else if (fifo8_is_full(&s->rx_fifo)) { 660 s->regs[R_INTR_STATUS] |= IXR_RX_FIFO_OVERFLOW; 661 DB_PRINT_L(0, "rx FIFO overflow"); 662 } else if (s->snoop_state == SNOOP_STRIPING) { 663 stripe8(tx_rx, num_effective_busses(s), true); 664 for (i = 0; i < num_effective_busses(s); ++i) { 665 fifo8_push(&s->rx_fifo, (uint8_t)tx_rx[i]); 666 DB_PRINT_L(debug_level, "pushing striped rx byte\n"); 667 } 668 } else { 669 DB_PRINT_L(debug_level, "pushing unstriped rx byte\n"); 670 fifo8_push(&s->rx_fifo, (uint8_t)tx_rx[0]); 671 } 672 673 if (s->link_state_next_when) { 674 s->link_state_next_when--; 675 if (!s->link_state_next_when) { 676 s->link_state = s->link_state_next; 677 } 678 } 679 680 DB_PRINT_L(debug_level, "initial snoop state: %x\n", 681 (unsigned)s->snoop_state); 682 switch (s->snoop_state) { 683 case (SNOOP_CHECKING): 684 /* Store the count of dummy bytes in the txfifo */ 685 s->cmd_dummies = xilinx_spips_num_dummies(q, tx); 686 addr_length = get_addr_length(s, tx); 687 if (s->cmd_dummies < 0) { 688 s->snoop_state = SNOOP_NONE; 689 } else { 690 s->snoop_state = SNOOP_ADDR + addr_length - 1; 691 } 692 switch (tx) { 693 case DPP: 694 case DOR: 695 case DOR_4: 696 s->link_state_next = 2; 697 s->link_state_next_when = addr_length + s->cmd_dummies; 698 break; 699 case QPP: 700 case QPP_4: 701 case QOR: 702 case QOR_4: 703 s->link_state_next = 4; 704 s->link_state_next_when = addr_length + s->cmd_dummies; 705 break; 706 case DIOR: 707 case DIOR_4: 708 s->link_state = 2; 709 break; 710 case QIOR: 711 case QIOR_4: 712 s->link_state = 4; 713 break; 714 } 715 break; 716 case (SNOOP_ADDR): 717 /* Address has been transmitted, transmit dummy cycles now if 718 * needed */ 719 if (s->cmd_dummies < 0) { 720 s->snoop_state = SNOOP_NONE; 721 } else { 722 s->snoop_state = s->cmd_dummies; 723 } 724 break; 725 case (SNOOP_STRIPING): 726 case (SNOOP_NONE): 727 /* Once we hit the boring stuff - squelch debug noise */ 728 if (!debug_level) { 729 DB_PRINT_L(0, "squelching debug info ....\n"); 730 debug_level = 1; 731 } 732 break; 733 default: 734 s->snoop_state--; 735 } 736 DB_PRINT_L(debug_level, "final snoop state: %x\n", 737 (unsigned)s->snoop_state); 738 } 739 } 740 741 static inline void tx_data_bytes(Fifo8 *fifo, uint32_t value, int num, bool be) 742 { 743 int i; 744 for (i = 0; i < num && !fifo8_is_full(fifo); ++i) { 745 if (be) { 746 fifo8_push(fifo, (uint8_t)(value >> 24)); 747 value <<= 8; 748 } else { 749 fifo8_push(fifo, (uint8_t)value); 750 value >>= 8; 751 } 752 } 753 } 754 755 static void xilinx_spips_check_zero_pump(XilinxSPIPS *s) 756 { 757 if (!s->regs[R_TRANSFER_SIZE]) { 758 return; 759 } 760 if (!fifo8_is_empty(&s->tx_fifo) && s->regs[R_CMND] & R_CMND_PUSH_WAIT) { 761 return; 762 } 763 /* 764 * The zero pump must never fill tx fifo such that rx overflow is 765 * possible 766 */ 767 while (s->regs[R_TRANSFER_SIZE] && 768 s->rx_fifo.num + s->tx_fifo.num < RXFF_A_Q - 3) { 769 /* endianess just doesn't matter when zero pumping */ 770 tx_data_bytes(&s->tx_fifo, 0, 4, false); 771 s->regs[R_TRANSFER_SIZE] &= ~0x03ull; 772 s->regs[R_TRANSFER_SIZE] -= 4; 773 } 774 } 775 776 static void xilinx_spips_check_flush(XilinxSPIPS *s) 777 { 778 if (s->man_start_com || 779 (!fifo8_is_empty(&s->tx_fifo) && 780 !(s->regs[R_CONFIG] & MAN_START_EN))) { 781 xilinx_spips_check_zero_pump(s); 782 xilinx_spips_flush_txfifo(s); 783 } 784 if (fifo8_is_empty(&s->tx_fifo) && !s->regs[R_TRANSFER_SIZE]) { 785 s->man_start_com = false; 786 } 787 xilinx_spips_update_ixr(s); 788 } 789 790 static void xlnx_zynqmp_qspips_check_flush(XlnxZynqMPQSPIPS *s) 791 { 792 bool gqspi_has_work = s->regs[R_GQSPI_DATA_STS] || 793 !fifo32_is_empty(&s->fifo_g); 794 795 if (ARRAY_FIELD_EX32(s->regs, GQSPI_SELECT, GENERIC_QSPI_EN)) { 796 if (s->man_start_com_g || (gqspi_has_work && 797 !ARRAY_FIELD_EX32(s->regs, GQSPI_CNFG, GEN_FIFO_START_MODE))) { 798 xlnx_zynqmp_qspips_flush_fifo_g(s); 799 } 800 } else { 801 xilinx_spips_check_flush(XILINX_SPIPS(s)); 802 } 803 if (!gqspi_has_work) { 804 s->man_start_com_g = false; 805 } 806 xlnx_zynqmp_qspips_update_ixr(s); 807 } 808 809 static inline int rx_data_bytes(Fifo8 *fifo, uint8_t *value, int max) 810 { 811 int i; 812 813 for (i = 0; i < max && !fifo8_is_empty(fifo); ++i) { 814 value[i] = fifo8_pop(fifo); 815 } 816 return max - i; 817 } 818 819 static const void *pop_buf(Fifo8 *fifo, uint32_t max, uint32_t *num) 820 { 821 void *ret; 822 823 if (max == 0 || max > fifo->num) { 824 abort(); 825 } 826 *num = MIN(fifo->capacity - fifo->head, max); 827 ret = &fifo->data[fifo->head]; 828 fifo->head += *num; 829 fifo->head %= fifo->capacity; 830 fifo->num -= *num; 831 return ret; 832 } 833 834 static void xlnx_zynqmp_qspips_notify(void *opaque) 835 { 836 XlnxZynqMPQSPIPS *rq = XLNX_ZYNQMP_QSPIPS(opaque); 837 XilinxSPIPS *s = XILINX_SPIPS(rq); 838 Fifo8 *recv_fifo; 839 840 if (ARRAY_FIELD_EX32(rq->regs, GQSPI_SELECT, GENERIC_QSPI_EN)) { 841 if (!(ARRAY_FIELD_EX32(rq->regs, GQSPI_CNFG, MODE_EN) == 2)) { 842 return; 843 } 844 recv_fifo = &rq->rx_fifo_g; 845 } else { 846 if (!(s->regs[R_CMND] & R_CMND_DMA_EN)) { 847 return; 848 } 849 recv_fifo = &s->rx_fifo; 850 } 851 while (recv_fifo->num >= 4 852 && stream_can_push(rq->dma, xlnx_zynqmp_qspips_notify, rq)) 853 { 854 size_t ret; 855 uint32_t num; 856 const void *rxd; 857 int len; 858 859 len = recv_fifo->num >= rq->dma_burst_size ? rq->dma_burst_size : 860 recv_fifo->num; 861 rxd = pop_buf(recv_fifo, len, &num); 862 863 memcpy(rq->dma_buf, rxd, num); 864 865 ret = stream_push(rq->dma, rq->dma_buf, num); 866 assert(ret == num); 867 xlnx_zynqmp_qspips_check_flush(rq); 868 } 869 } 870 871 static uint64_t xilinx_spips_read(void *opaque, hwaddr addr, 872 unsigned size) 873 { 874 XilinxSPIPS *s = opaque; 875 uint32_t mask = ~0; 876 uint32_t ret; 877 uint8_t rx_buf[4]; 878 int shortfall; 879 880 addr >>= 2; 881 switch (addr) { 882 case R_CONFIG: 883 mask = ~(R_CONFIG_RSVD | MAN_START_COM); 884 break; 885 case R_INTR_STATUS: 886 ret = s->regs[addr] & IXR_ALL; 887 s->regs[addr] = 0; 888 DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret); 889 xilinx_spips_update_ixr(s); 890 return ret; 891 case R_INTR_MASK: 892 mask = IXR_ALL; 893 break; 894 case R_EN: 895 mask = 0x1; 896 break; 897 case R_SLAVE_IDLE_COUNT: 898 mask = 0xFF; 899 break; 900 case R_MOD_ID: 901 mask = 0x01FFFFFF; 902 break; 903 case R_INTR_EN: 904 case R_INTR_DIS: 905 case R_TX_DATA: 906 mask = 0; 907 break; 908 case R_RX_DATA: 909 memset(rx_buf, 0, sizeof(rx_buf)); 910 shortfall = rx_data_bytes(&s->rx_fifo, rx_buf, s->num_txrx_bytes); 911 ret = s->regs[R_CONFIG] & R_CONFIG_ENDIAN ? 912 cpu_to_be32(*(uint32_t *)rx_buf) : 913 cpu_to_le32(*(uint32_t *)rx_buf); 914 if (!(s->regs[R_CONFIG] & R_CONFIG_ENDIAN)) { 915 ret <<= 8 * shortfall; 916 } 917 DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret); 918 xilinx_spips_check_flush(s); 919 xilinx_spips_update_ixr(s); 920 return ret; 921 } 922 DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4, 923 s->regs[addr] & mask); 924 return s->regs[addr] & mask; 925 926 } 927 928 static uint64_t xlnx_zynqmp_qspips_read(void *opaque, 929 hwaddr addr, unsigned size) 930 { 931 XlnxZynqMPQSPIPS *s = XLNX_ZYNQMP_QSPIPS(opaque); 932 uint32_t reg = addr / 4; 933 uint32_t ret; 934 uint8_t rx_buf[4]; 935 int shortfall; 936 937 if (reg <= R_MOD_ID) { 938 return xilinx_spips_read(opaque, addr, size); 939 } else { 940 switch (reg) { 941 case R_GQSPI_RXD: 942 if (fifo8_is_empty(&s->rx_fifo_g)) { 943 qemu_log_mask(LOG_GUEST_ERROR, 944 "Read from empty GQSPI RX FIFO\n"); 945 return 0; 946 } 947 memset(rx_buf, 0, sizeof(rx_buf)); 948 shortfall = rx_data_bytes(&s->rx_fifo_g, rx_buf, 949 XILINX_SPIPS(s)->num_txrx_bytes); 950 ret = ARRAY_FIELD_EX32(s->regs, GQSPI_CNFG, ENDIAN) ? 951 cpu_to_be32(*(uint32_t *)rx_buf) : 952 cpu_to_le32(*(uint32_t *)rx_buf); 953 if (!ARRAY_FIELD_EX32(s->regs, GQSPI_CNFG, ENDIAN)) { 954 ret <<= 8 * shortfall; 955 } 956 xlnx_zynqmp_qspips_check_flush(s); 957 xlnx_zynqmp_qspips_update_ixr(s); 958 return ret; 959 default: 960 return s->regs[reg]; 961 } 962 } 963 } 964 965 static void xilinx_spips_write(void *opaque, hwaddr addr, 966 uint64_t value, unsigned size) 967 { 968 int mask = ~0; 969 XilinxSPIPS *s = opaque; 970 971 DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr, (unsigned)value); 972 addr >>= 2; 973 switch (addr) { 974 case R_CONFIG: 975 mask = ~(R_CONFIG_RSVD | MAN_START_COM); 976 if ((value & MAN_START_COM) && (s->regs[R_CONFIG] & MAN_START_EN)) { 977 s->man_start_com = true; 978 } 979 break; 980 case R_INTR_STATUS: 981 mask = IXR_ALL; 982 s->regs[R_INTR_STATUS] &= ~(mask & value); 983 goto no_reg_update; 984 case R_INTR_DIS: 985 mask = IXR_ALL; 986 s->regs[R_INTR_MASK] &= ~(mask & value); 987 goto no_reg_update; 988 case R_INTR_EN: 989 mask = IXR_ALL; 990 s->regs[R_INTR_MASK] |= mask & value; 991 goto no_reg_update; 992 case R_EN: 993 mask = 0x1; 994 break; 995 case R_SLAVE_IDLE_COUNT: 996 mask = 0xFF; 997 break; 998 case R_RX_DATA: 999 case R_INTR_MASK: 1000 case R_MOD_ID: 1001 mask = 0; 1002 break; 1003 case R_TX_DATA: 1004 tx_data_bytes(&s->tx_fifo, (uint32_t)value, s->num_txrx_bytes, 1005 s->regs[R_CONFIG] & R_CONFIG_ENDIAN); 1006 goto no_reg_update; 1007 case R_TXD1: 1008 tx_data_bytes(&s->tx_fifo, (uint32_t)value, 1, 1009 s->regs[R_CONFIG] & R_CONFIG_ENDIAN); 1010 goto no_reg_update; 1011 case R_TXD2: 1012 tx_data_bytes(&s->tx_fifo, (uint32_t)value, 2, 1013 s->regs[R_CONFIG] & R_CONFIG_ENDIAN); 1014 goto no_reg_update; 1015 case R_TXD3: 1016 tx_data_bytes(&s->tx_fifo, (uint32_t)value, 3, 1017 s->regs[R_CONFIG] & R_CONFIG_ENDIAN); 1018 goto no_reg_update; 1019 } 1020 s->regs[addr] = (s->regs[addr] & ~mask) | (value & mask); 1021 no_reg_update: 1022 xilinx_spips_update_cs_lines(s); 1023 xilinx_spips_check_flush(s); 1024 xilinx_spips_update_cs_lines(s); 1025 xilinx_spips_update_ixr(s); 1026 } 1027 1028 static const MemoryRegionOps spips_ops = { 1029 .read = xilinx_spips_read, 1030 .write = xilinx_spips_write, 1031 .endianness = DEVICE_LITTLE_ENDIAN, 1032 }; 1033 1034 static void xilinx_qspips_invalidate_mmio_ptr(XilinxQSPIPS *q) 1035 { 1036 q->lqspi_cached_addr = ~0ULL; 1037 } 1038 1039 static void xilinx_qspips_write(void *opaque, hwaddr addr, 1040 uint64_t value, unsigned size) 1041 { 1042 XilinxQSPIPS *q = XILINX_QSPIPS(opaque); 1043 XilinxSPIPS *s = XILINX_SPIPS(opaque); 1044 1045 xilinx_spips_write(opaque, addr, value, size); 1046 addr >>= 2; 1047 1048 if (addr == R_LQSPI_CFG) { 1049 xilinx_qspips_invalidate_mmio_ptr(q); 1050 } 1051 if (s->regs[R_CMND] & R_CMND_RXFIFO_DRAIN) { 1052 fifo8_reset(&s->rx_fifo); 1053 } 1054 } 1055 1056 static void xlnx_zynqmp_qspips_write(void *opaque, hwaddr addr, 1057 uint64_t value, unsigned size) 1058 { 1059 XlnxZynqMPQSPIPS *s = XLNX_ZYNQMP_QSPIPS(opaque); 1060 uint32_t reg = addr / 4; 1061 1062 if (reg <= R_MOD_ID) { 1063 xilinx_qspips_write(opaque, addr, value, size); 1064 } else { 1065 switch (reg) { 1066 case R_GQSPI_CNFG: 1067 if (FIELD_EX32(value, GQSPI_CNFG, GEN_FIFO_START) && 1068 ARRAY_FIELD_EX32(s->regs, GQSPI_CNFG, GEN_FIFO_START_MODE)) { 1069 s->man_start_com_g = true; 1070 } 1071 s->regs[reg] = value & ~(R_GQSPI_CNFG_GEN_FIFO_START_MASK); 1072 break; 1073 case R_GQSPI_GEN_FIFO: 1074 if (!fifo32_is_full(&s->fifo_g)) { 1075 fifo32_push(&s->fifo_g, value); 1076 } 1077 break; 1078 case R_GQSPI_TXD: 1079 tx_data_bytes(&s->tx_fifo_g, (uint32_t)value, 4, 1080 ARRAY_FIELD_EX32(s->regs, GQSPI_CNFG, ENDIAN)); 1081 break; 1082 case R_GQSPI_FIFO_CTRL: 1083 if (FIELD_EX32(value, GQSPI_FIFO_CTRL, GENERIC_FIFO_RESET)) { 1084 fifo32_reset(&s->fifo_g); 1085 } 1086 if (FIELD_EX32(value, GQSPI_FIFO_CTRL, TX_FIFO_RESET)) { 1087 fifo8_reset(&s->tx_fifo_g); 1088 } 1089 if (FIELD_EX32(value, GQSPI_FIFO_CTRL, RX_FIFO_RESET)) { 1090 fifo8_reset(&s->rx_fifo_g); 1091 } 1092 break; 1093 case R_GQSPI_IDR: 1094 s->regs[R_GQSPI_IMR] |= value; 1095 break; 1096 case R_GQSPI_IER: 1097 s->regs[R_GQSPI_IMR] &= ~value; 1098 break; 1099 case R_GQSPI_ISR: 1100 s->regs[R_GQSPI_ISR] &= ~value; 1101 break; 1102 case R_GQSPI_IMR: 1103 case R_GQSPI_RXD: 1104 case R_GQSPI_GF_SNAPSHOT: 1105 case R_GQSPI_MOD_ID: 1106 break; 1107 default: 1108 s->regs[reg] = value; 1109 break; 1110 } 1111 xlnx_zynqmp_qspips_update_cs_lines(s); 1112 xlnx_zynqmp_qspips_check_flush(s); 1113 xlnx_zynqmp_qspips_update_cs_lines(s); 1114 xlnx_zynqmp_qspips_update_ixr(s); 1115 } 1116 xlnx_zynqmp_qspips_notify(s); 1117 } 1118 1119 static const MemoryRegionOps qspips_ops = { 1120 .read = xilinx_spips_read, 1121 .write = xilinx_qspips_write, 1122 .endianness = DEVICE_LITTLE_ENDIAN, 1123 }; 1124 1125 static const MemoryRegionOps xlnx_zynqmp_qspips_ops = { 1126 .read = xlnx_zynqmp_qspips_read, 1127 .write = xlnx_zynqmp_qspips_write, 1128 .endianness = DEVICE_LITTLE_ENDIAN, 1129 }; 1130 1131 #define LQSPI_CACHE_SIZE 1024 1132 1133 static void lqspi_load_cache(void *opaque, hwaddr addr) 1134 { 1135 XilinxQSPIPS *q = opaque; 1136 XilinxSPIPS *s = opaque; 1137 int i; 1138 int flash_addr = ((addr & ~(LQSPI_CACHE_SIZE - 1)) 1139 / num_effective_busses(s)); 1140 int slave = flash_addr >> LQSPI_ADDRESS_BITS; 1141 int cache_entry = 0; 1142 uint32_t u_page_save = s->regs[R_LQSPI_STS] & ~LQSPI_CFG_U_PAGE; 1143 1144 if (addr < q->lqspi_cached_addr || 1145 addr > q->lqspi_cached_addr + LQSPI_CACHE_SIZE - 4) { 1146 xilinx_qspips_invalidate_mmio_ptr(q); 1147 s->regs[R_LQSPI_STS] &= ~LQSPI_CFG_U_PAGE; 1148 s->regs[R_LQSPI_STS] |= slave ? LQSPI_CFG_U_PAGE : 0; 1149 1150 DB_PRINT_L(0, "config reg status: %08x\n", s->regs[R_LQSPI_CFG]); 1151 1152 fifo8_reset(&s->tx_fifo); 1153 fifo8_reset(&s->rx_fifo); 1154 1155 /* instruction */ 1156 DB_PRINT_L(0, "pushing read instruction: %02x\n", 1157 (unsigned)(uint8_t)(s->regs[R_LQSPI_CFG] & 1158 LQSPI_CFG_INST_CODE)); 1159 fifo8_push(&s->tx_fifo, s->regs[R_LQSPI_CFG] & LQSPI_CFG_INST_CODE); 1160 /* read address */ 1161 DB_PRINT_L(0, "pushing read address %06x\n", flash_addr); 1162 if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_ADDR4) { 1163 fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 24)); 1164 } 1165 fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 16)); 1166 fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 8)); 1167 fifo8_push(&s->tx_fifo, (uint8_t)flash_addr); 1168 /* mode bits */ 1169 if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_MODE_EN) { 1170 fifo8_push(&s->tx_fifo, extract32(s->regs[R_LQSPI_CFG], 1171 LQSPI_CFG_MODE_SHIFT, 1172 LQSPI_CFG_MODE_WIDTH)); 1173 } 1174 /* dummy bytes */ 1175 for (i = 0; i < (extract32(s->regs[R_LQSPI_CFG], LQSPI_CFG_DUMMY_SHIFT, 1176 LQSPI_CFG_DUMMY_WIDTH)); ++i) { 1177 DB_PRINT_L(0, "pushing dummy byte\n"); 1178 fifo8_push(&s->tx_fifo, 0); 1179 } 1180 xilinx_spips_update_cs_lines(s); 1181 xilinx_spips_flush_txfifo(s); 1182 fifo8_reset(&s->rx_fifo); 1183 1184 DB_PRINT_L(0, "starting QSPI data read\n"); 1185 1186 while (cache_entry < LQSPI_CACHE_SIZE) { 1187 for (i = 0; i < 64; ++i) { 1188 tx_data_bytes(&s->tx_fifo, 0, 1, false); 1189 } 1190 xilinx_spips_flush_txfifo(s); 1191 for (i = 0; i < 64; ++i) { 1192 rx_data_bytes(&s->rx_fifo, &q->lqspi_buf[cache_entry++], 1); 1193 } 1194 } 1195 1196 s->regs[R_LQSPI_STS] &= ~LQSPI_CFG_U_PAGE; 1197 s->regs[R_LQSPI_STS] |= u_page_save; 1198 xilinx_spips_update_cs_lines(s); 1199 1200 q->lqspi_cached_addr = flash_addr * num_effective_busses(s); 1201 } 1202 } 1203 1204 static uint64_t 1205 lqspi_read(void *opaque, hwaddr addr, unsigned int size) 1206 { 1207 XilinxQSPIPS *q = opaque; 1208 uint32_t ret; 1209 1210 if (addr >= q->lqspi_cached_addr && 1211 addr <= q->lqspi_cached_addr + LQSPI_CACHE_SIZE - 4) { 1212 uint8_t *retp = &q->lqspi_buf[addr - q->lqspi_cached_addr]; 1213 ret = cpu_to_le32(*(uint32_t *)retp); 1214 DB_PRINT_L(1, "addr: %08x, data: %08x\n", (unsigned)addr, 1215 (unsigned)ret); 1216 return ret; 1217 } else { 1218 lqspi_load_cache(opaque, addr); 1219 return lqspi_read(opaque, addr, size); 1220 } 1221 } 1222 1223 static const MemoryRegionOps lqspi_ops = { 1224 .read = lqspi_read, 1225 .endianness = DEVICE_NATIVE_ENDIAN, 1226 .valid = { 1227 .min_access_size = 1, 1228 .max_access_size = 4 1229 } 1230 }; 1231 1232 static void xilinx_spips_realize(DeviceState *dev, Error **errp) 1233 { 1234 XilinxSPIPS *s = XILINX_SPIPS(dev); 1235 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 1236 XilinxSPIPSClass *xsc = XILINX_SPIPS_GET_CLASS(s); 1237 qemu_irq *cs; 1238 int i; 1239 1240 DB_PRINT_L(0, "realized spips\n"); 1241 1242 if (s->num_busses > MAX_NUM_BUSSES) { 1243 error_setg(errp, 1244 "requested number of SPI busses %u exceeds maximum %d", 1245 s->num_busses, MAX_NUM_BUSSES); 1246 return; 1247 } 1248 if (s->num_busses < MIN_NUM_BUSSES) { 1249 error_setg(errp, 1250 "requested number of SPI busses %u is below minimum %d", 1251 s->num_busses, MIN_NUM_BUSSES); 1252 return; 1253 } 1254 1255 s->spi = g_new(SSIBus *, s->num_busses); 1256 for (i = 0; i < s->num_busses; ++i) { 1257 char bus_name[16]; 1258 snprintf(bus_name, 16, "spi%d", i); 1259 s->spi[i] = ssi_create_bus(dev, bus_name); 1260 } 1261 1262 s->cs_lines = g_new0(qemu_irq, s->num_cs * s->num_busses); 1263 s->cs_lines_state = g_new0(bool, s->num_cs * s->num_busses); 1264 for (i = 0, cs = s->cs_lines; i < s->num_busses; ++i, cs += s->num_cs) { 1265 ssi_auto_connect_slaves(DEVICE(s), cs, s->spi[i]); 1266 } 1267 1268 sysbus_init_irq(sbd, &s->irq); 1269 for (i = 0; i < s->num_cs * s->num_busses; ++i) { 1270 sysbus_init_irq(sbd, &s->cs_lines[i]); 1271 } 1272 1273 memory_region_init_io(&s->iomem, OBJECT(s), xsc->reg_ops, s, 1274 "spi", XLNX_ZYNQMP_SPIPS_R_MAX * 4); 1275 sysbus_init_mmio(sbd, &s->iomem); 1276 1277 s->irqline = -1; 1278 1279 fifo8_create(&s->rx_fifo, xsc->rx_fifo_size); 1280 fifo8_create(&s->tx_fifo, xsc->tx_fifo_size); 1281 } 1282 1283 static void xilinx_qspips_realize(DeviceState *dev, Error **errp) 1284 { 1285 XilinxSPIPS *s = XILINX_SPIPS(dev); 1286 XilinxQSPIPS *q = XILINX_QSPIPS(dev); 1287 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 1288 1289 DB_PRINT_L(0, "realized qspips\n"); 1290 1291 s->num_busses = 2; 1292 s->num_cs = 2; 1293 s->num_txrx_bytes = 4; 1294 1295 xilinx_spips_realize(dev, errp); 1296 memory_region_init_io(&s->mmlqspi, OBJECT(s), &lqspi_ops, s, "lqspi", 1297 (1 << LQSPI_ADDRESS_BITS) * 2); 1298 sysbus_init_mmio(sbd, &s->mmlqspi); 1299 1300 q->lqspi_cached_addr = ~0ULL; 1301 } 1302 1303 static void xlnx_zynqmp_qspips_realize(DeviceState *dev, Error **errp) 1304 { 1305 XlnxZynqMPQSPIPS *s = XLNX_ZYNQMP_QSPIPS(dev); 1306 XilinxSPIPSClass *xsc = XILINX_SPIPS_GET_CLASS(s); 1307 1308 if (s->dma_burst_size > QSPI_DMA_MAX_BURST_SIZE) { 1309 error_setg(errp, 1310 "qspi dma burst size %u exceeds maximum limit %d", 1311 s->dma_burst_size, QSPI_DMA_MAX_BURST_SIZE); 1312 return; 1313 } 1314 xilinx_qspips_realize(dev, errp); 1315 fifo8_create(&s->rx_fifo_g, xsc->rx_fifo_size); 1316 fifo8_create(&s->tx_fifo_g, xsc->tx_fifo_size); 1317 fifo32_create(&s->fifo_g, 32); 1318 } 1319 1320 static void xlnx_zynqmp_qspips_init(Object *obj) 1321 { 1322 XlnxZynqMPQSPIPS *rq = XLNX_ZYNQMP_QSPIPS(obj); 1323 1324 object_property_add_link(obj, "stream-connected-dma", TYPE_STREAM_SLAVE, 1325 (Object **)&rq->dma, 1326 object_property_allow_set_link, 1327 OBJ_PROP_LINK_STRONG, 1328 NULL); 1329 } 1330 1331 static int xilinx_spips_post_load(void *opaque, int version_id) 1332 { 1333 xilinx_spips_update_ixr((XilinxSPIPS *)opaque); 1334 xilinx_spips_update_cs_lines((XilinxSPIPS *)opaque); 1335 return 0; 1336 } 1337 1338 static const VMStateDescription vmstate_xilinx_spips = { 1339 .name = "xilinx_spips", 1340 .version_id = 2, 1341 .minimum_version_id = 2, 1342 .post_load = xilinx_spips_post_load, 1343 .fields = (VMStateField[]) { 1344 VMSTATE_FIFO8(tx_fifo, XilinxSPIPS), 1345 VMSTATE_FIFO8(rx_fifo, XilinxSPIPS), 1346 VMSTATE_UINT32_ARRAY(regs, XilinxSPIPS, XLNX_SPIPS_R_MAX), 1347 VMSTATE_UINT8(snoop_state, XilinxSPIPS), 1348 VMSTATE_END_OF_LIST() 1349 } 1350 }; 1351 1352 static int xlnx_zynqmp_qspips_post_load(void *opaque, int version_id) 1353 { 1354 XlnxZynqMPQSPIPS *s = (XlnxZynqMPQSPIPS *)opaque; 1355 XilinxSPIPS *qs = XILINX_SPIPS(s); 1356 1357 if (ARRAY_FIELD_EX32(s->regs, GQSPI_SELECT, GENERIC_QSPI_EN) && 1358 fifo8_is_empty(&qs->rx_fifo) && fifo8_is_empty(&qs->tx_fifo)) { 1359 xlnx_zynqmp_qspips_update_ixr(s); 1360 xlnx_zynqmp_qspips_update_cs_lines(s); 1361 } 1362 return 0; 1363 } 1364 1365 static const VMStateDescription vmstate_xilinx_qspips = { 1366 .name = "xilinx_qspips", 1367 .version_id = 1, 1368 .minimum_version_id = 1, 1369 .fields = (VMStateField[]) { 1370 VMSTATE_STRUCT(parent_obj, XilinxQSPIPS, 0, 1371 vmstate_xilinx_spips, XilinxSPIPS), 1372 VMSTATE_END_OF_LIST() 1373 } 1374 }; 1375 1376 static const VMStateDescription vmstate_xlnx_zynqmp_qspips = { 1377 .name = "xlnx_zynqmp_qspips", 1378 .version_id = 1, 1379 .minimum_version_id = 1, 1380 .post_load = xlnx_zynqmp_qspips_post_load, 1381 .fields = (VMStateField[]) { 1382 VMSTATE_STRUCT(parent_obj, XlnxZynqMPQSPIPS, 0, 1383 vmstate_xilinx_qspips, XilinxQSPIPS), 1384 VMSTATE_FIFO8(tx_fifo_g, XlnxZynqMPQSPIPS), 1385 VMSTATE_FIFO8(rx_fifo_g, XlnxZynqMPQSPIPS), 1386 VMSTATE_FIFO32(fifo_g, XlnxZynqMPQSPIPS), 1387 VMSTATE_UINT32_ARRAY(regs, XlnxZynqMPQSPIPS, XLNX_ZYNQMP_SPIPS_R_MAX), 1388 VMSTATE_END_OF_LIST() 1389 } 1390 }; 1391 1392 static Property xilinx_zynqmp_qspips_properties[] = { 1393 DEFINE_PROP_UINT32("dma-burst-size", XlnxZynqMPQSPIPS, dma_burst_size, 64), 1394 DEFINE_PROP_END_OF_LIST(), 1395 }; 1396 1397 static Property xilinx_spips_properties[] = { 1398 DEFINE_PROP_UINT8("num-busses", XilinxSPIPS, num_busses, 1), 1399 DEFINE_PROP_UINT8("num-ss-bits", XilinxSPIPS, num_cs, 4), 1400 DEFINE_PROP_UINT8("num-txrx-bytes", XilinxSPIPS, num_txrx_bytes, 1), 1401 DEFINE_PROP_END_OF_LIST(), 1402 }; 1403 1404 static void xilinx_qspips_class_init(ObjectClass *klass, void * data) 1405 { 1406 DeviceClass *dc = DEVICE_CLASS(klass); 1407 XilinxSPIPSClass *xsc = XILINX_SPIPS_CLASS(klass); 1408 1409 dc->realize = xilinx_qspips_realize; 1410 xsc->reg_ops = &qspips_ops; 1411 xsc->rx_fifo_size = RXFF_A_Q; 1412 xsc->tx_fifo_size = TXFF_A_Q; 1413 } 1414 1415 static void xilinx_spips_class_init(ObjectClass *klass, void *data) 1416 { 1417 DeviceClass *dc = DEVICE_CLASS(klass); 1418 XilinxSPIPSClass *xsc = XILINX_SPIPS_CLASS(klass); 1419 1420 dc->realize = xilinx_spips_realize; 1421 dc->reset = xilinx_spips_reset; 1422 dc->props = xilinx_spips_properties; 1423 dc->vmsd = &vmstate_xilinx_spips; 1424 1425 xsc->reg_ops = &spips_ops; 1426 xsc->rx_fifo_size = RXFF_A; 1427 xsc->tx_fifo_size = TXFF_A; 1428 } 1429 1430 static void xlnx_zynqmp_qspips_class_init(ObjectClass *klass, void * data) 1431 { 1432 DeviceClass *dc = DEVICE_CLASS(klass); 1433 XilinxSPIPSClass *xsc = XILINX_SPIPS_CLASS(klass); 1434 1435 dc->realize = xlnx_zynqmp_qspips_realize; 1436 dc->reset = xlnx_zynqmp_qspips_reset; 1437 dc->vmsd = &vmstate_xlnx_zynqmp_qspips; 1438 dc->props = xilinx_zynqmp_qspips_properties; 1439 xsc->reg_ops = &xlnx_zynqmp_qspips_ops; 1440 xsc->rx_fifo_size = RXFF_A_Q; 1441 xsc->tx_fifo_size = TXFF_A_Q; 1442 } 1443 1444 static const TypeInfo xilinx_spips_info = { 1445 .name = TYPE_XILINX_SPIPS, 1446 .parent = TYPE_SYS_BUS_DEVICE, 1447 .instance_size = sizeof(XilinxSPIPS), 1448 .class_init = xilinx_spips_class_init, 1449 .class_size = sizeof(XilinxSPIPSClass), 1450 }; 1451 1452 static const TypeInfo xilinx_qspips_info = { 1453 .name = TYPE_XILINX_QSPIPS, 1454 .parent = TYPE_XILINX_SPIPS, 1455 .instance_size = sizeof(XilinxQSPIPS), 1456 .class_init = xilinx_qspips_class_init, 1457 }; 1458 1459 static const TypeInfo xlnx_zynqmp_qspips_info = { 1460 .name = TYPE_XLNX_ZYNQMP_QSPIPS, 1461 .parent = TYPE_XILINX_QSPIPS, 1462 .instance_size = sizeof(XlnxZynqMPQSPIPS), 1463 .instance_init = xlnx_zynqmp_qspips_init, 1464 .class_init = xlnx_zynqmp_qspips_class_init, 1465 }; 1466 1467 static void xilinx_spips_register_types(void) 1468 { 1469 type_register_static(&xilinx_spips_info); 1470 type_register_static(&xilinx_qspips_info); 1471 type_register_static(&xlnx_zynqmp_qspips_info); 1472 } 1473 1474 type_init(xilinx_spips_register_types) 1475