1 /* 2 * QEMU model of the Xilinx Zynq SPI controller 3 * 4 * Copyright (c) 2012 Peter A. G. Crosthwaite 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "hw/sysbus.h" 27 #include "sysemu/sysemu.h" 28 #include "hw/ptimer.h" 29 #include "qemu/log.h" 30 #include "qemu/fifo8.h" 31 #include "hw/ssi/ssi.h" 32 #include "qemu/bitops.h" 33 #include "hw/ssi/xilinx_spips.h" 34 35 #ifndef XILINX_SPIPS_ERR_DEBUG 36 #define XILINX_SPIPS_ERR_DEBUG 0 37 #endif 38 39 #define DB_PRINT_L(level, ...) do { \ 40 if (XILINX_SPIPS_ERR_DEBUG > (level)) { \ 41 fprintf(stderr, ": %s: ", __func__); \ 42 fprintf(stderr, ## __VA_ARGS__); \ 43 } \ 44 } while (0); 45 46 /* config register */ 47 #define R_CONFIG (0x00 / 4) 48 #define IFMODE (1U << 31) 49 #define ENDIAN (1 << 26) 50 #define MODEFAIL_GEN_EN (1 << 17) 51 #define MAN_START_COM (1 << 16) 52 #define MAN_START_EN (1 << 15) 53 #define MANUAL_CS (1 << 14) 54 #define CS (0xF << 10) 55 #define CS_SHIFT (10) 56 #define PERI_SEL (1 << 9) 57 #define REF_CLK (1 << 8) 58 #define FIFO_WIDTH (3 << 6) 59 #define BAUD_RATE_DIV (7 << 3) 60 #define CLK_PH (1 << 2) 61 #define CLK_POL (1 << 1) 62 #define MODE_SEL (1 << 0) 63 #define R_CONFIG_RSVD (0x7bf40000) 64 65 /* interrupt mechanism */ 66 #define R_INTR_STATUS (0x04 / 4) 67 #define R_INTR_EN (0x08 / 4) 68 #define R_INTR_DIS (0x0C / 4) 69 #define R_INTR_MASK (0x10 / 4) 70 #define IXR_TX_FIFO_UNDERFLOW (1 << 6) 71 #define IXR_RX_FIFO_FULL (1 << 5) 72 #define IXR_RX_FIFO_NOT_EMPTY (1 << 4) 73 #define IXR_TX_FIFO_FULL (1 << 3) 74 #define IXR_TX_FIFO_NOT_FULL (1 << 2) 75 #define IXR_TX_FIFO_MODE_FAIL (1 << 1) 76 #define IXR_RX_FIFO_OVERFLOW (1 << 0) 77 #define IXR_ALL ((IXR_TX_FIFO_UNDERFLOW<<1)-1) 78 79 #define R_EN (0x14 / 4) 80 #define R_DELAY (0x18 / 4) 81 #define R_TX_DATA (0x1C / 4) 82 #define R_RX_DATA (0x20 / 4) 83 #define R_SLAVE_IDLE_COUNT (0x24 / 4) 84 #define R_TX_THRES (0x28 / 4) 85 #define R_RX_THRES (0x2C / 4) 86 #define R_TXD1 (0x80 / 4) 87 #define R_TXD2 (0x84 / 4) 88 #define R_TXD3 (0x88 / 4) 89 90 #define R_LQSPI_CFG (0xa0 / 4) 91 #define R_LQSPI_CFG_RESET 0x03A002EB 92 #define LQSPI_CFG_LQ_MODE (1U << 31) 93 #define LQSPI_CFG_TWO_MEM (1 << 30) 94 #define LQSPI_CFG_SEP_BUS (1 << 30) 95 #define LQSPI_CFG_U_PAGE (1 << 28) 96 #define LQSPI_CFG_MODE_EN (1 << 25) 97 #define LQSPI_CFG_MODE_WIDTH 8 98 #define LQSPI_CFG_MODE_SHIFT 16 99 #define LQSPI_CFG_DUMMY_WIDTH 3 100 #define LQSPI_CFG_DUMMY_SHIFT 8 101 #define LQSPI_CFG_INST_CODE 0xFF 102 103 #define R_LQSPI_STS (0xA4 / 4) 104 #define LQSPI_STS_WR_RECVD (1 << 1) 105 106 #define R_MOD_ID (0xFC / 4) 107 108 /* size of TXRX FIFOs */ 109 #define RXFF_A 32 110 #define TXFF_A 32 111 112 #define RXFF_A_Q (64 * 4) 113 #define TXFF_A_Q (64 * 4) 114 115 /* 16MB per linear region */ 116 #define LQSPI_ADDRESS_BITS 24 117 /* Bite off 4k chunks at a time */ 118 #define LQSPI_CACHE_SIZE 1024 119 120 #define SNOOP_CHECKING 0xFF 121 #define SNOOP_NONE 0xFE 122 #define SNOOP_STRIPING 0 123 124 typedef enum { 125 READ = 0x3, 126 FAST_READ = 0xb, 127 DOR = 0x3b, 128 QOR = 0x6b, 129 DIOR = 0xbb, 130 QIOR = 0xeb, 131 132 PP = 0x2, 133 DPP = 0xa2, 134 QPP = 0x32, 135 } FlashCMD; 136 137 typedef struct { 138 XilinxSPIPS parent_obj; 139 140 uint8_t lqspi_buf[LQSPI_CACHE_SIZE]; 141 hwaddr lqspi_cached_addr; 142 } XilinxQSPIPS; 143 144 typedef struct XilinxSPIPSClass { 145 SysBusDeviceClass parent_class; 146 147 const MemoryRegionOps *reg_ops; 148 149 uint32_t rx_fifo_size; 150 uint32_t tx_fifo_size; 151 } XilinxSPIPSClass; 152 153 static inline int num_effective_busses(XilinxSPIPS *s) 154 { 155 return (s->regs[R_LQSPI_CFG] & LQSPI_CFG_SEP_BUS && 156 s->regs[R_LQSPI_CFG] & LQSPI_CFG_TWO_MEM) ? s->num_busses : 1; 157 } 158 159 static inline bool xilinx_spips_cs_is_set(XilinxSPIPS *s, int i, int field) 160 { 161 return ~field & (1 << i) && (s->regs[R_CONFIG] & MANUAL_CS 162 || !fifo8_is_empty(&s->tx_fifo)); 163 } 164 165 static void xilinx_spips_update_cs_lines(XilinxSPIPS *s) 166 { 167 int i, j; 168 bool found = false; 169 int field = s->regs[R_CONFIG] >> CS_SHIFT; 170 171 for (i = 0; i < s->num_cs; i++) { 172 for (j = 0; j < num_effective_busses(s); j++) { 173 int upage = !!(s->regs[R_LQSPI_STS] & LQSPI_CFG_U_PAGE); 174 int cs_to_set = (j * s->num_cs + i + upage) % 175 (s->num_cs * s->num_busses); 176 177 if (xilinx_spips_cs_is_set(s, i, field) && !found) { 178 DB_PRINT_L(0, "selecting slave %d\n", i); 179 qemu_set_irq(s->cs_lines[cs_to_set], 0); 180 } else { 181 DB_PRINT_L(0, "deselecting slave %d\n", i); 182 qemu_set_irq(s->cs_lines[cs_to_set], 1); 183 } 184 } 185 if (xilinx_spips_cs_is_set(s, i, field)) { 186 found = true; 187 } 188 } 189 if (!found) { 190 s->snoop_state = SNOOP_CHECKING; 191 DB_PRINT_L(1, "moving to snoop check state\n"); 192 } 193 } 194 195 static void xilinx_spips_update_ixr(XilinxSPIPS *s) 196 { 197 if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_LQ_MODE) { 198 return; 199 } 200 /* These are set/cleared as they occur */ 201 s->regs[R_INTR_STATUS] &= (IXR_TX_FIFO_UNDERFLOW | IXR_RX_FIFO_OVERFLOW | 202 IXR_TX_FIFO_MODE_FAIL); 203 /* these are pure functions of fifo state, set them here */ 204 s->regs[R_INTR_STATUS] |= 205 (fifo8_is_full(&s->rx_fifo) ? IXR_RX_FIFO_FULL : 0) | 206 (s->rx_fifo.num >= s->regs[R_RX_THRES] ? IXR_RX_FIFO_NOT_EMPTY : 0) | 207 (fifo8_is_full(&s->tx_fifo) ? IXR_TX_FIFO_FULL : 0) | 208 (s->tx_fifo.num < s->regs[R_TX_THRES] ? IXR_TX_FIFO_NOT_FULL : 0); 209 /* drive external interrupt pin */ 210 int new_irqline = !!(s->regs[R_INTR_MASK] & s->regs[R_INTR_STATUS] & 211 IXR_ALL); 212 if (new_irqline != s->irqline) { 213 s->irqline = new_irqline; 214 qemu_set_irq(s->irq, s->irqline); 215 } 216 } 217 218 static void xilinx_spips_reset(DeviceState *d) 219 { 220 XilinxSPIPS *s = XILINX_SPIPS(d); 221 222 int i; 223 for (i = 0; i < XLNX_SPIPS_R_MAX; i++) { 224 s->regs[i] = 0; 225 } 226 227 fifo8_reset(&s->rx_fifo); 228 fifo8_reset(&s->rx_fifo); 229 /* non zero resets */ 230 s->regs[R_CONFIG] |= MODEFAIL_GEN_EN; 231 s->regs[R_SLAVE_IDLE_COUNT] = 0xFF; 232 s->regs[R_TX_THRES] = 1; 233 s->regs[R_RX_THRES] = 1; 234 /* FIXME: move magic number definition somewhere sensible */ 235 s->regs[R_MOD_ID] = 0x01090106; 236 s->regs[R_LQSPI_CFG] = R_LQSPI_CFG_RESET; 237 s->snoop_state = SNOOP_CHECKING; 238 xilinx_spips_update_ixr(s); 239 xilinx_spips_update_cs_lines(s); 240 } 241 242 /* N way (num) in place bit striper. Lay out row wise bits (LSB to MSB) 243 * column wise (from element 0 to N-1). num is the length of x, and dir 244 * reverses the direction of the transform. Best illustrated by example: 245 * Each digit in the below array is a single bit (num == 3): 246 * 247 * {{ 76543210, } ----- stripe (dir == false) -----> {{ FCheb630, } 248 * { hgfedcba, } { GDAfc741, } 249 * { HGFEDCBA, }} <---- upstripe (dir == true) ----- { HEBgda52, }} 250 */ 251 252 static inline void stripe8(uint8_t *x, int num, bool dir) 253 { 254 uint8_t r[num]; 255 memset(r, 0, sizeof(uint8_t) * num); 256 int idx[2] = {0, 0}; 257 int bit[2] = {0, 0}; 258 int d = dir; 259 260 for (idx[0] = 0; idx[0] < num; ++idx[0]) { 261 for (bit[0] = 0; bit[0] < 8; ++bit[0]) { 262 r[idx[d]] |= x[idx[!d]] & 1 << bit[!d] ? 1 << bit[d] : 0; 263 idx[1] = (idx[1] + 1) % num; 264 if (!idx[1]) { 265 bit[1]++; 266 } 267 } 268 } 269 memcpy(x, r, sizeof(uint8_t) * num); 270 } 271 272 static void xilinx_spips_flush_txfifo(XilinxSPIPS *s) 273 { 274 int debug_level = 0; 275 276 for (;;) { 277 int i; 278 uint8_t tx = 0; 279 uint8_t tx_rx[num_effective_busses(s)]; 280 281 if (fifo8_is_empty(&s->tx_fifo)) { 282 if (!(s->regs[R_LQSPI_CFG] & LQSPI_CFG_LQ_MODE)) { 283 s->regs[R_INTR_STATUS] |= IXR_TX_FIFO_UNDERFLOW; 284 } 285 xilinx_spips_update_ixr(s); 286 return; 287 } else if (s->snoop_state == SNOOP_STRIPING) { 288 for (i = 0; i < num_effective_busses(s); ++i) { 289 tx_rx[i] = fifo8_pop(&s->tx_fifo); 290 } 291 stripe8(tx_rx, num_effective_busses(s), false); 292 } else { 293 tx = fifo8_pop(&s->tx_fifo); 294 for (i = 0; i < num_effective_busses(s); ++i) { 295 tx_rx[i] = tx; 296 } 297 } 298 299 for (i = 0; i < num_effective_busses(s); ++i) { 300 DB_PRINT_L(debug_level, "tx = %02x\n", tx_rx[i]); 301 tx_rx[i] = ssi_transfer(s->spi[i], (uint32_t)tx_rx[i]); 302 DB_PRINT_L(debug_level, "rx = %02x\n", tx_rx[i]); 303 } 304 305 if (fifo8_is_full(&s->rx_fifo)) { 306 s->regs[R_INTR_STATUS] |= IXR_RX_FIFO_OVERFLOW; 307 DB_PRINT_L(0, "rx FIFO overflow"); 308 } else if (s->snoop_state == SNOOP_STRIPING) { 309 stripe8(tx_rx, num_effective_busses(s), true); 310 for (i = 0; i < num_effective_busses(s); ++i) { 311 fifo8_push(&s->rx_fifo, (uint8_t)tx_rx[i]); 312 } 313 } else { 314 fifo8_push(&s->rx_fifo, (uint8_t)tx_rx[0]); 315 } 316 317 DB_PRINT_L(debug_level, "initial snoop state: %x\n", 318 (unsigned)s->snoop_state); 319 switch (s->snoop_state) { 320 case (SNOOP_CHECKING): 321 switch (tx) { /* new instruction code */ 322 case READ: /* 3 address bytes, no dummy bytes/cycles */ 323 case PP: 324 case DPP: 325 case QPP: 326 s->snoop_state = 3; 327 break; 328 case FAST_READ: /* 3 address bytes, 1 dummy byte */ 329 case DOR: 330 case QOR: 331 case DIOR: /* FIXME: these vary between vendor - set to spansion */ 332 s->snoop_state = 4; 333 break; 334 case QIOR: /* 3 address bytes, 2 dummy bytes */ 335 s->snoop_state = 6; 336 break; 337 default: 338 s->snoop_state = SNOOP_NONE; 339 } 340 break; 341 case (SNOOP_STRIPING): 342 case (SNOOP_NONE): 343 /* Once we hit the boring stuff - squelch debug noise */ 344 if (!debug_level) { 345 DB_PRINT_L(0, "squelching debug info ....\n"); 346 debug_level = 1; 347 } 348 break; 349 default: 350 s->snoop_state--; 351 } 352 DB_PRINT_L(debug_level, "final snoop state: %x\n", 353 (unsigned)s->snoop_state); 354 } 355 } 356 357 static inline void rx_data_bytes(XilinxSPIPS *s, uint8_t *value, int max) 358 { 359 int i; 360 361 for (i = 0; i < max && !fifo8_is_empty(&s->rx_fifo); ++i) { 362 value[i] = fifo8_pop(&s->rx_fifo); 363 } 364 } 365 366 static uint64_t xilinx_spips_read(void *opaque, hwaddr addr, 367 unsigned size) 368 { 369 XilinxSPIPS *s = opaque; 370 uint32_t mask = ~0; 371 uint32_t ret; 372 uint8_t rx_buf[4]; 373 374 addr >>= 2; 375 switch (addr) { 376 case R_CONFIG: 377 mask = ~(R_CONFIG_RSVD | MAN_START_COM); 378 break; 379 case R_INTR_STATUS: 380 ret = s->regs[addr] & IXR_ALL; 381 s->regs[addr] = 0; 382 DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret); 383 return ret; 384 case R_INTR_MASK: 385 mask = IXR_ALL; 386 break; 387 case R_EN: 388 mask = 0x1; 389 break; 390 case R_SLAVE_IDLE_COUNT: 391 mask = 0xFF; 392 break; 393 case R_MOD_ID: 394 mask = 0x01FFFFFF; 395 break; 396 case R_INTR_EN: 397 case R_INTR_DIS: 398 case R_TX_DATA: 399 mask = 0; 400 break; 401 case R_RX_DATA: 402 memset(rx_buf, 0, sizeof(rx_buf)); 403 rx_data_bytes(s, rx_buf, s->num_txrx_bytes); 404 ret = s->regs[R_CONFIG] & ENDIAN ? cpu_to_be32(*(uint32_t *)rx_buf) 405 : cpu_to_le32(*(uint32_t *)rx_buf); 406 DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret); 407 xilinx_spips_update_ixr(s); 408 return ret; 409 } 410 DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4, 411 s->regs[addr] & mask); 412 return s->regs[addr] & mask; 413 414 } 415 416 static inline void tx_data_bytes(XilinxSPIPS *s, uint32_t value, int num) 417 { 418 int i; 419 for (i = 0; i < num && !fifo8_is_full(&s->tx_fifo); ++i) { 420 if (s->regs[R_CONFIG] & ENDIAN) { 421 fifo8_push(&s->tx_fifo, (uint8_t)(value >> 24)); 422 value <<= 8; 423 } else { 424 fifo8_push(&s->tx_fifo, (uint8_t)value); 425 value >>= 8; 426 } 427 } 428 } 429 430 static void xilinx_spips_write(void *opaque, hwaddr addr, 431 uint64_t value, unsigned size) 432 { 433 int mask = ~0; 434 int man_start_com = 0; 435 XilinxSPIPS *s = opaque; 436 437 DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr, (unsigned)value); 438 addr >>= 2; 439 switch (addr) { 440 case R_CONFIG: 441 mask = ~(R_CONFIG_RSVD | MAN_START_COM); 442 if (value & MAN_START_COM) { 443 man_start_com = 1; 444 } 445 break; 446 case R_INTR_STATUS: 447 mask = IXR_ALL; 448 s->regs[R_INTR_STATUS] &= ~(mask & value); 449 goto no_reg_update; 450 case R_INTR_DIS: 451 mask = IXR_ALL; 452 s->regs[R_INTR_MASK] &= ~(mask & value); 453 goto no_reg_update; 454 case R_INTR_EN: 455 mask = IXR_ALL; 456 s->regs[R_INTR_MASK] |= mask & value; 457 goto no_reg_update; 458 case R_EN: 459 mask = 0x1; 460 break; 461 case R_SLAVE_IDLE_COUNT: 462 mask = 0xFF; 463 break; 464 case R_RX_DATA: 465 case R_INTR_MASK: 466 case R_MOD_ID: 467 mask = 0; 468 break; 469 case R_TX_DATA: 470 tx_data_bytes(s, (uint32_t)value, s->num_txrx_bytes); 471 goto no_reg_update; 472 case R_TXD1: 473 tx_data_bytes(s, (uint32_t)value, 1); 474 goto no_reg_update; 475 case R_TXD2: 476 tx_data_bytes(s, (uint32_t)value, 2); 477 goto no_reg_update; 478 case R_TXD3: 479 tx_data_bytes(s, (uint32_t)value, 3); 480 goto no_reg_update; 481 } 482 s->regs[addr] = (s->regs[addr] & ~mask) | (value & mask); 483 no_reg_update: 484 xilinx_spips_update_cs_lines(s); 485 if ((man_start_com && s->regs[R_CONFIG] & MAN_START_EN) || 486 (fifo8_is_empty(&s->tx_fifo) && s->regs[R_CONFIG] & MAN_START_EN)) { 487 xilinx_spips_flush_txfifo(s); 488 } 489 xilinx_spips_update_cs_lines(s); 490 xilinx_spips_update_ixr(s); 491 } 492 493 static const MemoryRegionOps spips_ops = { 494 .read = xilinx_spips_read, 495 .write = xilinx_spips_write, 496 .endianness = DEVICE_LITTLE_ENDIAN, 497 }; 498 499 static void xilinx_qspips_write(void *opaque, hwaddr addr, 500 uint64_t value, unsigned size) 501 { 502 XilinxQSPIPS *q = XILINX_QSPIPS(opaque); 503 504 xilinx_spips_write(opaque, addr, value, size); 505 addr >>= 2; 506 507 if (addr == R_LQSPI_CFG) { 508 q->lqspi_cached_addr = ~0ULL; 509 } 510 } 511 512 static const MemoryRegionOps qspips_ops = { 513 .read = xilinx_spips_read, 514 .write = xilinx_qspips_write, 515 .endianness = DEVICE_LITTLE_ENDIAN, 516 }; 517 518 #define LQSPI_CACHE_SIZE 1024 519 520 static uint64_t 521 lqspi_read(void *opaque, hwaddr addr, unsigned int size) 522 { 523 int i; 524 XilinxQSPIPS *q = opaque; 525 XilinxSPIPS *s = opaque; 526 uint32_t ret; 527 528 if (addr >= q->lqspi_cached_addr && 529 addr <= q->lqspi_cached_addr + LQSPI_CACHE_SIZE - 4) { 530 uint8_t *retp = &q->lqspi_buf[addr - q->lqspi_cached_addr]; 531 ret = cpu_to_le32(*(uint32_t *)retp); 532 DB_PRINT_L(1, "addr: %08x, data: %08x\n", (unsigned)addr, 533 (unsigned)ret); 534 return ret; 535 } else { 536 int flash_addr = (addr / num_effective_busses(s)); 537 int slave = flash_addr >> LQSPI_ADDRESS_BITS; 538 int cache_entry = 0; 539 uint32_t u_page_save = s->regs[R_LQSPI_STS] & ~LQSPI_CFG_U_PAGE; 540 541 s->regs[R_LQSPI_STS] &= ~LQSPI_CFG_U_PAGE; 542 s->regs[R_LQSPI_STS] |= slave ? LQSPI_CFG_U_PAGE : 0; 543 544 DB_PRINT_L(0, "config reg status: %08x\n", s->regs[R_LQSPI_CFG]); 545 546 fifo8_reset(&s->tx_fifo); 547 fifo8_reset(&s->rx_fifo); 548 549 /* instruction */ 550 DB_PRINT_L(0, "pushing read instruction: %02x\n", 551 (unsigned)(uint8_t)(s->regs[R_LQSPI_CFG] & 552 LQSPI_CFG_INST_CODE)); 553 fifo8_push(&s->tx_fifo, s->regs[R_LQSPI_CFG] & LQSPI_CFG_INST_CODE); 554 /* read address */ 555 DB_PRINT_L(0, "pushing read address %06x\n", flash_addr); 556 fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 16)); 557 fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 8)); 558 fifo8_push(&s->tx_fifo, (uint8_t)flash_addr); 559 /* mode bits */ 560 if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_MODE_EN) { 561 fifo8_push(&s->tx_fifo, extract32(s->regs[R_LQSPI_CFG], 562 LQSPI_CFG_MODE_SHIFT, 563 LQSPI_CFG_MODE_WIDTH)); 564 } 565 /* dummy bytes */ 566 for (i = 0; i < (extract32(s->regs[R_LQSPI_CFG], LQSPI_CFG_DUMMY_SHIFT, 567 LQSPI_CFG_DUMMY_WIDTH)); ++i) { 568 DB_PRINT_L(0, "pushing dummy byte\n"); 569 fifo8_push(&s->tx_fifo, 0); 570 } 571 xilinx_spips_update_cs_lines(s); 572 xilinx_spips_flush_txfifo(s); 573 fifo8_reset(&s->rx_fifo); 574 575 DB_PRINT_L(0, "starting QSPI data read\n"); 576 577 while (cache_entry < LQSPI_CACHE_SIZE) { 578 for (i = 0; i < 64; ++i) { 579 tx_data_bytes(s, 0, 1); 580 } 581 xilinx_spips_flush_txfifo(s); 582 for (i = 0; i < 64; ++i) { 583 rx_data_bytes(s, &q->lqspi_buf[cache_entry++], 1); 584 } 585 } 586 587 s->regs[R_LQSPI_STS] &= ~LQSPI_CFG_U_PAGE; 588 s->regs[R_LQSPI_STS] |= u_page_save; 589 xilinx_spips_update_cs_lines(s); 590 591 q->lqspi_cached_addr = flash_addr * num_effective_busses(s); 592 return lqspi_read(opaque, addr, size); 593 } 594 } 595 596 static const MemoryRegionOps lqspi_ops = { 597 .read = lqspi_read, 598 .endianness = DEVICE_NATIVE_ENDIAN, 599 .valid = { 600 .min_access_size = 1, 601 .max_access_size = 4 602 } 603 }; 604 605 static void xilinx_spips_realize(DeviceState *dev, Error **errp) 606 { 607 XilinxSPIPS *s = XILINX_SPIPS(dev); 608 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 609 XilinxSPIPSClass *xsc = XILINX_SPIPS_GET_CLASS(s); 610 qemu_irq *cs; 611 int i; 612 613 DB_PRINT_L(0, "realized spips\n"); 614 615 s->spi = g_new(SSIBus *, s->num_busses); 616 for (i = 0; i < s->num_busses; ++i) { 617 char bus_name[16]; 618 snprintf(bus_name, 16, "spi%d", i); 619 s->spi[i] = ssi_create_bus(dev, bus_name); 620 } 621 622 s->cs_lines = g_new0(qemu_irq, s->num_cs * s->num_busses); 623 for (i = 0, cs = s->cs_lines; i < s->num_busses; ++i, cs += s->num_cs) { 624 ssi_auto_connect_slaves(DEVICE(s), cs, s->spi[i]); 625 } 626 627 sysbus_init_irq(sbd, &s->irq); 628 for (i = 0; i < s->num_cs * s->num_busses; ++i) { 629 sysbus_init_irq(sbd, &s->cs_lines[i]); 630 } 631 632 memory_region_init_io(&s->iomem, OBJECT(s), xsc->reg_ops, s, 633 "spi", XLNX_SPIPS_R_MAX * 4); 634 sysbus_init_mmio(sbd, &s->iomem); 635 636 s->irqline = -1; 637 638 fifo8_create(&s->rx_fifo, xsc->rx_fifo_size); 639 fifo8_create(&s->tx_fifo, xsc->tx_fifo_size); 640 } 641 642 static void xilinx_qspips_realize(DeviceState *dev, Error **errp) 643 { 644 XilinxSPIPS *s = XILINX_SPIPS(dev); 645 XilinxQSPIPS *q = XILINX_QSPIPS(dev); 646 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 647 648 DB_PRINT_L(0, "realized qspips\n"); 649 650 s->num_busses = 2; 651 s->num_cs = 2; 652 s->num_txrx_bytes = 4; 653 654 xilinx_spips_realize(dev, errp); 655 memory_region_init_io(&s->mmlqspi, OBJECT(s), &lqspi_ops, s, "lqspi", 656 (1 << LQSPI_ADDRESS_BITS) * 2); 657 sysbus_init_mmio(sbd, &s->mmlqspi); 658 659 q->lqspi_cached_addr = ~0ULL; 660 } 661 662 static int xilinx_spips_post_load(void *opaque, int version_id) 663 { 664 xilinx_spips_update_ixr((XilinxSPIPS *)opaque); 665 xilinx_spips_update_cs_lines((XilinxSPIPS *)opaque); 666 return 0; 667 } 668 669 static const VMStateDescription vmstate_xilinx_spips = { 670 .name = "xilinx_spips", 671 .version_id = 2, 672 .minimum_version_id = 2, 673 .post_load = xilinx_spips_post_load, 674 .fields = (VMStateField[]) { 675 VMSTATE_FIFO8(tx_fifo, XilinxSPIPS), 676 VMSTATE_FIFO8(rx_fifo, XilinxSPIPS), 677 VMSTATE_UINT32_ARRAY(regs, XilinxSPIPS, XLNX_SPIPS_R_MAX), 678 VMSTATE_UINT8(snoop_state, XilinxSPIPS), 679 VMSTATE_END_OF_LIST() 680 } 681 }; 682 683 static Property xilinx_spips_properties[] = { 684 DEFINE_PROP_UINT8("num-busses", XilinxSPIPS, num_busses, 1), 685 DEFINE_PROP_UINT8("num-ss-bits", XilinxSPIPS, num_cs, 4), 686 DEFINE_PROP_UINT8("num-txrx-bytes", XilinxSPIPS, num_txrx_bytes, 1), 687 DEFINE_PROP_END_OF_LIST(), 688 }; 689 690 static void xilinx_qspips_class_init(ObjectClass *klass, void * data) 691 { 692 DeviceClass *dc = DEVICE_CLASS(klass); 693 XilinxSPIPSClass *xsc = XILINX_SPIPS_CLASS(klass); 694 695 dc->realize = xilinx_qspips_realize; 696 xsc->reg_ops = &qspips_ops; 697 xsc->rx_fifo_size = RXFF_A_Q; 698 xsc->tx_fifo_size = TXFF_A_Q; 699 } 700 701 static void xilinx_spips_class_init(ObjectClass *klass, void *data) 702 { 703 DeviceClass *dc = DEVICE_CLASS(klass); 704 XilinxSPIPSClass *xsc = XILINX_SPIPS_CLASS(klass); 705 706 dc->realize = xilinx_spips_realize; 707 dc->reset = xilinx_spips_reset; 708 dc->props = xilinx_spips_properties; 709 dc->vmsd = &vmstate_xilinx_spips; 710 711 xsc->reg_ops = &spips_ops; 712 xsc->rx_fifo_size = RXFF_A; 713 xsc->tx_fifo_size = TXFF_A; 714 } 715 716 static const TypeInfo xilinx_spips_info = { 717 .name = TYPE_XILINX_SPIPS, 718 .parent = TYPE_SYS_BUS_DEVICE, 719 .instance_size = sizeof(XilinxSPIPS), 720 .class_init = xilinx_spips_class_init, 721 .class_size = sizeof(XilinxSPIPSClass), 722 }; 723 724 static const TypeInfo xilinx_qspips_info = { 725 .name = TYPE_XILINX_QSPIPS, 726 .parent = TYPE_XILINX_SPIPS, 727 .instance_size = sizeof(XilinxQSPIPS), 728 .class_init = xilinx_qspips_class_init, 729 }; 730 731 static void xilinx_spips_register_types(void) 732 { 733 type_register_static(&xilinx_spips_info); 734 type_register_static(&xilinx_qspips_info); 735 } 736 737 type_init(xilinx_spips_register_types) 738