xref: /openbmc/qemu/hw/ssi/xilinx_spips.c (revision 47d17c0ac310f3274489c74d29dce4656376be8c)
1 /*
2  * QEMU model of the Xilinx Zynq SPI controller
3  *
4  * Copyright (c) 2012 Peter A. G. Crosthwaite
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a copy
7  * of this software and associated documentation files (the "Software"), to deal
8  * in the Software without restriction, including without limitation the rights
9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10  * copies of the Software, and to permit persons to whom the Software is
11  * furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22  * THE SOFTWARE.
23  */
24 
25 #include "qemu/osdep.h"
26 #include "hw/sysbus.h"
27 #include "sysemu/sysemu.h"
28 #include "hw/ptimer.h"
29 #include "qemu/log.h"
30 #include "qemu/bitops.h"
31 #include "hw/ssi/xilinx_spips.h"
32 #include "qapi/error.h"
33 #include "hw/register.h"
34 #include "sysemu/dma.h"
35 #include "migration/blocker.h"
36 
37 #ifndef XILINX_SPIPS_ERR_DEBUG
38 #define XILINX_SPIPS_ERR_DEBUG 0
39 #endif
40 
41 #define DB_PRINT_L(level, ...) do { \
42     if (XILINX_SPIPS_ERR_DEBUG > (level)) { \
43         fprintf(stderr,  ": %s: ", __func__); \
44         fprintf(stderr, ## __VA_ARGS__); \
45     } \
46 } while (0)
47 
48 /* config register */
49 #define R_CONFIG            (0x00 / 4)
50 #define IFMODE              (1U << 31)
51 #define R_CONFIG_ENDIAN     (1 << 26)
52 #define MODEFAIL_GEN_EN     (1 << 17)
53 #define MAN_START_COM       (1 << 16)
54 #define MAN_START_EN        (1 << 15)
55 #define MANUAL_CS           (1 << 14)
56 #define CS                  (0xF << 10)
57 #define CS_SHIFT            (10)
58 #define PERI_SEL            (1 << 9)
59 #define REF_CLK             (1 << 8)
60 #define FIFO_WIDTH          (3 << 6)
61 #define BAUD_RATE_DIV       (7 << 3)
62 #define CLK_PH              (1 << 2)
63 #define CLK_POL             (1 << 1)
64 #define MODE_SEL            (1 << 0)
65 #define R_CONFIG_RSVD       (0x7bf40000)
66 
67 /* interrupt mechanism */
68 #define R_INTR_STATUS       (0x04 / 4)
69 #define R_INTR_STATUS_RESET (0x104)
70 #define R_INTR_EN           (0x08 / 4)
71 #define R_INTR_DIS          (0x0C / 4)
72 #define R_INTR_MASK         (0x10 / 4)
73 #define IXR_TX_FIFO_UNDERFLOW   (1 << 6)
74 /* Poll timeout not implemented */
75 #define IXR_RX_FIFO_EMPTY       (1 << 11)
76 #define IXR_GENERIC_FIFO_FULL   (1 << 10)
77 #define IXR_GENERIC_FIFO_NOT_FULL (1 << 9)
78 #define IXR_TX_FIFO_EMPTY       (1 << 8)
79 #define IXR_GENERIC_FIFO_EMPTY  (1 << 7)
80 #define IXR_RX_FIFO_FULL        (1 << 5)
81 #define IXR_RX_FIFO_NOT_EMPTY   (1 << 4)
82 #define IXR_TX_FIFO_FULL        (1 << 3)
83 #define IXR_TX_FIFO_NOT_FULL    (1 << 2)
84 #define IXR_TX_FIFO_MODE_FAIL   (1 << 1)
85 #define IXR_RX_FIFO_OVERFLOW    (1 << 0)
86 #define IXR_ALL                 ((1 << 13) - 1)
87 #define GQSPI_IXR_MASK          0xFBE
88 #define IXR_SELF_CLEAR \
89 (IXR_GENERIC_FIFO_EMPTY \
90 | IXR_GENERIC_FIFO_FULL  \
91 | IXR_GENERIC_FIFO_NOT_FULL \
92 | IXR_TX_FIFO_EMPTY \
93 | IXR_TX_FIFO_FULL  \
94 | IXR_TX_FIFO_NOT_FULL \
95 | IXR_RX_FIFO_EMPTY \
96 | IXR_RX_FIFO_FULL  \
97 | IXR_RX_FIFO_NOT_EMPTY)
98 
99 #define R_EN                (0x14 / 4)
100 #define R_DELAY             (0x18 / 4)
101 #define R_TX_DATA           (0x1C / 4)
102 #define R_RX_DATA           (0x20 / 4)
103 #define R_SLAVE_IDLE_COUNT  (0x24 / 4)
104 #define R_TX_THRES          (0x28 / 4)
105 #define R_RX_THRES          (0x2C / 4)
106 #define R_GPIO              (0x30 / 4)
107 #define R_LPBK_DLY_ADJ      (0x38 / 4)
108 #define R_LPBK_DLY_ADJ_RESET (0x33)
109 #define R_TXD1              (0x80 / 4)
110 #define R_TXD2              (0x84 / 4)
111 #define R_TXD3              (0x88 / 4)
112 
113 #define R_LQSPI_CFG         (0xa0 / 4)
114 #define R_LQSPI_CFG_RESET       0x03A002EB
115 #define LQSPI_CFG_LQ_MODE       (1U << 31)
116 #define LQSPI_CFG_TWO_MEM       (1 << 30)
117 #define LQSPI_CFG_SEP_BUS       (1 << 29)
118 #define LQSPI_CFG_U_PAGE        (1 << 28)
119 #define LQSPI_CFG_ADDR4         (1 << 27)
120 #define LQSPI_CFG_MODE_EN       (1 << 25)
121 #define LQSPI_CFG_MODE_WIDTH    8
122 #define LQSPI_CFG_MODE_SHIFT    16
123 #define LQSPI_CFG_DUMMY_WIDTH   3
124 #define LQSPI_CFG_DUMMY_SHIFT   8
125 #define LQSPI_CFG_INST_CODE     0xFF
126 
127 #define R_CMND        (0xc0 / 4)
128     #define R_CMND_RXFIFO_DRAIN   (1 << 19)
129     FIELD(CMND, PARTIAL_BYTE_LEN, 16, 3)
130 #define R_CMND_EXT_ADD        (1 << 15)
131     FIELD(CMND, RX_DISCARD, 8, 7)
132     FIELD(CMND, DUMMY_CYCLES, 2, 6)
133 #define R_CMND_DMA_EN         (1 << 1)
134 #define R_CMND_PUSH_WAIT      (1 << 0)
135 #define R_TRANSFER_SIZE     (0xc4 / 4)
136 #define R_LQSPI_STS         (0xA4 / 4)
137 #define LQSPI_STS_WR_RECVD      (1 << 1)
138 
139 #define R_MOD_ID            (0xFC / 4)
140 
141 #define R_GQSPI_SELECT          (0x144 / 4)
142     FIELD(GQSPI_SELECT, GENERIC_QSPI_EN, 0, 1)
143 #define R_GQSPI_ISR         (0x104 / 4)
144 #define R_GQSPI_IER         (0x108 / 4)
145 #define R_GQSPI_IDR         (0x10c / 4)
146 #define R_GQSPI_IMR         (0x110 / 4)
147 #define R_GQSPI_IMR_RESET   (0xfbe)
148 #define R_GQSPI_TX_THRESH   (0x128 / 4)
149 #define R_GQSPI_RX_THRESH   (0x12c / 4)
150 #define R_GQSPI_GPIO (0x130 / 4)
151 #define R_GQSPI_LPBK_DLY_ADJ (0x138 / 4)
152 #define R_GQSPI_LPBK_DLY_ADJ_RESET (0x33)
153 #define R_GQSPI_CNFG        (0x100 / 4)
154     FIELD(GQSPI_CNFG, MODE_EN, 30, 2)
155     FIELD(GQSPI_CNFG, GEN_FIFO_START_MODE, 29, 1)
156     FIELD(GQSPI_CNFG, GEN_FIFO_START, 28, 1)
157     FIELD(GQSPI_CNFG, ENDIAN, 26, 1)
158     /* Poll timeout not implemented */
159     FIELD(GQSPI_CNFG, EN_POLL_TIMEOUT, 20, 1)
160     /* QEMU doesnt care about any of these last three */
161     FIELD(GQSPI_CNFG, BR, 3, 3)
162     FIELD(GQSPI_CNFG, CPH, 2, 1)
163     FIELD(GQSPI_CNFG, CPL, 1, 1)
164 #define R_GQSPI_GEN_FIFO        (0x140 / 4)
165 #define R_GQSPI_TXD             (0x11c / 4)
166 #define R_GQSPI_RXD             (0x120 / 4)
167 #define R_GQSPI_FIFO_CTRL       (0x14c / 4)
168     FIELD(GQSPI_FIFO_CTRL, RX_FIFO_RESET, 2, 1)
169     FIELD(GQSPI_FIFO_CTRL, TX_FIFO_RESET, 1, 1)
170     FIELD(GQSPI_FIFO_CTRL, GENERIC_FIFO_RESET, 0, 1)
171 #define R_GQSPI_GFIFO_THRESH    (0x150 / 4)
172 #define R_GQSPI_DATA_STS (0x15c / 4)
173 /* We use the snapshot register to hold the core state for the currently
174  * or most recently executed command. So the generic fifo format is defined
175  * for the snapshot register
176  */
177 #define R_GQSPI_GF_SNAPSHOT (0x160 / 4)
178     FIELD(GQSPI_GF_SNAPSHOT, POLL, 19, 1)
179     FIELD(GQSPI_GF_SNAPSHOT, STRIPE, 18, 1)
180     FIELD(GQSPI_GF_SNAPSHOT, RECIEVE, 17, 1)
181     FIELD(GQSPI_GF_SNAPSHOT, TRANSMIT, 16, 1)
182     FIELD(GQSPI_GF_SNAPSHOT, DATA_BUS_SELECT, 14, 2)
183     FIELD(GQSPI_GF_SNAPSHOT, CHIP_SELECT, 12, 2)
184     FIELD(GQSPI_GF_SNAPSHOT, SPI_MODE, 10, 2)
185     FIELD(GQSPI_GF_SNAPSHOT, EXPONENT, 9, 1)
186     FIELD(GQSPI_GF_SNAPSHOT, DATA_XFER, 8, 1)
187     FIELD(GQSPI_GF_SNAPSHOT, IMMEDIATE_DATA, 0, 8)
188 #define R_GQSPI_MOD_ID        (0x1fc / 4)
189 #define R_GQSPI_MOD_ID_RESET  (0x10a0000)
190 
191 #define R_QSPIDMA_DST_CTRL         (0x80c / 4)
192 #define R_QSPIDMA_DST_CTRL_RESET   (0x803ffa00)
193 #define R_QSPIDMA_DST_I_MASK       (0x820 / 4)
194 #define R_QSPIDMA_DST_I_MASK_RESET (0xfe)
195 #define R_QSPIDMA_DST_CTRL2        (0x824 / 4)
196 #define R_QSPIDMA_DST_CTRL2_RESET  (0x081bfff8)
197 
198 /* size of TXRX FIFOs */
199 #define RXFF_A          (128)
200 #define TXFF_A          (128)
201 
202 #define RXFF_A_Q          (64 * 4)
203 #define TXFF_A_Q          (64 * 4)
204 
205 /* 16MB per linear region */
206 #define LQSPI_ADDRESS_BITS 24
207 
208 #define SNOOP_CHECKING 0xFF
209 #define SNOOP_ADDR 0xF0
210 #define SNOOP_NONE 0xEE
211 #define SNOOP_STRIPING 0
212 
213 #define MIN_NUM_BUSSES 1
214 #define MAX_NUM_BUSSES 2
215 
216 static inline int num_effective_busses(XilinxSPIPS *s)
217 {
218     return (s->regs[R_LQSPI_CFG] & LQSPI_CFG_SEP_BUS &&
219             s->regs[R_LQSPI_CFG] & LQSPI_CFG_TWO_MEM) ? s->num_busses : 1;
220 }
221 
222 static void xilinx_spips_update_cs(XilinxSPIPS *s, int field)
223 {
224     int i;
225 
226     for (i = 0; i < s->num_cs; i++) {
227         bool old_state = s->cs_lines_state[i];
228         bool new_state = field & (1 << i);
229 
230         if (old_state != new_state) {
231             s->cs_lines_state[i] = new_state;
232             s->rx_discard = ARRAY_FIELD_EX32(s->regs, CMND, RX_DISCARD);
233             DB_PRINT_L(1, "%sselecting slave %d\n", new_state ? "" : "de", i);
234         }
235         qemu_set_irq(s->cs_lines[i], !new_state);
236     }
237     if (!(field & ((1 << s->num_cs) - 1))) {
238         s->snoop_state = SNOOP_CHECKING;
239         s->cmd_dummies = 0;
240         s->link_state = 1;
241         s->link_state_next = 1;
242         s->link_state_next_when = 0;
243         DB_PRINT_L(1, "moving to snoop check state\n");
244     }
245 }
246 
247 static void xlnx_zynqmp_qspips_update_cs_lines(XlnxZynqMPQSPIPS *s)
248 {
249     if (s->regs[R_GQSPI_GF_SNAPSHOT]) {
250         int field = ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, CHIP_SELECT);
251         xilinx_spips_update_cs(XILINX_SPIPS(s), field);
252     }
253 }
254 
255 static void xilinx_spips_update_cs_lines(XilinxSPIPS *s)
256 {
257     int field = ~((s->regs[R_CONFIG] & CS) >> CS_SHIFT);
258 
259     /* In dual parallel, mirror low CS to both */
260     if (num_effective_busses(s) == 2) {
261         /* Single bit chip-select for qspi */
262         field &= 0x1;
263         field |= field << 1;
264     /* Dual stack U-Page */
265     } else if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_TWO_MEM &&
266                s->regs[R_LQSPI_STS] & LQSPI_CFG_U_PAGE) {
267         /* Single bit chip-select for qspi */
268         field &= 0x1;
269         /* change from CS0 to CS1 */
270         field <<= 1;
271     }
272     /* Auto CS */
273     if (!(s->regs[R_CONFIG] & MANUAL_CS) &&
274         fifo8_is_empty(&s->tx_fifo)) {
275         field = 0;
276     }
277     xilinx_spips_update_cs(s, field);
278 }
279 
280 static void xilinx_spips_update_ixr(XilinxSPIPS *s)
281 {
282     if (!(s->regs[R_LQSPI_CFG] & LQSPI_CFG_LQ_MODE)) {
283         s->regs[R_INTR_STATUS] &= ~IXR_SELF_CLEAR;
284         s->regs[R_INTR_STATUS] |=
285             (fifo8_is_full(&s->rx_fifo) ? IXR_RX_FIFO_FULL : 0) |
286             (s->rx_fifo.num >= s->regs[R_RX_THRES] ?
287                                     IXR_RX_FIFO_NOT_EMPTY : 0) |
288             (fifo8_is_full(&s->tx_fifo) ? IXR_TX_FIFO_FULL : 0) |
289             (fifo8_is_empty(&s->tx_fifo) ? IXR_TX_FIFO_EMPTY : 0) |
290             (s->tx_fifo.num < s->regs[R_TX_THRES] ? IXR_TX_FIFO_NOT_FULL : 0);
291     }
292     int new_irqline = !!(s->regs[R_INTR_MASK] & s->regs[R_INTR_STATUS] &
293                                                                 IXR_ALL);
294     if (new_irqline != s->irqline) {
295         s->irqline = new_irqline;
296         qemu_set_irq(s->irq, s->irqline);
297     }
298 }
299 
300 static void xlnx_zynqmp_qspips_update_ixr(XlnxZynqMPQSPIPS *s)
301 {
302     uint32_t gqspi_int;
303     int new_irqline;
304 
305     s->regs[R_GQSPI_ISR] &= ~IXR_SELF_CLEAR;
306     s->regs[R_GQSPI_ISR] |=
307         (fifo32_is_empty(&s->fifo_g) ? IXR_GENERIC_FIFO_EMPTY : 0) |
308         (fifo32_is_full(&s->fifo_g) ? IXR_GENERIC_FIFO_FULL : 0) |
309         (s->fifo_g.fifo.num < s->regs[R_GQSPI_GFIFO_THRESH] ?
310                                     IXR_GENERIC_FIFO_NOT_FULL : 0) |
311         (fifo8_is_empty(&s->rx_fifo_g) ? IXR_RX_FIFO_EMPTY : 0) |
312         (fifo8_is_full(&s->rx_fifo_g) ? IXR_RX_FIFO_FULL : 0) |
313         (s->rx_fifo_g.num >= s->regs[R_GQSPI_RX_THRESH] ?
314                                     IXR_RX_FIFO_NOT_EMPTY : 0) |
315         (fifo8_is_empty(&s->tx_fifo_g) ? IXR_TX_FIFO_EMPTY : 0) |
316         (fifo8_is_full(&s->tx_fifo_g) ? IXR_TX_FIFO_FULL : 0) |
317         (s->tx_fifo_g.num < s->regs[R_GQSPI_TX_THRESH] ?
318                                     IXR_TX_FIFO_NOT_FULL : 0);
319 
320     /* GQSPI Interrupt Trigger Status */
321     gqspi_int = (~s->regs[R_GQSPI_IMR]) & s->regs[R_GQSPI_ISR] & GQSPI_IXR_MASK;
322     new_irqline = !!(gqspi_int & IXR_ALL);
323 
324     /* drive external interrupt pin */
325     if (new_irqline != s->gqspi_irqline) {
326         s->gqspi_irqline = new_irqline;
327         qemu_set_irq(XILINX_SPIPS(s)->irq, s->gqspi_irqline);
328     }
329 }
330 
331 static void xilinx_spips_reset(DeviceState *d)
332 {
333     XilinxSPIPS *s = XILINX_SPIPS(d);
334 
335     memset(s->regs, 0, sizeof(s->regs));
336 
337     fifo8_reset(&s->rx_fifo);
338     fifo8_reset(&s->rx_fifo);
339     /* non zero resets */
340     s->regs[R_CONFIG] |= MODEFAIL_GEN_EN;
341     s->regs[R_SLAVE_IDLE_COUNT] = 0xFF;
342     s->regs[R_TX_THRES] = 1;
343     s->regs[R_RX_THRES] = 1;
344     /* FIXME: move magic number definition somewhere sensible */
345     s->regs[R_MOD_ID] = 0x01090106;
346     s->regs[R_LQSPI_CFG] = R_LQSPI_CFG_RESET;
347     s->link_state = 1;
348     s->link_state_next = 1;
349     s->link_state_next_when = 0;
350     s->snoop_state = SNOOP_CHECKING;
351     s->cmd_dummies = 0;
352     s->man_start_com = false;
353     xilinx_spips_update_ixr(s);
354     xilinx_spips_update_cs_lines(s);
355 }
356 
357 static void xlnx_zynqmp_qspips_reset(DeviceState *d)
358 {
359     XlnxZynqMPQSPIPS *s = XLNX_ZYNQMP_QSPIPS(d);
360 
361     xilinx_spips_reset(d);
362 
363     memset(s->regs, 0, sizeof(s->regs));
364 
365     fifo8_reset(&s->rx_fifo_g);
366     fifo8_reset(&s->rx_fifo_g);
367     fifo32_reset(&s->fifo_g);
368     s->regs[R_INTR_STATUS] = R_INTR_STATUS_RESET;
369     s->regs[R_GPIO] = 1;
370     s->regs[R_LPBK_DLY_ADJ] = R_LPBK_DLY_ADJ_RESET;
371     s->regs[R_GQSPI_GFIFO_THRESH] = 0x10;
372     s->regs[R_MOD_ID] = 0x01090101;
373     s->regs[R_GQSPI_IMR] = R_GQSPI_IMR_RESET;
374     s->regs[R_GQSPI_TX_THRESH] = 1;
375     s->regs[R_GQSPI_RX_THRESH] = 1;
376     s->regs[R_GQSPI_GPIO] = 1;
377     s->regs[R_GQSPI_LPBK_DLY_ADJ] = R_GQSPI_LPBK_DLY_ADJ_RESET;
378     s->regs[R_GQSPI_MOD_ID] = R_GQSPI_MOD_ID_RESET;
379     s->regs[R_QSPIDMA_DST_CTRL] = R_QSPIDMA_DST_CTRL_RESET;
380     s->regs[R_QSPIDMA_DST_I_MASK] = R_QSPIDMA_DST_I_MASK_RESET;
381     s->regs[R_QSPIDMA_DST_CTRL2] = R_QSPIDMA_DST_CTRL2_RESET;
382     s->man_start_com_g = false;
383     s->gqspi_irqline = 0;
384     xlnx_zynqmp_qspips_update_ixr(s);
385 }
386 
387 /* N way (num) in place bit striper. Lay out row wise bits (MSB to LSB)
388  * column wise (from element 0 to N-1). num is the length of x, and dir
389  * reverses the direction of the transform. Best illustrated by example:
390  * Each digit in the below array is a single bit (num == 3):
391  *
392  * {{ 76543210, }  ----- stripe (dir == false) -----> {{ 741gdaFC, }
393  *  { hgfedcba, }                                      { 630fcHEB, }
394  *  { HGFEDCBA, }} <---- upstripe (dir == true) -----  { 52hebGDA, }}
395  */
396 
397 static inline void stripe8(uint8_t *x, int num, bool dir)
398 {
399     uint8_t r[num];
400     memset(r, 0, sizeof(uint8_t) * num);
401     int idx[2] = {0, 0};
402     int bit[2] = {0, 7};
403     int d = dir;
404 
405     for (idx[0] = 0; idx[0] < num; ++idx[0]) {
406         for (bit[0] = 7; bit[0] >= 0; bit[0]--) {
407             r[idx[!d]] |= x[idx[d]] & 1 << bit[d] ? 1 << bit[!d] : 0;
408             idx[1] = (idx[1] + 1) % num;
409             if (!idx[1]) {
410                 bit[1]--;
411             }
412         }
413     }
414     memcpy(x, r, sizeof(uint8_t) * num);
415 }
416 
417 static void xlnx_zynqmp_qspips_flush_fifo_g(XlnxZynqMPQSPIPS *s)
418 {
419     while (s->regs[R_GQSPI_DATA_STS] || !fifo32_is_empty(&s->fifo_g)) {
420         uint8_t tx_rx[2] = { 0 };
421         int num_stripes = 1;
422         uint8_t busses;
423         int i;
424 
425         if (!s->regs[R_GQSPI_DATA_STS]) {
426             uint8_t imm;
427 
428             s->regs[R_GQSPI_GF_SNAPSHOT] = fifo32_pop(&s->fifo_g);
429             DB_PRINT_L(0, "GQSPI command: %x\n", s->regs[R_GQSPI_GF_SNAPSHOT]);
430             if (!s->regs[R_GQSPI_GF_SNAPSHOT]) {
431                 DB_PRINT_L(0, "Dummy GQSPI Delay Command Entry, Do nothing");
432                 continue;
433             }
434             xlnx_zynqmp_qspips_update_cs_lines(s);
435 
436             imm = ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, IMMEDIATE_DATA);
437             if (!ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, DATA_XFER)) {
438                 /* immedate transfer */
439                 if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, TRANSMIT) ||
440                     ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, RECIEVE)) {
441                     s->regs[R_GQSPI_DATA_STS] = 1;
442                 /* CS setup/hold - do nothing */
443                 } else {
444                     s->regs[R_GQSPI_DATA_STS] = 0;
445                 }
446             } else if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, EXPONENT)) {
447                 if (imm > 31) {
448                     qemu_log_mask(LOG_UNIMP, "QSPI exponential transfer too"
449                                   " long - 2 ^ %" PRId8 " requested\n", imm);
450                 }
451                 s->regs[R_GQSPI_DATA_STS] = 1ul << imm;
452             } else {
453                 s->regs[R_GQSPI_DATA_STS] = imm;
454             }
455         }
456         /* Zero length transfer check */
457         if (!s->regs[R_GQSPI_DATA_STS]) {
458             continue;
459         }
460         if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, RECIEVE) &&
461             fifo8_is_full(&s->rx_fifo_g)) {
462             /* No space in RX fifo for transfer - try again later */
463             return;
464         }
465         if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, STRIPE) &&
466             (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, TRANSMIT) ||
467              ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, RECIEVE))) {
468             num_stripes = 2;
469         }
470         if (!ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, DATA_XFER)) {
471             tx_rx[0] = ARRAY_FIELD_EX32(s->regs,
472                                         GQSPI_GF_SNAPSHOT, IMMEDIATE_DATA);
473         } else if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, TRANSMIT)) {
474             for (i = 0; i < num_stripes; ++i) {
475                 if (!fifo8_is_empty(&s->tx_fifo_g)) {
476                     tx_rx[i] = fifo8_pop(&s->tx_fifo_g);
477                     s->tx_fifo_g_align++;
478                 } else {
479                     return;
480                 }
481             }
482         }
483         if (num_stripes == 1) {
484             /* mirror */
485             tx_rx[1] = tx_rx[0];
486         }
487         busses = ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, DATA_BUS_SELECT);
488         for (i = 0; i < 2; ++i) {
489             DB_PRINT_L(1, "bus %d tx = %02x\n", i, tx_rx[i]);
490             tx_rx[i] = ssi_transfer(XILINX_SPIPS(s)->spi[i], tx_rx[i]);
491             DB_PRINT_L(1, "bus %d rx = %02x\n", i, tx_rx[i]);
492         }
493         if (s->regs[R_GQSPI_DATA_STS] > 1 &&
494             busses == 0x3 && num_stripes == 2) {
495             s->regs[R_GQSPI_DATA_STS] -= 2;
496         } else if (s->regs[R_GQSPI_DATA_STS] > 0) {
497             s->regs[R_GQSPI_DATA_STS]--;
498         }
499         if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, RECIEVE)) {
500             for (i = 0; i < 2; ++i) {
501                 if (busses & (1 << i)) {
502                     DB_PRINT_L(1, "bus %d push_byte = %02x\n", i, tx_rx[i]);
503                     fifo8_push(&s->rx_fifo_g, tx_rx[i]);
504                     s->rx_fifo_g_align++;
505                 }
506             }
507         }
508         if (!s->regs[R_GQSPI_DATA_STS]) {
509             for (; s->tx_fifo_g_align % 4; s->tx_fifo_g_align++) {
510                 fifo8_pop(&s->tx_fifo_g);
511             }
512             for (; s->rx_fifo_g_align % 4; s->rx_fifo_g_align++) {
513                 fifo8_push(&s->rx_fifo_g, 0);
514             }
515         }
516     }
517 }
518 
519 static int xilinx_spips_num_dummies(XilinxQSPIPS *qs, uint8_t command)
520 {
521     if (!qs) {
522         /* The SPI device is not a QSPI device */
523         return -1;
524     }
525 
526     switch (command) { /* check for dummies */
527     case READ: /* no dummy bytes/cycles */
528     case PP:
529     case DPP:
530     case QPP:
531     case READ_4:
532     case PP_4:
533     case QPP_4:
534         return 0;
535     case FAST_READ:
536     case DOR:
537     case QOR:
538     case DOR_4:
539     case QOR_4:
540         return 1;
541     case DIOR:
542     case FAST_READ_4:
543     case DIOR_4:
544         return 2;
545     case QIOR:
546     case QIOR_4:
547         return 5;
548     default:
549         return -1;
550     }
551 }
552 
553 static inline uint8_t get_addr_length(XilinxSPIPS *s, uint8_t cmd)
554 {
555    switch (cmd) {
556    case PP_4:
557    case QPP_4:
558    case READ_4:
559    case QIOR_4:
560    case FAST_READ_4:
561    case DOR_4:
562    case QOR_4:
563    case DIOR_4:
564        return 4;
565    default:
566        return (s->regs[R_CMND] & R_CMND_EXT_ADD) ? 4 : 3;
567    }
568 }
569 
570 static void xilinx_spips_flush_txfifo(XilinxSPIPS *s)
571 {
572     int debug_level = 0;
573     XilinxQSPIPS *q = (XilinxQSPIPS *) object_dynamic_cast(OBJECT(s),
574                                                            TYPE_XILINX_QSPIPS);
575 
576     for (;;) {
577         int i;
578         uint8_t tx = 0;
579         uint8_t tx_rx[MAX_NUM_BUSSES] = { 0 };
580         uint8_t dummy_cycles = 0;
581         uint8_t addr_length;
582 
583         if (fifo8_is_empty(&s->tx_fifo)) {
584             xilinx_spips_update_ixr(s);
585             return;
586         } else if (s->snoop_state == SNOOP_STRIPING) {
587             for (i = 0; i < num_effective_busses(s); ++i) {
588                 tx_rx[i] = fifo8_pop(&s->tx_fifo);
589             }
590             stripe8(tx_rx, num_effective_busses(s), false);
591         } else if (s->snoop_state >= SNOOP_ADDR) {
592             tx = fifo8_pop(&s->tx_fifo);
593             for (i = 0; i < num_effective_busses(s); ++i) {
594                 tx_rx[i] = tx;
595             }
596         } else {
597             /* Extract a dummy byte and generate dummy cycles according to the
598              * link state */
599             tx = fifo8_pop(&s->tx_fifo);
600             dummy_cycles = 8 / s->link_state;
601         }
602 
603         for (i = 0; i < num_effective_busses(s); ++i) {
604             int bus = num_effective_busses(s) - 1 - i;
605             if (dummy_cycles) {
606                 int d;
607                 for (d = 0; d < dummy_cycles; ++d) {
608                     tx_rx[0] = ssi_transfer(s->spi[bus], (uint32_t)tx_rx[0]);
609                 }
610             } else {
611                 DB_PRINT_L(debug_level, "tx = %02x\n", tx_rx[i]);
612                 tx_rx[i] = ssi_transfer(s->spi[bus], (uint32_t)tx_rx[i]);
613                 DB_PRINT_L(debug_level, "rx = %02x\n", tx_rx[i]);
614             }
615         }
616 
617         if (s->regs[R_CMND] & R_CMND_RXFIFO_DRAIN) {
618             DB_PRINT_L(debug_level, "dircarding drained rx byte\n");
619             /* Do nothing */
620         } else if (s->rx_discard) {
621             DB_PRINT_L(debug_level, "dircarding discarded rx byte\n");
622             s->rx_discard -= 8 / s->link_state;
623         } else if (fifo8_is_full(&s->rx_fifo)) {
624             s->regs[R_INTR_STATUS] |= IXR_RX_FIFO_OVERFLOW;
625             DB_PRINT_L(0, "rx FIFO overflow");
626         } else if (s->snoop_state == SNOOP_STRIPING) {
627             stripe8(tx_rx, num_effective_busses(s), true);
628             for (i = 0; i < num_effective_busses(s); ++i) {
629                 fifo8_push(&s->rx_fifo, (uint8_t)tx_rx[i]);
630                 DB_PRINT_L(debug_level, "pushing striped rx byte\n");
631             }
632         } else {
633            DB_PRINT_L(debug_level, "pushing unstriped rx byte\n");
634            fifo8_push(&s->rx_fifo, (uint8_t)tx_rx[0]);
635         }
636 
637         if (s->link_state_next_when) {
638             s->link_state_next_when--;
639             if (!s->link_state_next_when) {
640                 s->link_state = s->link_state_next;
641             }
642         }
643 
644         DB_PRINT_L(debug_level, "initial snoop state: %x\n",
645                    (unsigned)s->snoop_state);
646         switch (s->snoop_state) {
647         case (SNOOP_CHECKING):
648             /* Store the count of dummy bytes in the txfifo */
649             s->cmd_dummies = xilinx_spips_num_dummies(q, tx);
650             addr_length = get_addr_length(s, tx);
651             if (s->cmd_dummies < 0) {
652                 s->snoop_state = SNOOP_NONE;
653             } else {
654                 s->snoop_state = SNOOP_ADDR + addr_length - 1;
655             }
656             switch (tx) {
657             case DPP:
658             case DOR:
659             case DOR_4:
660                 s->link_state_next = 2;
661                 s->link_state_next_when = addr_length + s->cmd_dummies;
662                 break;
663             case QPP:
664             case QPP_4:
665             case QOR:
666             case QOR_4:
667                 s->link_state_next = 4;
668                 s->link_state_next_when = addr_length + s->cmd_dummies;
669                 break;
670             case DIOR:
671             case DIOR_4:
672                 s->link_state = 2;
673                 break;
674             case QIOR:
675             case QIOR_4:
676                 s->link_state = 4;
677                 break;
678             }
679             break;
680         case (SNOOP_ADDR):
681             /* Address has been transmitted, transmit dummy cycles now if
682              * needed */
683             if (s->cmd_dummies < 0) {
684                 s->snoop_state = SNOOP_NONE;
685             } else {
686                 s->snoop_state = s->cmd_dummies;
687             }
688             break;
689         case (SNOOP_STRIPING):
690         case (SNOOP_NONE):
691             /* Once we hit the boring stuff - squelch debug noise */
692             if (!debug_level) {
693                 DB_PRINT_L(0, "squelching debug info ....\n");
694                 debug_level = 1;
695             }
696             break;
697         default:
698             s->snoop_state--;
699         }
700         DB_PRINT_L(debug_level, "final snoop state: %x\n",
701                    (unsigned)s->snoop_state);
702     }
703 }
704 
705 static inline void tx_data_bytes(Fifo8 *fifo, uint32_t value, int num, bool be)
706 {
707     int i;
708     for (i = 0; i < num && !fifo8_is_full(fifo); ++i) {
709         if (be) {
710             fifo8_push(fifo, (uint8_t)(value >> 24));
711             value <<= 8;
712         } else {
713             fifo8_push(fifo, (uint8_t)value);
714             value >>= 8;
715         }
716     }
717 }
718 
719 static void xilinx_spips_check_zero_pump(XilinxSPIPS *s)
720 {
721     if (!s->regs[R_TRANSFER_SIZE]) {
722         return;
723     }
724     if (!fifo8_is_empty(&s->tx_fifo) && s->regs[R_CMND] & R_CMND_PUSH_WAIT) {
725         return;
726     }
727     /*
728      * The zero pump must never fill tx fifo such that rx overflow is
729      * possible
730      */
731     while (s->regs[R_TRANSFER_SIZE] &&
732            s->rx_fifo.num + s->tx_fifo.num < RXFF_A_Q - 3) {
733         /* endianess just doesn't matter when zero pumping */
734         tx_data_bytes(&s->tx_fifo, 0, 4, false);
735         s->regs[R_TRANSFER_SIZE] &= ~0x03ull;
736         s->regs[R_TRANSFER_SIZE] -= 4;
737     }
738 }
739 
740 static void xilinx_spips_check_flush(XilinxSPIPS *s)
741 {
742     if (s->man_start_com ||
743         (!fifo8_is_empty(&s->tx_fifo) &&
744          !(s->regs[R_CONFIG] & MAN_START_EN))) {
745         xilinx_spips_check_zero_pump(s);
746         xilinx_spips_flush_txfifo(s);
747     }
748     if (fifo8_is_empty(&s->tx_fifo) && !s->regs[R_TRANSFER_SIZE]) {
749         s->man_start_com = false;
750     }
751     xilinx_spips_update_ixr(s);
752 }
753 
754 static void xlnx_zynqmp_qspips_check_flush(XlnxZynqMPQSPIPS *s)
755 {
756     bool gqspi_has_work = s->regs[R_GQSPI_DATA_STS] ||
757                           !fifo32_is_empty(&s->fifo_g);
758 
759     if (ARRAY_FIELD_EX32(s->regs, GQSPI_SELECT, GENERIC_QSPI_EN)) {
760         if (s->man_start_com_g || (gqspi_has_work &&
761              !ARRAY_FIELD_EX32(s->regs, GQSPI_CNFG, GEN_FIFO_START_MODE))) {
762             xlnx_zynqmp_qspips_flush_fifo_g(s);
763         }
764     } else {
765         xilinx_spips_check_flush(XILINX_SPIPS(s));
766     }
767     if (!gqspi_has_work) {
768         s->man_start_com_g = false;
769     }
770     xlnx_zynqmp_qspips_update_ixr(s);
771 }
772 
773 static inline int rx_data_bytes(Fifo8 *fifo, uint8_t *value, int max)
774 {
775     int i;
776 
777     for (i = 0; i < max && !fifo8_is_empty(fifo); ++i) {
778         value[i] = fifo8_pop(fifo);
779     }
780     return max - i;
781 }
782 
783 static const void *pop_buf(Fifo8 *fifo, uint32_t max, uint32_t *num)
784 {
785     void *ret;
786 
787     if (max == 0 || max > fifo->num) {
788         abort();
789     }
790     *num = MIN(fifo->capacity - fifo->head, max);
791     ret = &fifo->data[fifo->head];
792     fifo->head += *num;
793     fifo->head %= fifo->capacity;
794     fifo->num -= *num;
795     return ret;
796 }
797 
798 static void xlnx_zynqmp_qspips_notify(void *opaque)
799 {
800     XlnxZynqMPQSPIPS *rq = XLNX_ZYNQMP_QSPIPS(opaque);
801     XilinxSPIPS *s = XILINX_SPIPS(rq);
802     Fifo8 *recv_fifo;
803 
804     if (ARRAY_FIELD_EX32(rq->regs, GQSPI_SELECT, GENERIC_QSPI_EN)) {
805         if (!(ARRAY_FIELD_EX32(rq->regs, GQSPI_CNFG, MODE_EN) == 2)) {
806             return;
807         }
808         recv_fifo = &rq->rx_fifo_g;
809     } else {
810         if (!(s->regs[R_CMND] & R_CMND_DMA_EN)) {
811             return;
812         }
813         recv_fifo = &s->rx_fifo;
814     }
815     while (recv_fifo->num >= 4
816            && stream_can_push(rq->dma, xlnx_zynqmp_qspips_notify, rq))
817     {
818         size_t ret;
819         uint32_t num;
820         const void *rxd = pop_buf(recv_fifo, 4, &num);
821 
822         memcpy(rq->dma_buf, rxd, num);
823 
824         ret = stream_push(rq->dma, rq->dma_buf, 4);
825         assert(ret == 4);
826         xlnx_zynqmp_qspips_check_flush(rq);
827     }
828 }
829 
830 static uint64_t xilinx_spips_read(void *opaque, hwaddr addr,
831                                                         unsigned size)
832 {
833     XilinxSPIPS *s = opaque;
834     uint32_t mask = ~0;
835     uint32_t ret;
836     uint8_t rx_buf[4];
837     int shortfall;
838 
839     addr >>= 2;
840     switch (addr) {
841     case R_CONFIG:
842         mask = ~(R_CONFIG_RSVD | MAN_START_COM);
843         break;
844     case R_INTR_STATUS:
845         ret = s->regs[addr] & IXR_ALL;
846         s->regs[addr] = 0;
847         DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret);
848         xilinx_spips_update_ixr(s);
849         return ret;
850     case R_INTR_MASK:
851         mask = IXR_ALL;
852         break;
853     case  R_EN:
854         mask = 0x1;
855         break;
856     case R_SLAVE_IDLE_COUNT:
857         mask = 0xFF;
858         break;
859     case R_MOD_ID:
860         mask = 0x01FFFFFF;
861         break;
862     case R_INTR_EN:
863     case R_INTR_DIS:
864     case R_TX_DATA:
865         mask = 0;
866         break;
867     case R_RX_DATA:
868         memset(rx_buf, 0, sizeof(rx_buf));
869         shortfall = rx_data_bytes(&s->rx_fifo, rx_buf, s->num_txrx_bytes);
870         ret = s->regs[R_CONFIG] & R_CONFIG_ENDIAN ?
871                         cpu_to_be32(*(uint32_t *)rx_buf) :
872                         cpu_to_le32(*(uint32_t *)rx_buf);
873         if (!(s->regs[R_CONFIG] & R_CONFIG_ENDIAN)) {
874             ret <<= 8 * shortfall;
875         }
876         DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret);
877         xilinx_spips_check_flush(s);
878         xilinx_spips_update_ixr(s);
879         return ret;
880     }
881     DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4,
882                s->regs[addr] & mask);
883     return s->regs[addr] & mask;
884 
885 }
886 
887 static uint64_t xlnx_zynqmp_qspips_read(void *opaque,
888                                         hwaddr addr, unsigned size)
889 {
890     XlnxZynqMPQSPIPS *s = XLNX_ZYNQMP_QSPIPS(opaque);
891     uint32_t reg = addr / 4;
892     uint32_t ret;
893     uint8_t rx_buf[4];
894     int shortfall;
895 
896     if (reg <= R_MOD_ID) {
897         return xilinx_spips_read(opaque, addr, size);
898     } else {
899         switch (reg) {
900         case R_GQSPI_RXD:
901             if (fifo8_is_empty(&s->rx_fifo_g)) {
902                 qemu_log_mask(LOG_GUEST_ERROR,
903                               "Read from empty GQSPI RX FIFO\n");
904                 return 0;
905             }
906             memset(rx_buf, 0, sizeof(rx_buf));
907             shortfall = rx_data_bytes(&s->rx_fifo_g, rx_buf,
908                                       XILINX_SPIPS(s)->num_txrx_bytes);
909             ret = ARRAY_FIELD_EX32(s->regs, GQSPI_CNFG, ENDIAN) ?
910                   cpu_to_be32(*(uint32_t *)rx_buf) :
911                   cpu_to_le32(*(uint32_t *)rx_buf);
912             if (!ARRAY_FIELD_EX32(s->regs, GQSPI_CNFG, ENDIAN)) {
913                 ret <<= 8 * shortfall;
914             }
915             xlnx_zynqmp_qspips_check_flush(s);
916             xlnx_zynqmp_qspips_update_ixr(s);
917             return ret;
918         default:
919             return s->regs[reg];
920         }
921     }
922 }
923 
924 static void xilinx_spips_write(void *opaque, hwaddr addr,
925                                         uint64_t value, unsigned size)
926 {
927     int mask = ~0;
928     XilinxSPIPS *s = opaque;
929 
930     DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr, (unsigned)value);
931     addr >>= 2;
932     switch (addr) {
933     case R_CONFIG:
934         mask = ~(R_CONFIG_RSVD | MAN_START_COM);
935         if ((value & MAN_START_COM) && (s->regs[R_CONFIG] & MAN_START_EN)) {
936             s->man_start_com = true;
937         }
938         break;
939     case R_INTR_STATUS:
940         mask = IXR_ALL;
941         s->regs[R_INTR_STATUS] &= ~(mask & value);
942         goto no_reg_update;
943     case R_INTR_DIS:
944         mask = IXR_ALL;
945         s->regs[R_INTR_MASK] &= ~(mask & value);
946         goto no_reg_update;
947     case R_INTR_EN:
948         mask = IXR_ALL;
949         s->regs[R_INTR_MASK] |= mask & value;
950         goto no_reg_update;
951     case R_EN:
952         mask = 0x1;
953         break;
954     case R_SLAVE_IDLE_COUNT:
955         mask = 0xFF;
956         break;
957     case R_RX_DATA:
958     case R_INTR_MASK:
959     case R_MOD_ID:
960         mask = 0;
961         break;
962     case R_TX_DATA:
963         tx_data_bytes(&s->tx_fifo, (uint32_t)value, s->num_txrx_bytes,
964                       s->regs[R_CONFIG] & R_CONFIG_ENDIAN);
965         goto no_reg_update;
966     case R_TXD1:
967         tx_data_bytes(&s->tx_fifo, (uint32_t)value, 1,
968                       s->regs[R_CONFIG] & R_CONFIG_ENDIAN);
969         goto no_reg_update;
970     case R_TXD2:
971         tx_data_bytes(&s->tx_fifo, (uint32_t)value, 2,
972                       s->regs[R_CONFIG] & R_CONFIG_ENDIAN);
973         goto no_reg_update;
974     case R_TXD3:
975         tx_data_bytes(&s->tx_fifo, (uint32_t)value, 3,
976                       s->regs[R_CONFIG] & R_CONFIG_ENDIAN);
977         goto no_reg_update;
978     }
979     s->regs[addr] = (s->regs[addr] & ~mask) | (value & mask);
980 no_reg_update:
981     xilinx_spips_update_cs_lines(s);
982     xilinx_spips_check_flush(s);
983     xilinx_spips_update_cs_lines(s);
984     xilinx_spips_update_ixr(s);
985 }
986 
987 static const MemoryRegionOps spips_ops = {
988     .read = xilinx_spips_read,
989     .write = xilinx_spips_write,
990     .endianness = DEVICE_LITTLE_ENDIAN,
991 };
992 
993 static void xilinx_qspips_invalidate_mmio_ptr(XilinxQSPIPS *q)
994 {
995     XilinxSPIPS *s = &q->parent_obj;
996 
997     if ((q->mmio_execution_enabled) && (q->lqspi_cached_addr != ~0ULL)) {
998         /* Invalidate the current mapped mmio */
999         memory_region_invalidate_mmio_ptr(&s->mmlqspi, q->lqspi_cached_addr,
1000                                           LQSPI_CACHE_SIZE);
1001     }
1002 
1003     q->lqspi_cached_addr = ~0ULL;
1004 }
1005 
1006 static void xilinx_qspips_write(void *opaque, hwaddr addr,
1007                                 uint64_t value, unsigned size)
1008 {
1009     XilinxQSPIPS *q = XILINX_QSPIPS(opaque);
1010     XilinxSPIPS *s = XILINX_SPIPS(opaque);
1011 
1012     xilinx_spips_write(opaque, addr, value, size);
1013     addr >>= 2;
1014 
1015     if (addr == R_LQSPI_CFG) {
1016         xilinx_qspips_invalidate_mmio_ptr(q);
1017     }
1018     if (s->regs[R_CMND] & R_CMND_RXFIFO_DRAIN) {
1019         fifo8_reset(&s->rx_fifo);
1020     }
1021 }
1022 
1023 static void xlnx_zynqmp_qspips_write(void *opaque, hwaddr addr,
1024                                         uint64_t value, unsigned size)
1025 {
1026     XlnxZynqMPQSPIPS *s = XLNX_ZYNQMP_QSPIPS(opaque);
1027     uint32_t reg = addr / 4;
1028 
1029     if (reg <= R_MOD_ID) {
1030         xilinx_qspips_write(opaque, addr, value, size);
1031     } else {
1032         switch (reg) {
1033         case R_GQSPI_CNFG:
1034             if (FIELD_EX32(value, GQSPI_CNFG, GEN_FIFO_START) &&
1035                 ARRAY_FIELD_EX32(s->regs, GQSPI_CNFG, GEN_FIFO_START_MODE)) {
1036                 s->man_start_com_g = true;
1037             }
1038             s->regs[reg] = value & ~(R_GQSPI_CNFG_GEN_FIFO_START_MASK);
1039             break;
1040         case R_GQSPI_GEN_FIFO:
1041             if (!fifo32_is_full(&s->fifo_g)) {
1042                 fifo32_push(&s->fifo_g, value);
1043             }
1044             break;
1045         case R_GQSPI_TXD:
1046             tx_data_bytes(&s->tx_fifo_g, (uint32_t)value, 4,
1047                           ARRAY_FIELD_EX32(s->regs, GQSPI_CNFG, ENDIAN));
1048             break;
1049         case R_GQSPI_FIFO_CTRL:
1050             if (FIELD_EX32(value, GQSPI_FIFO_CTRL, GENERIC_FIFO_RESET)) {
1051                 fifo32_reset(&s->fifo_g);
1052             }
1053             if (FIELD_EX32(value, GQSPI_FIFO_CTRL, TX_FIFO_RESET)) {
1054                 fifo8_reset(&s->tx_fifo_g);
1055             }
1056             if (FIELD_EX32(value, GQSPI_FIFO_CTRL, RX_FIFO_RESET)) {
1057                 fifo8_reset(&s->rx_fifo_g);
1058             }
1059             break;
1060         case R_GQSPI_IDR:
1061             s->regs[R_GQSPI_IMR] |= value;
1062             break;
1063         case R_GQSPI_IER:
1064             s->regs[R_GQSPI_IMR] &= ~value;
1065             break;
1066         case R_GQSPI_ISR:
1067             s->regs[R_GQSPI_ISR] &= ~value;
1068             break;
1069         case R_GQSPI_IMR:
1070         case R_GQSPI_RXD:
1071         case R_GQSPI_GF_SNAPSHOT:
1072         case R_GQSPI_MOD_ID:
1073             break;
1074         default:
1075             s->regs[reg] = value;
1076             break;
1077         }
1078         xlnx_zynqmp_qspips_update_cs_lines(s);
1079         xlnx_zynqmp_qspips_check_flush(s);
1080         xlnx_zynqmp_qspips_update_cs_lines(s);
1081         xlnx_zynqmp_qspips_update_ixr(s);
1082     }
1083     xlnx_zynqmp_qspips_notify(s);
1084 }
1085 
1086 static const MemoryRegionOps qspips_ops = {
1087     .read = xilinx_spips_read,
1088     .write = xilinx_qspips_write,
1089     .endianness = DEVICE_LITTLE_ENDIAN,
1090 };
1091 
1092 static const MemoryRegionOps xlnx_zynqmp_qspips_ops = {
1093     .read = xlnx_zynqmp_qspips_read,
1094     .write = xlnx_zynqmp_qspips_write,
1095     .endianness = DEVICE_LITTLE_ENDIAN,
1096 };
1097 
1098 #define LQSPI_CACHE_SIZE 1024
1099 
1100 static void lqspi_load_cache(void *opaque, hwaddr addr)
1101 {
1102     XilinxQSPIPS *q = opaque;
1103     XilinxSPIPS *s = opaque;
1104     int i;
1105     int flash_addr = ((addr & ~(LQSPI_CACHE_SIZE - 1))
1106                    / num_effective_busses(s));
1107     int slave = flash_addr >> LQSPI_ADDRESS_BITS;
1108     int cache_entry = 0;
1109     uint32_t u_page_save = s->regs[R_LQSPI_STS] & ~LQSPI_CFG_U_PAGE;
1110 
1111     if (addr < q->lqspi_cached_addr ||
1112             addr > q->lqspi_cached_addr + LQSPI_CACHE_SIZE - 4) {
1113         xilinx_qspips_invalidate_mmio_ptr(q);
1114         s->regs[R_LQSPI_STS] &= ~LQSPI_CFG_U_PAGE;
1115         s->regs[R_LQSPI_STS] |= slave ? LQSPI_CFG_U_PAGE : 0;
1116 
1117         DB_PRINT_L(0, "config reg status: %08x\n", s->regs[R_LQSPI_CFG]);
1118 
1119         fifo8_reset(&s->tx_fifo);
1120         fifo8_reset(&s->rx_fifo);
1121 
1122         /* instruction */
1123         DB_PRINT_L(0, "pushing read instruction: %02x\n",
1124                    (unsigned)(uint8_t)(s->regs[R_LQSPI_CFG] &
1125                                        LQSPI_CFG_INST_CODE));
1126         fifo8_push(&s->tx_fifo, s->regs[R_LQSPI_CFG] & LQSPI_CFG_INST_CODE);
1127         /* read address */
1128         DB_PRINT_L(0, "pushing read address %06x\n", flash_addr);
1129         if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_ADDR4) {
1130             fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 24));
1131         }
1132         fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 16));
1133         fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 8));
1134         fifo8_push(&s->tx_fifo, (uint8_t)flash_addr);
1135         /* mode bits */
1136         if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_MODE_EN) {
1137             fifo8_push(&s->tx_fifo, extract32(s->regs[R_LQSPI_CFG],
1138                                               LQSPI_CFG_MODE_SHIFT,
1139                                               LQSPI_CFG_MODE_WIDTH));
1140         }
1141         /* dummy bytes */
1142         for (i = 0; i < (extract32(s->regs[R_LQSPI_CFG], LQSPI_CFG_DUMMY_SHIFT,
1143                                    LQSPI_CFG_DUMMY_WIDTH)); ++i) {
1144             DB_PRINT_L(0, "pushing dummy byte\n");
1145             fifo8_push(&s->tx_fifo, 0);
1146         }
1147         xilinx_spips_update_cs_lines(s);
1148         xilinx_spips_flush_txfifo(s);
1149         fifo8_reset(&s->rx_fifo);
1150 
1151         DB_PRINT_L(0, "starting QSPI data read\n");
1152 
1153         while (cache_entry < LQSPI_CACHE_SIZE) {
1154             for (i = 0; i < 64; ++i) {
1155                 tx_data_bytes(&s->tx_fifo, 0, 1, false);
1156             }
1157             xilinx_spips_flush_txfifo(s);
1158             for (i = 0; i < 64; ++i) {
1159                 rx_data_bytes(&s->rx_fifo, &q->lqspi_buf[cache_entry++], 1);
1160             }
1161         }
1162 
1163         s->regs[R_LQSPI_STS] &= ~LQSPI_CFG_U_PAGE;
1164         s->regs[R_LQSPI_STS] |= u_page_save;
1165         xilinx_spips_update_cs_lines(s);
1166 
1167         q->lqspi_cached_addr = flash_addr * num_effective_busses(s);
1168     }
1169 }
1170 
1171 static void *lqspi_request_mmio_ptr(void *opaque, hwaddr addr, unsigned *size,
1172                                     unsigned *offset)
1173 {
1174     XilinxQSPIPS *q = opaque;
1175     hwaddr offset_within_the_region;
1176 
1177     if (!q->mmio_execution_enabled) {
1178         return NULL;
1179     }
1180 
1181     offset_within_the_region = addr & ~(LQSPI_CACHE_SIZE - 1);
1182     lqspi_load_cache(opaque, offset_within_the_region);
1183     *size = LQSPI_CACHE_SIZE;
1184     *offset = offset_within_the_region;
1185     return q->lqspi_buf;
1186 }
1187 
1188 static uint64_t
1189 lqspi_read(void *opaque, hwaddr addr, unsigned int size)
1190 {
1191     XilinxQSPIPS *q = opaque;
1192     uint32_t ret;
1193 
1194     if (addr >= q->lqspi_cached_addr &&
1195             addr <= q->lqspi_cached_addr + LQSPI_CACHE_SIZE - 4) {
1196         uint8_t *retp = &q->lqspi_buf[addr - q->lqspi_cached_addr];
1197         ret = cpu_to_le32(*(uint32_t *)retp);
1198         DB_PRINT_L(1, "addr: %08x, data: %08x\n", (unsigned)addr,
1199                    (unsigned)ret);
1200         return ret;
1201     } else {
1202         lqspi_load_cache(opaque, addr);
1203         return lqspi_read(opaque, addr, size);
1204     }
1205 }
1206 
1207 static const MemoryRegionOps lqspi_ops = {
1208     .read = lqspi_read,
1209     .request_ptr = lqspi_request_mmio_ptr,
1210     .endianness = DEVICE_NATIVE_ENDIAN,
1211     .valid = {
1212         .min_access_size = 1,
1213         .max_access_size = 4
1214     }
1215 };
1216 
1217 static void xilinx_spips_realize(DeviceState *dev, Error **errp)
1218 {
1219     XilinxSPIPS *s = XILINX_SPIPS(dev);
1220     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
1221     XilinxSPIPSClass *xsc = XILINX_SPIPS_GET_CLASS(s);
1222     qemu_irq *cs;
1223     int i;
1224 
1225     DB_PRINT_L(0, "realized spips\n");
1226 
1227     if (s->num_busses > MAX_NUM_BUSSES) {
1228         error_setg(errp,
1229                    "requested number of SPI busses %u exceeds maximum %d",
1230                    s->num_busses, MAX_NUM_BUSSES);
1231         return;
1232     }
1233     if (s->num_busses < MIN_NUM_BUSSES) {
1234         error_setg(errp,
1235                    "requested number of SPI busses %u is below minimum %d",
1236                    s->num_busses, MIN_NUM_BUSSES);
1237         return;
1238     }
1239 
1240     s->spi = g_new(SSIBus *, s->num_busses);
1241     for (i = 0; i < s->num_busses; ++i) {
1242         char bus_name[16];
1243         snprintf(bus_name, 16, "spi%d", i);
1244         s->spi[i] = ssi_create_bus(dev, bus_name);
1245     }
1246 
1247     s->cs_lines = g_new0(qemu_irq, s->num_cs * s->num_busses);
1248     s->cs_lines_state = g_new0(bool, s->num_cs * s->num_busses);
1249     for (i = 0, cs = s->cs_lines; i < s->num_busses; ++i, cs += s->num_cs) {
1250         ssi_auto_connect_slaves(DEVICE(s), cs, s->spi[i]);
1251     }
1252 
1253     sysbus_init_irq(sbd, &s->irq);
1254     for (i = 0; i < s->num_cs * s->num_busses; ++i) {
1255         sysbus_init_irq(sbd, &s->cs_lines[i]);
1256     }
1257 
1258     memory_region_init_io(&s->iomem, OBJECT(s), xsc->reg_ops, s,
1259                           "spi", XLNX_ZYNQMP_SPIPS_R_MAX * 4);
1260     sysbus_init_mmio(sbd, &s->iomem);
1261 
1262     s->irqline = -1;
1263 
1264     fifo8_create(&s->rx_fifo, xsc->rx_fifo_size);
1265     fifo8_create(&s->tx_fifo, xsc->tx_fifo_size);
1266 }
1267 
1268 static void xilinx_qspips_realize(DeviceState *dev, Error **errp)
1269 {
1270     XilinxSPIPS *s = XILINX_SPIPS(dev);
1271     XilinxQSPIPS *q = XILINX_QSPIPS(dev);
1272     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
1273 
1274     DB_PRINT_L(0, "realized qspips\n");
1275 
1276     s->num_busses = 2;
1277     s->num_cs = 2;
1278     s->num_txrx_bytes = 4;
1279 
1280     xilinx_spips_realize(dev, errp);
1281     memory_region_init_io(&s->mmlqspi, OBJECT(s), &lqspi_ops, s, "lqspi",
1282                           (1 << LQSPI_ADDRESS_BITS) * 2);
1283     sysbus_init_mmio(sbd, &s->mmlqspi);
1284 
1285     q->lqspi_cached_addr = ~0ULL;
1286 
1287     /* mmio_execution breaks migration better aborting than having strange
1288      * bugs.
1289      */
1290     if (q->mmio_execution_enabled) {
1291         error_setg(&q->migration_blocker,
1292                    "enabling mmio_execution breaks migration");
1293         migrate_add_blocker(q->migration_blocker, &error_fatal);
1294     }
1295 }
1296 
1297 static void xlnx_zynqmp_qspips_realize(DeviceState *dev, Error **errp)
1298 {
1299     XlnxZynqMPQSPIPS *s = XLNX_ZYNQMP_QSPIPS(dev);
1300     XilinxSPIPSClass *xsc = XILINX_SPIPS_GET_CLASS(s);
1301 
1302     xilinx_qspips_realize(dev, errp);
1303     fifo8_create(&s->rx_fifo_g, xsc->rx_fifo_size);
1304     fifo8_create(&s->tx_fifo_g, xsc->tx_fifo_size);
1305     fifo32_create(&s->fifo_g, 32);
1306 }
1307 
1308 static void xlnx_zynqmp_qspips_init(Object *obj)
1309 {
1310     XlnxZynqMPQSPIPS *rq = XLNX_ZYNQMP_QSPIPS(obj);
1311 
1312     object_property_add_link(obj, "stream-connected-dma", TYPE_STREAM_SLAVE,
1313                              (Object **)&rq->dma,
1314                              object_property_allow_set_link,
1315                              OBJ_PROP_LINK_UNREF_ON_RELEASE,
1316                              NULL);
1317 }
1318 
1319 static int xilinx_spips_post_load(void *opaque, int version_id)
1320 {
1321     xilinx_spips_update_ixr((XilinxSPIPS *)opaque);
1322     xilinx_spips_update_cs_lines((XilinxSPIPS *)opaque);
1323     return 0;
1324 }
1325 
1326 static const VMStateDescription vmstate_xilinx_spips = {
1327     .name = "xilinx_spips",
1328     .version_id = 2,
1329     .minimum_version_id = 2,
1330     .post_load = xilinx_spips_post_load,
1331     .fields = (VMStateField[]) {
1332         VMSTATE_FIFO8(tx_fifo, XilinxSPIPS),
1333         VMSTATE_FIFO8(rx_fifo, XilinxSPIPS),
1334         VMSTATE_UINT32_ARRAY(regs, XilinxSPIPS, XLNX_SPIPS_R_MAX),
1335         VMSTATE_UINT8(snoop_state, XilinxSPIPS),
1336         VMSTATE_END_OF_LIST()
1337     }
1338 };
1339 
1340 static int xlnx_zynqmp_qspips_post_load(void *opaque, int version_id)
1341 {
1342     XlnxZynqMPQSPIPS *s = (XlnxZynqMPQSPIPS *)opaque;
1343     XilinxSPIPS *qs = XILINX_SPIPS(s);
1344 
1345     if (ARRAY_FIELD_EX32(s->regs, GQSPI_SELECT, GENERIC_QSPI_EN) &&
1346         fifo8_is_empty(&qs->rx_fifo) && fifo8_is_empty(&qs->tx_fifo)) {
1347         xlnx_zynqmp_qspips_update_ixr(s);
1348         xlnx_zynqmp_qspips_update_cs_lines(s);
1349     }
1350     return 0;
1351 }
1352 
1353 static const VMStateDescription vmstate_xilinx_qspips = {
1354     .name = "xilinx_qspips",
1355     .version_id = 1,
1356     .minimum_version_id = 1,
1357     .fields = (VMStateField[]) {
1358         VMSTATE_STRUCT(parent_obj, XilinxQSPIPS, 0,
1359                        vmstate_xilinx_spips, XilinxSPIPS),
1360         VMSTATE_END_OF_LIST()
1361     }
1362 };
1363 
1364 static const VMStateDescription vmstate_xlnx_zynqmp_qspips = {
1365     .name = "xlnx_zynqmp_qspips",
1366     .version_id = 1,
1367     .minimum_version_id = 1,
1368     .post_load = xlnx_zynqmp_qspips_post_load,
1369     .fields = (VMStateField[]) {
1370         VMSTATE_STRUCT(parent_obj, XlnxZynqMPQSPIPS, 0,
1371                        vmstate_xilinx_qspips, XilinxQSPIPS),
1372         VMSTATE_FIFO8(tx_fifo_g, XlnxZynqMPQSPIPS),
1373         VMSTATE_FIFO8(rx_fifo_g, XlnxZynqMPQSPIPS),
1374         VMSTATE_FIFO32(fifo_g, XlnxZynqMPQSPIPS),
1375         VMSTATE_UINT32_ARRAY(regs, XlnxZynqMPQSPIPS, XLNX_ZYNQMP_SPIPS_R_MAX),
1376         VMSTATE_END_OF_LIST()
1377     }
1378 };
1379 
1380 static Property xilinx_qspips_properties[] = {
1381     /* We had to turn this off for 2.10 as it is not compatible with migration.
1382      * It can be enabled but will prevent the device to be migrated.
1383      * This will go aways when a fix will be released.
1384      */
1385     DEFINE_PROP_BOOL("x-mmio-exec", XilinxQSPIPS, mmio_execution_enabled,
1386                      false),
1387     DEFINE_PROP_END_OF_LIST(),
1388 };
1389 
1390 static Property xilinx_spips_properties[] = {
1391     DEFINE_PROP_UINT8("num-busses", XilinxSPIPS, num_busses, 1),
1392     DEFINE_PROP_UINT8("num-ss-bits", XilinxSPIPS, num_cs, 4),
1393     DEFINE_PROP_UINT8("num-txrx-bytes", XilinxSPIPS, num_txrx_bytes, 1),
1394     DEFINE_PROP_END_OF_LIST(),
1395 };
1396 
1397 static void xilinx_qspips_class_init(ObjectClass *klass, void * data)
1398 {
1399     DeviceClass *dc = DEVICE_CLASS(klass);
1400     XilinxSPIPSClass *xsc = XILINX_SPIPS_CLASS(klass);
1401 
1402     dc->realize = xilinx_qspips_realize;
1403     dc->props = xilinx_qspips_properties;
1404     xsc->reg_ops = &qspips_ops;
1405     xsc->rx_fifo_size = RXFF_A_Q;
1406     xsc->tx_fifo_size = TXFF_A_Q;
1407 }
1408 
1409 static void xilinx_spips_class_init(ObjectClass *klass, void *data)
1410 {
1411     DeviceClass *dc = DEVICE_CLASS(klass);
1412     XilinxSPIPSClass *xsc = XILINX_SPIPS_CLASS(klass);
1413 
1414     dc->realize = xilinx_spips_realize;
1415     dc->reset = xilinx_spips_reset;
1416     dc->props = xilinx_spips_properties;
1417     dc->vmsd = &vmstate_xilinx_spips;
1418 
1419     xsc->reg_ops = &spips_ops;
1420     xsc->rx_fifo_size = RXFF_A;
1421     xsc->tx_fifo_size = TXFF_A;
1422 }
1423 
1424 static void xlnx_zynqmp_qspips_class_init(ObjectClass *klass, void * data)
1425 {
1426     DeviceClass *dc = DEVICE_CLASS(klass);
1427     XilinxSPIPSClass *xsc = XILINX_SPIPS_CLASS(klass);
1428 
1429     dc->realize = xlnx_zynqmp_qspips_realize;
1430     dc->reset = xlnx_zynqmp_qspips_reset;
1431     dc->vmsd = &vmstate_xlnx_zynqmp_qspips;
1432     xsc->reg_ops = &xlnx_zynqmp_qspips_ops;
1433     xsc->rx_fifo_size = RXFF_A_Q;
1434     xsc->tx_fifo_size = TXFF_A_Q;
1435 }
1436 
1437 static const TypeInfo xilinx_spips_info = {
1438     .name  = TYPE_XILINX_SPIPS,
1439     .parent = TYPE_SYS_BUS_DEVICE,
1440     .instance_size  = sizeof(XilinxSPIPS),
1441     .class_init = xilinx_spips_class_init,
1442     .class_size = sizeof(XilinxSPIPSClass),
1443 };
1444 
1445 static const TypeInfo xilinx_qspips_info = {
1446     .name  = TYPE_XILINX_QSPIPS,
1447     .parent = TYPE_XILINX_SPIPS,
1448     .instance_size  = sizeof(XilinxQSPIPS),
1449     .class_init = xilinx_qspips_class_init,
1450 };
1451 
1452 static const TypeInfo xlnx_zynqmp_qspips_info = {
1453     .name  = TYPE_XLNX_ZYNQMP_QSPIPS,
1454     .parent = TYPE_XILINX_QSPIPS,
1455     .instance_size  = sizeof(XlnxZynqMPQSPIPS),
1456     .instance_init  = xlnx_zynqmp_qspips_init,
1457     .class_init = xlnx_zynqmp_qspips_class_init,
1458 };
1459 
1460 static void xilinx_spips_register_types(void)
1461 {
1462     type_register_static(&xilinx_spips_info);
1463     type_register_static(&xilinx_qspips_info);
1464     type_register_static(&xlnx_zynqmp_qspips_info);
1465 }
1466 
1467 type_init(xilinx_spips_register_types)
1468