131e17060SPaolo Bonzini /* 231e17060SPaolo Bonzini * QEMU model of the Xilinx Zynq SPI controller 331e17060SPaolo Bonzini * 431e17060SPaolo Bonzini * Copyright (c) 2012 Peter A. G. Crosthwaite 531e17060SPaolo Bonzini * 631e17060SPaolo Bonzini * Permission is hereby granted, free of charge, to any person obtaining a copy 731e17060SPaolo Bonzini * of this software and associated documentation files (the "Software"), to deal 831e17060SPaolo Bonzini * in the Software without restriction, including without limitation the rights 931e17060SPaolo Bonzini * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 1031e17060SPaolo Bonzini * copies of the Software, and to permit persons to whom the Software is 1131e17060SPaolo Bonzini * furnished to do so, subject to the following conditions: 1231e17060SPaolo Bonzini * 1331e17060SPaolo Bonzini * The above copyright notice and this permission notice shall be included in 1431e17060SPaolo Bonzini * all copies or substantial portions of the Software. 1531e17060SPaolo Bonzini * 1631e17060SPaolo Bonzini * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1731e17060SPaolo Bonzini * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1831e17060SPaolo Bonzini * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 1931e17060SPaolo Bonzini * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 2031e17060SPaolo Bonzini * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 2131e17060SPaolo Bonzini * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 2231e17060SPaolo Bonzini * THE SOFTWARE. 2331e17060SPaolo Bonzini */ 2431e17060SPaolo Bonzini 258ef94f0bSPeter Maydell #include "qemu/osdep.h" 2631e17060SPaolo Bonzini #include "hw/sysbus.h" 2731e17060SPaolo Bonzini #include "sysemu/sysemu.h" 2831e17060SPaolo Bonzini #include "hw/ptimer.h" 2931e17060SPaolo Bonzini #include "qemu/log.h" 3031e17060SPaolo Bonzini #include "qemu/bitops.h" 316363235bSAlistair Francis #include "hw/ssi/xilinx_spips.h" 3283c3a1f6SKONRAD Frederic #include "qapi/error.h" 33ef06ca39SFrancisco Iglesias #include "hw/register.h" 3483c3a1f6SKONRAD Frederic #include "migration/blocker.h" 3531e17060SPaolo Bonzini 364a5b6fa8SPeter Crosthwaite #ifndef XILINX_SPIPS_ERR_DEBUG 374a5b6fa8SPeter Crosthwaite #define XILINX_SPIPS_ERR_DEBUG 0 384a5b6fa8SPeter Crosthwaite #endif 394a5b6fa8SPeter Crosthwaite 404a5b6fa8SPeter Crosthwaite #define DB_PRINT_L(level, ...) do { \ 414a5b6fa8SPeter Crosthwaite if (XILINX_SPIPS_ERR_DEBUG > (level)) { \ 4231e17060SPaolo Bonzini fprintf(stderr, ": %s: ", __func__); \ 4331e17060SPaolo Bonzini fprintf(stderr, ## __VA_ARGS__); \ 444a5b6fa8SPeter Crosthwaite } \ 4531e17060SPaolo Bonzini } while (0); 4631e17060SPaolo Bonzini 4731e17060SPaolo Bonzini /* config register */ 4831e17060SPaolo Bonzini #define R_CONFIG (0x00 / 4) 49c8f8f9fbSPeter Maydell #define IFMODE (1U << 31) 502fdd171eSFrancisco Iglesias #define R_CONFIG_ENDIAN (1 << 26) 5131e17060SPaolo Bonzini #define MODEFAIL_GEN_EN (1 << 17) 5231e17060SPaolo Bonzini #define MAN_START_COM (1 << 16) 5331e17060SPaolo Bonzini #define MAN_START_EN (1 << 15) 5431e17060SPaolo Bonzini #define MANUAL_CS (1 << 14) 5531e17060SPaolo Bonzini #define CS (0xF << 10) 5631e17060SPaolo Bonzini #define CS_SHIFT (10) 5731e17060SPaolo Bonzini #define PERI_SEL (1 << 9) 5831e17060SPaolo Bonzini #define REF_CLK (1 << 8) 5931e17060SPaolo Bonzini #define FIFO_WIDTH (3 << 6) 6031e17060SPaolo Bonzini #define BAUD_RATE_DIV (7 << 3) 6131e17060SPaolo Bonzini #define CLK_PH (1 << 2) 6231e17060SPaolo Bonzini #define CLK_POL (1 << 1) 6331e17060SPaolo Bonzini #define MODE_SEL (1 << 0) 642133a5f6SPeter Crosthwaite #define R_CONFIG_RSVD (0x7bf40000) 6531e17060SPaolo Bonzini 6631e17060SPaolo Bonzini /* interrupt mechanism */ 6731e17060SPaolo Bonzini #define R_INTR_STATUS (0x04 / 4) 6831e17060SPaolo Bonzini #define R_INTR_EN (0x08 / 4) 6931e17060SPaolo Bonzini #define R_INTR_DIS (0x0C / 4) 7031e17060SPaolo Bonzini #define R_INTR_MASK (0x10 / 4) 7131e17060SPaolo Bonzini #define IXR_TX_FIFO_UNDERFLOW (1 << 6) 7231e17060SPaolo Bonzini #define IXR_RX_FIFO_FULL (1 << 5) 7331e17060SPaolo Bonzini #define IXR_RX_FIFO_NOT_EMPTY (1 << 4) 7431e17060SPaolo Bonzini #define IXR_TX_FIFO_FULL (1 << 3) 7531e17060SPaolo Bonzini #define IXR_TX_FIFO_NOT_FULL (1 << 2) 7631e17060SPaolo Bonzini #define IXR_TX_FIFO_MODE_FAIL (1 << 1) 7731e17060SPaolo Bonzini #define IXR_RX_FIFO_OVERFLOW (1 << 0) 7831e17060SPaolo Bonzini #define IXR_ALL ((IXR_TX_FIFO_UNDERFLOW<<1)-1) 7931e17060SPaolo Bonzini 8031e17060SPaolo Bonzini #define R_EN (0x14 / 4) 8131e17060SPaolo Bonzini #define R_DELAY (0x18 / 4) 8231e17060SPaolo Bonzini #define R_TX_DATA (0x1C / 4) 8331e17060SPaolo Bonzini #define R_RX_DATA (0x20 / 4) 8431e17060SPaolo Bonzini #define R_SLAVE_IDLE_COUNT (0x24 / 4) 8531e17060SPaolo Bonzini #define R_TX_THRES (0x28 / 4) 8631e17060SPaolo Bonzini #define R_RX_THRES (0x2C / 4) 8731e17060SPaolo Bonzini #define R_TXD1 (0x80 / 4) 8831e17060SPaolo Bonzini #define R_TXD2 (0x84 / 4) 8931e17060SPaolo Bonzini #define R_TXD3 (0x88 / 4) 9031e17060SPaolo Bonzini 9131e17060SPaolo Bonzini #define R_LQSPI_CFG (0xa0 / 4) 9231e17060SPaolo Bonzini #define R_LQSPI_CFG_RESET 0x03A002EB 93c8f8f9fbSPeter Maydell #define LQSPI_CFG_LQ_MODE (1U << 31) 9431e17060SPaolo Bonzini #define LQSPI_CFG_TWO_MEM (1 << 30) 95*fbfaa507SFrancisco Iglesias #define LQSPI_CFG_SEP_BUS (1 << 29) 9631e17060SPaolo Bonzini #define LQSPI_CFG_U_PAGE (1 << 28) 97*fbfaa507SFrancisco Iglesias #define LQSPI_CFG_ADDR4 (1 << 27) 9831e17060SPaolo Bonzini #define LQSPI_CFG_MODE_EN (1 << 25) 9931e17060SPaolo Bonzini #define LQSPI_CFG_MODE_WIDTH 8 10031e17060SPaolo Bonzini #define LQSPI_CFG_MODE_SHIFT 16 10131e17060SPaolo Bonzini #define LQSPI_CFG_DUMMY_WIDTH 3 10231e17060SPaolo Bonzini #define LQSPI_CFG_DUMMY_SHIFT 8 10331e17060SPaolo Bonzini #define LQSPI_CFG_INST_CODE 0xFF 10431e17060SPaolo Bonzini 105ef06ca39SFrancisco Iglesias #define R_CMND (0xc0 / 4) 106ef06ca39SFrancisco Iglesias #define R_CMND_RXFIFO_DRAIN (1 << 19) 107ef06ca39SFrancisco Iglesias FIELD(CMND, PARTIAL_BYTE_LEN, 16, 3) 108ef06ca39SFrancisco Iglesias #define R_CMND_EXT_ADD (1 << 15) 109ef06ca39SFrancisco Iglesias FIELD(CMND, RX_DISCARD, 8, 7) 110ef06ca39SFrancisco Iglesias FIELD(CMND, DUMMY_CYCLES, 2, 6) 111ef06ca39SFrancisco Iglesias #define R_CMND_DMA_EN (1 << 1) 112ef06ca39SFrancisco Iglesias #define R_CMND_PUSH_WAIT (1 << 0) 113275e28ccSFrancisco Iglesias #define R_TRANSFER_SIZE (0xc4 / 4) 11431e17060SPaolo Bonzini #define R_LQSPI_STS (0xA4 / 4) 11531e17060SPaolo Bonzini #define LQSPI_STS_WR_RECVD (1 << 1) 11631e17060SPaolo Bonzini 11731e17060SPaolo Bonzini #define R_MOD_ID (0xFC / 4) 11831e17060SPaolo Bonzini 11931e17060SPaolo Bonzini /* size of TXRX FIFOs */ 12031e17060SPaolo Bonzini #define RXFF_A 32 12131e17060SPaolo Bonzini #define TXFF_A 32 12231e17060SPaolo Bonzini 12310e60b35SPeter Crosthwaite #define RXFF_A_Q (64 * 4) 12410e60b35SPeter Crosthwaite #define TXFF_A_Q (64 * 4) 12510e60b35SPeter Crosthwaite 12631e17060SPaolo Bonzini /* 16MB per linear region */ 12731e17060SPaolo Bonzini #define LQSPI_ADDRESS_BITS 24 12831e17060SPaolo Bonzini 12931e17060SPaolo Bonzini #define SNOOP_CHECKING 0xFF 130ef06ca39SFrancisco Iglesias #define SNOOP_ADDR 0xF0 131ef06ca39SFrancisco Iglesias #define SNOOP_NONE 0xEE 13231e17060SPaolo Bonzini #define SNOOP_STRIPING 0 13331e17060SPaolo Bonzini 13431e17060SPaolo Bonzini static inline int num_effective_busses(XilinxSPIPS *s) 13531e17060SPaolo Bonzini { 13631e17060SPaolo Bonzini return (s->regs[R_LQSPI_CFG] & LQSPI_CFG_SEP_BUS && 13731e17060SPaolo Bonzini s->regs[R_LQSPI_CFG] & LQSPI_CFG_TWO_MEM) ? s->num_busses : 1; 13831e17060SPaolo Bonzini } 13931e17060SPaolo Bonzini 140c4f08ffeSPeter Crosthwaite static inline bool xilinx_spips_cs_is_set(XilinxSPIPS *s, int i, int field) 141c4f08ffeSPeter Crosthwaite { 142c4f08ffeSPeter Crosthwaite return ~field & (1 << i) && (s->regs[R_CONFIG] & MANUAL_CS 143c4f08ffeSPeter Crosthwaite || !fifo8_is_empty(&s->tx_fifo)); 144c4f08ffeSPeter Crosthwaite } 145c4f08ffeSPeter Crosthwaite 14631e17060SPaolo Bonzini static void xilinx_spips_update_cs_lines(XilinxSPIPS *s) 14731e17060SPaolo Bonzini { 14831e17060SPaolo Bonzini int i, j; 14931e17060SPaolo Bonzini bool found = false; 15031e17060SPaolo Bonzini int field = s->regs[R_CONFIG] >> CS_SHIFT; 15131e17060SPaolo Bonzini 15231e17060SPaolo Bonzini for (i = 0; i < s->num_cs; i++) { 15331e17060SPaolo Bonzini for (j = 0; j < num_effective_busses(s); j++) { 15431e17060SPaolo Bonzini int upage = !!(s->regs[R_LQSPI_STS] & LQSPI_CFG_U_PAGE); 15531e17060SPaolo Bonzini int cs_to_set = (j * s->num_cs + i + upage) % 15631e17060SPaolo Bonzini (s->num_cs * s->num_busses); 15731e17060SPaolo Bonzini 158c4f08ffeSPeter Crosthwaite if (xilinx_spips_cs_is_set(s, i, field) && !found) { 1594a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "selecting slave %d\n", i); 16031e17060SPaolo Bonzini qemu_set_irq(s->cs_lines[cs_to_set], 0); 161ef06ca39SFrancisco Iglesias if (s->cs_lines_state[cs_to_set]) { 162ef06ca39SFrancisco Iglesias s->cs_lines_state[cs_to_set] = false; 163ef06ca39SFrancisco Iglesias s->rx_discard = ARRAY_FIELD_EX32(s->regs, CMND, RX_DISCARD); 164ef06ca39SFrancisco Iglesias } 16531e17060SPaolo Bonzini } else { 1664a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "deselecting slave %d\n", i); 16731e17060SPaolo Bonzini qemu_set_irq(s->cs_lines[cs_to_set], 1); 168ef06ca39SFrancisco Iglesias s->cs_lines_state[cs_to_set] = true; 16931e17060SPaolo Bonzini } 17031e17060SPaolo Bonzini } 171c4f08ffeSPeter Crosthwaite if (xilinx_spips_cs_is_set(s, i, field)) { 17231e17060SPaolo Bonzini found = true; 17331e17060SPaolo Bonzini } 17431e17060SPaolo Bonzini } 17531e17060SPaolo Bonzini if (!found) { 17631e17060SPaolo Bonzini s->snoop_state = SNOOP_CHECKING; 177ef06ca39SFrancisco Iglesias s->cmd_dummies = 0; 178ef06ca39SFrancisco Iglesias s->link_state = 1; 179ef06ca39SFrancisco Iglesias s->link_state_next = 1; 180ef06ca39SFrancisco Iglesias s->link_state_next_when = 0; 1814a5b6fa8SPeter Crosthwaite DB_PRINT_L(1, "moving to snoop check state\n"); 18231e17060SPaolo Bonzini } 18331e17060SPaolo Bonzini } 18431e17060SPaolo Bonzini 18531e17060SPaolo Bonzini static void xilinx_spips_update_ixr(XilinxSPIPS *s) 18631e17060SPaolo Bonzini { 1873ea728d0SPeter Crosthwaite if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_LQ_MODE) { 1883ea728d0SPeter Crosthwaite return; 1893ea728d0SPeter Crosthwaite } 19031e17060SPaolo Bonzini /* These are set/cleared as they occur */ 19131e17060SPaolo Bonzini s->regs[R_INTR_STATUS] &= (IXR_TX_FIFO_UNDERFLOW | IXR_RX_FIFO_OVERFLOW | 19231e17060SPaolo Bonzini IXR_TX_FIFO_MODE_FAIL); 19331e17060SPaolo Bonzini /* these are pure functions of fifo state, set them here */ 19431e17060SPaolo Bonzini s->regs[R_INTR_STATUS] |= 19531e17060SPaolo Bonzini (fifo8_is_full(&s->rx_fifo) ? IXR_RX_FIFO_FULL : 0) | 19631e17060SPaolo Bonzini (s->rx_fifo.num >= s->regs[R_RX_THRES] ? IXR_RX_FIFO_NOT_EMPTY : 0) | 19731e17060SPaolo Bonzini (fifo8_is_full(&s->tx_fifo) ? IXR_TX_FIFO_FULL : 0) | 19831e17060SPaolo Bonzini (s->tx_fifo.num < s->regs[R_TX_THRES] ? IXR_TX_FIFO_NOT_FULL : 0); 19931e17060SPaolo Bonzini /* drive external interrupt pin */ 20031e17060SPaolo Bonzini int new_irqline = !!(s->regs[R_INTR_MASK] & s->regs[R_INTR_STATUS] & 20131e17060SPaolo Bonzini IXR_ALL); 20231e17060SPaolo Bonzini if (new_irqline != s->irqline) { 20331e17060SPaolo Bonzini s->irqline = new_irqline; 20431e17060SPaolo Bonzini qemu_set_irq(s->irq, s->irqline); 20531e17060SPaolo Bonzini } 20631e17060SPaolo Bonzini } 20731e17060SPaolo Bonzini 20831e17060SPaolo Bonzini static void xilinx_spips_reset(DeviceState *d) 20931e17060SPaolo Bonzini { 21031e17060SPaolo Bonzini XilinxSPIPS *s = XILINX_SPIPS(d); 21131e17060SPaolo Bonzini 21231e17060SPaolo Bonzini int i; 2136363235bSAlistair Francis for (i = 0; i < XLNX_SPIPS_R_MAX; i++) { 21431e17060SPaolo Bonzini s->regs[i] = 0; 21531e17060SPaolo Bonzini } 21631e17060SPaolo Bonzini 21731e17060SPaolo Bonzini fifo8_reset(&s->rx_fifo); 21831e17060SPaolo Bonzini fifo8_reset(&s->rx_fifo); 21931e17060SPaolo Bonzini /* non zero resets */ 22031e17060SPaolo Bonzini s->regs[R_CONFIG] |= MODEFAIL_GEN_EN; 22131e17060SPaolo Bonzini s->regs[R_SLAVE_IDLE_COUNT] = 0xFF; 22231e17060SPaolo Bonzini s->regs[R_TX_THRES] = 1; 22331e17060SPaolo Bonzini s->regs[R_RX_THRES] = 1; 22431e17060SPaolo Bonzini /* FIXME: move magic number definition somewhere sensible */ 22531e17060SPaolo Bonzini s->regs[R_MOD_ID] = 0x01090106; 22631e17060SPaolo Bonzini s->regs[R_LQSPI_CFG] = R_LQSPI_CFG_RESET; 227ef06ca39SFrancisco Iglesias s->link_state = 1; 228ef06ca39SFrancisco Iglesias s->link_state_next = 1; 229ef06ca39SFrancisco Iglesias s->link_state_next_when = 0; 23031e17060SPaolo Bonzini s->snoop_state = SNOOP_CHECKING; 231ef06ca39SFrancisco Iglesias s->cmd_dummies = 0; 232275e28ccSFrancisco Iglesias s->man_start_com = false; 23331e17060SPaolo Bonzini xilinx_spips_update_ixr(s); 23431e17060SPaolo Bonzini xilinx_spips_update_cs_lines(s); 23531e17060SPaolo Bonzini } 23631e17060SPaolo Bonzini 237c3725b85SFrancisco Iglesias /* N way (num) in place bit striper. Lay out row wise bits (MSB to LSB) 2389151da25SPeter Crosthwaite * column wise (from element 0 to N-1). num is the length of x, and dir 2399151da25SPeter Crosthwaite * reverses the direction of the transform. Best illustrated by example: 2409151da25SPeter Crosthwaite * Each digit in the below array is a single bit (num == 3): 2419151da25SPeter Crosthwaite * 242c3725b85SFrancisco Iglesias * {{ 76543210, } ----- stripe (dir == false) -----> {{ 741gdaFC, } 243c3725b85SFrancisco Iglesias * { hgfedcba, } { 630fcHEB, } 244c3725b85SFrancisco Iglesias * { HGFEDCBA, }} <---- upstripe (dir == true) ----- { 52hebGDA, }} 2459151da25SPeter Crosthwaite */ 2469151da25SPeter Crosthwaite 2479151da25SPeter Crosthwaite static inline void stripe8(uint8_t *x, int num, bool dir) 2489151da25SPeter Crosthwaite { 2499151da25SPeter Crosthwaite uint8_t r[num]; 2509151da25SPeter Crosthwaite memset(r, 0, sizeof(uint8_t) * num); 2519151da25SPeter Crosthwaite int idx[2] = {0, 0}; 252c3725b85SFrancisco Iglesias int bit[2] = {0, 7}; 2539151da25SPeter Crosthwaite int d = dir; 2549151da25SPeter Crosthwaite 2559151da25SPeter Crosthwaite for (idx[0] = 0; idx[0] < num; ++idx[0]) { 256c3725b85SFrancisco Iglesias for (bit[0] = 7; bit[0] >= 0; bit[0]--) { 257c3725b85SFrancisco Iglesias r[idx[!d]] |= x[idx[d]] & 1 << bit[d] ? 1 << bit[!d] : 0; 2589151da25SPeter Crosthwaite idx[1] = (idx[1] + 1) % num; 2599151da25SPeter Crosthwaite if (!idx[1]) { 260c3725b85SFrancisco Iglesias bit[1]--; 2619151da25SPeter Crosthwaite } 2629151da25SPeter Crosthwaite } 2639151da25SPeter Crosthwaite } 2649151da25SPeter Crosthwaite memcpy(x, r, sizeof(uint8_t) * num); 2659151da25SPeter Crosthwaite } 2669151da25SPeter Crosthwaite 267ef06ca39SFrancisco Iglesias static int xilinx_spips_num_dummies(XilinxQSPIPS *qs, uint8_t command) 268ef06ca39SFrancisco Iglesias { 269ef06ca39SFrancisco Iglesias if (!qs) { 270ef06ca39SFrancisco Iglesias /* The SPI device is not a QSPI device */ 271ef06ca39SFrancisco Iglesias return -1; 272ef06ca39SFrancisco Iglesias } 273ef06ca39SFrancisco Iglesias 274ef06ca39SFrancisco Iglesias switch (command) { /* check for dummies */ 275ef06ca39SFrancisco Iglesias case READ: /* no dummy bytes/cycles */ 276ef06ca39SFrancisco Iglesias case PP: 277ef06ca39SFrancisco Iglesias case DPP: 278ef06ca39SFrancisco Iglesias case QPP: 279ef06ca39SFrancisco Iglesias case READ_4: 280ef06ca39SFrancisco Iglesias case PP_4: 281ef06ca39SFrancisco Iglesias case QPP_4: 282ef06ca39SFrancisco Iglesias return 0; 283ef06ca39SFrancisco Iglesias case FAST_READ: 284ef06ca39SFrancisco Iglesias case DOR: 285ef06ca39SFrancisco Iglesias case QOR: 286ef06ca39SFrancisco Iglesias case DOR_4: 287ef06ca39SFrancisco Iglesias case QOR_4: 288ef06ca39SFrancisco Iglesias return 1; 289ef06ca39SFrancisco Iglesias case DIOR: 290ef06ca39SFrancisco Iglesias case FAST_READ_4: 291ef06ca39SFrancisco Iglesias case DIOR_4: 292ef06ca39SFrancisco Iglesias return 2; 293ef06ca39SFrancisco Iglesias case QIOR: 294ef06ca39SFrancisco Iglesias case QIOR_4: 295ef06ca39SFrancisco Iglesias return 5; 296ef06ca39SFrancisco Iglesias default: 297ef06ca39SFrancisco Iglesias return -1; 298ef06ca39SFrancisco Iglesias } 299ef06ca39SFrancisco Iglesias } 300ef06ca39SFrancisco Iglesias 301ef06ca39SFrancisco Iglesias static inline uint8_t get_addr_length(XilinxSPIPS *s, uint8_t cmd) 302ef06ca39SFrancisco Iglesias { 303ef06ca39SFrancisco Iglesias switch (cmd) { 304ef06ca39SFrancisco Iglesias case PP_4: 305ef06ca39SFrancisco Iglesias case QPP_4: 306ef06ca39SFrancisco Iglesias case READ_4: 307ef06ca39SFrancisco Iglesias case QIOR_4: 308ef06ca39SFrancisco Iglesias case FAST_READ_4: 309ef06ca39SFrancisco Iglesias case DOR_4: 310ef06ca39SFrancisco Iglesias case QOR_4: 311ef06ca39SFrancisco Iglesias case DIOR_4: 312ef06ca39SFrancisco Iglesias return 4; 313ef06ca39SFrancisco Iglesias default: 314ef06ca39SFrancisco Iglesias return (s->regs[R_CMND] & R_CMND_EXT_ADD) ? 4 : 3; 315ef06ca39SFrancisco Iglesias } 316ef06ca39SFrancisco Iglesias } 317ef06ca39SFrancisco Iglesias 31831e17060SPaolo Bonzini static void xilinx_spips_flush_txfifo(XilinxSPIPS *s) 31931e17060SPaolo Bonzini { 3204a5b6fa8SPeter Crosthwaite int debug_level = 0; 321ef06ca39SFrancisco Iglesias XilinxQSPIPS *q = (XilinxQSPIPS *) object_dynamic_cast(OBJECT(s), 322ef06ca39SFrancisco Iglesias TYPE_XILINX_QSPIPS); 3234a5b6fa8SPeter Crosthwaite 32431e17060SPaolo Bonzini for (;;) { 32531e17060SPaolo Bonzini int i; 32631e17060SPaolo Bonzini uint8_t tx = 0; 3279151da25SPeter Crosthwaite uint8_t tx_rx[num_effective_busses(s)]; 328ef06ca39SFrancisco Iglesias uint8_t dummy_cycles = 0; 329ef06ca39SFrancisco Iglesias uint8_t addr_length; 33031e17060SPaolo Bonzini 33131e17060SPaolo Bonzini if (fifo8_is_empty(&s->tx_fifo)) { 3323ea728d0SPeter Crosthwaite if (!(s->regs[R_LQSPI_CFG] & LQSPI_CFG_LQ_MODE)) { 33331e17060SPaolo Bonzini s->regs[R_INTR_STATUS] |= IXR_TX_FIFO_UNDERFLOW; 3343ea728d0SPeter Crosthwaite } 33531e17060SPaolo Bonzini xilinx_spips_update_ixr(s); 33631e17060SPaolo Bonzini return; 3379151da25SPeter Crosthwaite } else if (s->snoop_state == SNOOP_STRIPING) { 3389151da25SPeter Crosthwaite for (i = 0; i < num_effective_busses(s); ++i) { 3399151da25SPeter Crosthwaite tx_rx[i] = fifo8_pop(&s->tx_fifo); 3409151da25SPeter Crosthwaite } 3419151da25SPeter Crosthwaite stripe8(tx_rx, num_effective_busses(s), false); 342ef06ca39SFrancisco Iglesias } else if (s->snoop_state >= SNOOP_ADDR) { 34331e17060SPaolo Bonzini tx = fifo8_pop(&s->tx_fifo); 3449151da25SPeter Crosthwaite for (i = 0; i < num_effective_busses(s); ++i) { 3459151da25SPeter Crosthwaite tx_rx[i] = tx; 34631e17060SPaolo Bonzini } 347ef06ca39SFrancisco Iglesias } else { 348ef06ca39SFrancisco Iglesias /* Extract a dummy byte and generate dummy cycles according to the 349ef06ca39SFrancisco Iglesias * link state */ 350ef06ca39SFrancisco Iglesias tx = fifo8_pop(&s->tx_fifo); 351ef06ca39SFrancisco Iglesias dummy_cycles = 8 / s->link_state; 35231e17060SPaolo Bonzini } 3539151da25SPeter Crosthwaite 3549151da25SPeter Crosthwaite for (i = 0; i < num_effective_busses(s); ++i) { 355c3725b85SFrancisco Iglesias int bus = num_effective_busses(s) - 1 - i; 356ef06ca39SFrancisco Iglesias if (dummy_cycles) { 357ef06ca39SFrancisco Iglesias int d; 358ef06ca39SFrancisco Iglesias for (d = 0; d < dummy_cycles; ++d) { 359ef06ca39SFrancisco Iglesias tx_rx[0] = ssi_transfer(s->spi[bus], (uint32_t)tx_rx[0]); 360ef06ca39SFrancisco Iglesias } 361ef06ca39SFrancisco Iglesias } else { 3624a5b6fa8SPeter Crosthwaite DB_PRINT_L(debug_level, "tx = %02x\n", tx_rx[i]); 363c3725b85SFrancisco Iglesias tx_rx[i] = ssi_transfer(s->spi[bus], (uint32_t)tx_rx[i]); 3644a5b6fa8SPeter Crosthwaite DB_PRINT_L(debug_level, "rx = %02x\n", tx_rx[i]); 3659151da25SPeter Crosthwaite } 366ef06ca39SFrancisco Iglesias } 3679151da25SPeter Crosthwaite 368ef06ca39SFrancisco Iglesias if (s->regs[R_CMND] & R_CMND_RXFIFO_DRAIN) { 369ef06ca39SFrancisco Iglesias DB_PRINT_L(debug_level, "dircarding drained rx byte\n"); 370ef06ca39SFrancisco Iglesias /* Do nothing */ 371ef06ca39SFrancisco Iglesias } else if (s->rx_discard) { 372ef06ca39SFrancisco Iglesias DB_PRINT_L(debug_level, "dircarding discarded rx byte\n"); 373ef06ca39SFrancisco Iglesias s->rx_discard -= 8 / s->link_state; 374ef06ca39SFrancisco Iglesias } else if (fifo8_is_full(&s->rx_fifo)) { 37531e17060SPaolo Bonzini s->regs[R_INTR_STATUS] |= IXR_RX_FIFO_OVERFLOW; 3764a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "rx FIFO overflow"); 3779151da25SPeter Crosthwaite } else if (s->snoop_state == SNOOP_STRIPING) { 3789151da25SPeter Crosthwaite stripe8(tx_rx, num_effective_busses(s), true); 3799151da25SPeter Crosthwaite for (i = 0; i < num_effective_busses(s); ++i) { 3809151da25SPeter Crosthwaite fifo8_push(&s->rx_fifo, (uint8_t)tx_rx[i]); 381ef06ca39SFrancisco Iglesias DB_PRINT_L(debug_level, "pushing striped rx byte\n"); 3829151da25SPeter Crosthwaite } 38331e17060SPaolo Bonzini } else { 384ef06ca39SFrancisco Iglesias DB_PRINT_L(debug_level, "pushing unstriped rx byte\n"); 3859151da25SPeter Crosthwaite fifo8_push(&s->rx_fifo, (uint8_t)tx_rx[0]); 38631e17060SPaolo Bonzini } 38731e17060SPaolo Bonzini 388ef06ca39SFrancisco Iglesias if (s->link_state_next_when) { 389ef06ca39SFrancisco Iglesias s->link_state_next_when--; 390ef06ca39SFrancisco Iglesias if (!s->link_state_next_when) { 391ef06ca39SFrancisco Iglesias s->link_state = s->link_state_next; 392ef06ca39SFrancisco Iglesias } 393ef06ca39SFrancisco Iglesias } 394ef06ca39SFrancisco Iglesias 3954a5b6fa8SPeter Crosthwaite DB_PRINT_L(debug_level, "initial snoop state: %x\n", 3964a5b6fa8SPeter Crosthwaite (unsigned)s->snoop_state); 39731e17060SPaolo Bonzini switch (s->snoop_state) { 39831e17060SPaolo Bonzini case (SNOOP_CHECKING): 399ef06ca39SFrancisco Iglesias /* Store the count of dummy bytes in the txfifo */ 400ef06ca39SFrancisco Iglesias s->cmd_dummies = xilinx_spips_num_dummies(q, tx); 401ef06ca39SFrancisco Iglesias addr_length = get_addr_length(s, tx); 402ef06ca39SFrancisco Iglesias if (s->cmd_dummies < 0) { 40331e17060SPaolo Bonzini s->snoop_state = SNOOP_NONE; 404ef06ca39SFrancisco Iglesias } else { 405ef06ca39SFrancisco Iglesias s->snoop_state = SNOOP_ADDR + addr_length - 1; 406ef06ca39SFrancisco Iglesias } 407ef06ca39SFrancisco Iglesias switch (tx) { 408ef06ca39SFrancisco Iglesias case DPP: 409ef06ca39SFrancisco Iglesias case DOR: 410ef06ca39SFrancisco Iglesias case DOR_4: 411ef06ca39SFrancisco Iglesias s->link_state_next = 2; 412ef06ca39SFrancisco Iglesias s->link_state_next_when = addr_length + s->cmd_dummies; 413ef06ca39SFrancisco Iglesias break; 414ef06ca39SFrancisco Iglesias case QPP: 415ef06ca39SFrancisco Iglesias case QPP_4: 416ef06ca39SFrancisco Iglesias case QOR: 417ef06ca39SFrancisco Iglesias case QOR_4: 418ef06ca39SFrancisco Iglesias s->link_state_next = 4; 419ef06ca39SFrancisco Iglesias s->link_state_next_when = addr_length + s->cmd_dummies; 420ef06ca39SFrancisco Iglesias break; 421ef06ca39SFrancisco Iglesias case DIOR: 422ef06ca39SFrancisco Iglesias case DIOR_4: 423ef06ca39SFrancisco Iglesias s->link_state = 2; 424ef06ca39SFrancisco Iglesias break; 425ef06ca39SFrancisco Iglesias case QIOR: 426ef06ca39SFrancisco Iglesias case QIOR_4: 427ef06ca39SFrancisco Iglesias s->link_state = 4; 428ef06ca39SFrancisco Iglesias break; 429ef06ca39SFrancisco Iglesias } 430ef06ca39SFrancisco Iglesias break; 431ef06ca39SFrancisco Iglesias case (SNOOP_ADDR): 432ef06ca39SFrancisco Iglesias /* Address has been transmitted, transmit dummy cycles now if 433ef06ca39SFrancisco Iglesias * needed */ 434ef06ca39SFrancisco Iglesias if (s->cmd_dummies < 0) { 435ef06ca39SFrancisco Iglesias s->snoop_state = SNOOP_NONE; 436ef06ca39SFrancisco Iglesias } else { 437ef06ca39SFrancisco Iglesias s->snoop_state = s->cmd_dummies; 43831e17060SPaolo Bonzini } 43931e17060SPaolo Bonzini break; 44031e17060SPaolo Bonzini case (SNOOP_STRIPING): 44131e17060SPaolo Bonzini case (SNOOP_NONE): 4424a5b6fa8SPeter Crosthwaite /* Once we hit the boring stuff - squelch debug noise */ 4434a5b6fa8SPeter Crosthwaite if (!debug_level) { 4444a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "squelching debug info ....\n"); 4454a5b6fa8SPeter Crosthwaite debug_level = 1; 4464a5b6fa8SPeter Crosthwaite } 44731e17060SPaolo Bonzini break; 44831e17060SPaolo Bonzini default: 44931e17060SPaolo Bonzini s->snoop_state--; 45031e17060SPaolo Bonzini } 4514a5b6fa8SPeter Crosthwaite DB_PRINT_L(debug_level, "final snoop state: %x\n", 4524a5b6fa8SPeter Crosthwaite (unsigned)s->snoop_state); 45331e17060SPaolo Bonzini } 45431e17060SPaolo Bonzini } 45531e17060SPaolo Bonzini 4562fdd171eSFrancisco Iglesias static inline void tx_data_bytes(Fifo8 *fifo, uint32_t value, int num, bool be) 4572fdd171eSFrancisco Iglesias { 4582fdd171eSFrancisco Iglesias int i; 4592fdd171eSFrancisco Iglesias for (i = 0; i < num && !fifo8_is_full(fifo); ++i) { 4602fdd171eSFrancisco Iglesias if (be) { 4612fdd171eSFrancisco Iglesias fifo8_push(fifo, (uint8_t)(value >> 24)); 4622fdd171eSFrancisco Iglesias value <<= 8; 4632fdd171eSFrancisco Iglesias } else { 4642fdd171eSFrancisco Iglesias fifo8_push(fifo, (uint8_t)value); 4652fdd171eSFrancisco Iglesias value >>= 8; 4662fdd171eSFrancisco Iglesias } 4672fdd171eSFrancisco Iglesias } 4682fdd171eSFrancisco Iglesias } 4692fdd171eSFrancisco Iglesias 470275e28ccSFrancisco Iglesias static void xilinx_spips_check_zero_pump(XilinxSPIPS *s) 471275e28ccSFrancisco Iglesias { 472275e28ccSFrancisco Iglesias if (!s->regs[R_TRANSFER_SIZE]) { 473275e28ccSFrancisco Iglesias return; 474275e28ccSFrancisco Iglesias } 475275e28ccSFrancisco Iglesias if (!fifo8_is_empty(&s->tx_fifo) && s->regs[R_CMND] & R_CMND_PUSH_WAIT) { 476275e28ccSFrancisco Iglesias return; 477275e28ccSFrancisco Iglesias } 478275e28ccSFrancisco Iglesias /* 479275e28ccSFrancisco Iglesias * The zero pump must never fill tx fifo such that rx overflow is 480275e28ccSFrancisco Iglesias * possible 481275e28ccSFrancisco Iglesias */ 482275e28ccSFrancisco Iglesias while (s->regs[R_TRANSFER_SIZE] && 483275e28ccSFrancisco Iglesias s->rx_fifo.num + s->tx_fifo.num < RXFF_A_Q - 3) { 484275e28ccSFrancisco Iglesias /* endianess just doesn't matter when zero pumping */ 485275e28ccSFrancisco Iglesias tx_data_bytes(&s->tx_fifo, 0, 4, false); 486275e28ccSFrancisco Iglesias s->regs[R_TRANSFER_SIZE] &= ~0x03ull; 487275e28ccSFrancisco Iglesias s->regs[R_TRANSFER_SIZE] -= 4; 488275e28ccSFrancisco Iglesias } 489275e28ccSFrancisco Iglesias } 490275e28ccSFrancisco Iglesias 491275e28ccSFrancisco Iglesias static void xilinx_spips_check_flush(XilinxSPIPS *s) 492275e28ccSFrancisco Iglesias { 493275e28ccSFrancisco Iglesias if (s->man_start_com || 494275e28ccSFrancisco Iglesias (!fifo8_is_empty(&s->tx_fifo) && 495275e28ccSFrancisco Iglesias !(s->regs[R_CONFIG] & MAN_START_EN))) { 496275e28ccSFrancisco Iglesias xilinx_spips_check_zero_pump(s); 497275e28ccSFrancisco Iglesias xilinx_spips_flush_txfifo(s); 498275e28ccSFrancisco Iglesias } 499275e28ccSFrancisco Iglesias if (fifo8_is_empty(&s->tx_fifo) && !s->regs[R_TRANSFER_SIZE]) { 500275e28ccSFrancisco Iglesias s->man_start_com = false; 501275e28ccSFrancisco Iglesias } 502275e28ccSFrancisco Iglesias xilinx_spips_update_ixr(s); 503275e28ccSFrancisco Iglesias } 504275e28ccSFrancisco Iglesias 5052fdd171eSFrancisco Iglesias static inline int rx_data_bytes(Fifo8 *fifo, uint8_t *value, int max) 50631e17060SPaolo Bonzini { 50731e17060SPaolo Bonzini int i; 50831e17060SPaolo Bonzini 5092fdd171eSFrancisco Iglesias for (i = 0; i < max && !fifo8_is_empty(fifo); ++i) { 5102fdd171eSFrancisco Iglesias value[i] = fifo8_pop(fifo); 51131e17060SPaolo Bonzini } 5122fdd171eSFrancisco Iglesias return max - i; 51331e17060SPaolo Bonzini } 51431e17060SPaolo Bonzini 51531e17060SPaolo Bonzini static uint64_t xilinx_spips_read(void *opaque, hwaddr addr, 51631e17060SPaolo Bonzini unsigned size) 51731e17060SPaolo Bonzini { 51831e17060SPaolo Bonzini XilinxSPIPS *s = opaque; 51931e17060SPaolo Bonzini uint32_t mask = ~0; 52031e17060SPaolo Bonzini uint32_t ret; 521b0b7ae62SPeter Crosthwaite uint8_t rx_buf[4]; 5222fdd171eSFrancisco Iglesias int shortfall; 52331e17060SPaolo Bonzini 52431e17060SPaolo Bonzini addr >>= 2; 52531e17060SPaolo Bonzini switch (addr) { 52631e17060SPaolo Bonzini case R_CONFIG: 5272133a5f6SPeter Crosthwaite mask = ~(R_CONFIG_RSVD | MAN_START_COM); 52831e17060SPaolo Bonzini break; 52931e17060SPaolo Bonzini case R_INTR_STATUS: 53087920b44SPeter Crosthwaite ret = s->regs[addr] & IXR_ALL; 53187920b44SPeter Crosthwaite s->regs[addr] = 0; 5324a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret); 53387920b44SPeter Crosthwaite return ret; 53431e17060SPaolo Bonzini case R_INTR_MASK: 53531e17060SPaolo Bonzini mask = IXR_ALL; 53631e17060SPaolo Bonzini break; 53731e17060SPaolo Bonzini case R_EN: 53831e17060SPaolo Bonzini mask = 0x1; 53931e17060SPaolo Bonzini break; 54031e17060SPaolo Bonzini case R_SLAVE_IDLE_COUNT: 54131e17060SPaolo Bonzini mask = 0xFF; 54231e17060SPaolo Bonzini break; 54331e17060SPaolo Bonzini case R_MOD_ID: 54431e17060SPaolo Bonzini mask = 0x01FFFFFF; 54531e17060SPaolo Bonzini break; 54631e17060SPaolo Bonzini case R_INTR_EN: 54731e17060SPaolo Bonzini case R_INTR_DIS: 54831e17060SPaolo Bonzini case R_TX_DATA: 54931e17060SPaolo Bonzini mask = 0; 55031e17060SPaolo Bonzini break; 55131e17060SPaolo Bonzini case R_RX_DATA: 552b0b7ae62SPeter Crosthwaite memset(rx_buf, 0, sizeof(rx_buf)); 5532fdd171eSFrancisco Iglesias shortfall = rx_data_bytes(&s->rx_fifo, rx_buf, s->num_txrx_bytes); 5542fdd171eSFrancisco Iglesias ret = s->regs[R_CONFIG] & R_CONFIG_ENDIAN ? 5552fdd171eSFrancisco Iglesias cpu_to_be32(*(uint32_t *)rx_buf) : 5562fdd171eSFrancisco Iglesias cpu_to_le32(*(uint32_t *)rx_buf); 5572fdd171eSFrancisco Iglesias if (!(s->regs[R_CONFIG] & R_CONFIG_ENDIAN)) { 5582fdd171eSFrancisco Iglesias ret <<= 8 * shortfall; 5592fdd171eSFrancisco Iglesias } 5604a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret); 56131e17060SPaolo Bonzini xilinx_spips_update_ixr(s); 56231e17060SPaolo Bonzini return ret; 56331e17060SPaolo Bonzini } 5644a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4, 5654a5b6fa8SPeter Crosthwaite s->regs[addr] & mask); 56631e17060SPaolo Bonzini return s->regs[addr] & mask; 56731e17060SPaolo Bonzini 56831e17060SPaolo Bonzini } 56931e17060SPaolo Bonzini 57031e17060SPaolo Bonzini static void xilinx_spips_write(void *opaque, hwaddr addr, 57131e17060SPaolo Bonzini uint64_t value, unsigned size) 57231e17060SPaolo Bonzini { 57331e17060SPaolo Bonzini int mask = ~0; 57431e17060SPaolo Bonzini XilinxSPIPS *s = opaque; 57531e17060SPaolo Bonzini 5764a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr, (unsigned)value); 57731e17060SPaolo Bonzini addr >>= 2; 57831e17060SPaolo Bonzini switch (addr) { 57931e17060SPaolo Bonzini case R_CONFIG: 5802133a5f6SPeter Crosthwaite mask = ~(R_CONFIG_RSVD | MAN_START_COM); 581275e28ccSFrancisco Iglesias if ((value & MAN_START_COM) && (s->regs[R_CONFIG] & MAN_START_EN)) { 582275e28ccSFrancisco Iglesias s->man_start_com = true; 58331e17060SPaolo Bonzini } 58431e17060SPaolo Bonzini break; 58531e17060SPaolo Bonzini case R_INTR_STATUS: 58631e17060SPaolo Bonzini mask = IXR_ALL; 58731e17060SPaolo Bonzini s->regs[R_INTR_STATUS] &= ~(mask & value); 58831e17060SPaolo Bonzini goto no_reg_update; 58931e17060SPaolo Bonzini case R_INTR_DIS: 59031e17060SPaolo Bonzini mask = IXR_ALL; 59131e17060SPaolo Bonzini s->regs[R_INTR_MASK] &= ~(mask & value); 59231e17060SPaolo Bonzini goto no_reg_update; 59331e17060SPaolo Bonzini case R_INTR_EN: 59431e17060SPaolo Bonzini mask = IXR_ALL; 59531e17060SPaolo Bonzini s->regs[R_INTR_MASK] |= mask & value; 59631e17060SPaolo Bonzini goto no_reg_update; 59731e17060SPaolo Bonzini case R_EN: 59831e17060SPaolo Bonzini mask = 0x1; 59931e17060SPaolo Bonzini break; 60031e17060SPaolo Bonzini case R_SLAVE_IDLE_COUNT: 60131e17060SPaolo Bonzini mask = 0xFF; 60231e17060SPaolo Bonzini break; 60331e17060SPaolo Bonzini case R_RX_DATA: 60431e17060SPaolo Bonzini case R_INTR_MASK: 60531e17060SPaolo Bonzini case R_MOD_ID: 60631e17060SPaolo Bonzini mask = 0; 60731e17060SPaolo Bonzini break; 60831e17060SPaolo Bonzini case R_TX_DATA: 6092fdd171eSFrancisco Iglesias tx_data_bytes(&s->tx_fifo, (uint32_t)value, s->num_txrx_bytes, 6102fdd171eSFrancisco Iglesias s->regs[R_CONFIG] & R_CONFIG_ENDIAN); 61131e17060SPaolo Bonzini goto no_reg_update; 61231e17060SPaolo Bonzini case R_TXD1: 6132fdd171eSFrancisco Iglesias tx_data_bytes(&s->tx_fifo, (uint32_t)value, 1, 6142fdd171eSFrancisco Iglesias s->regs[R_CONFIG] & R_CONFIG_ENDIAN); 61531e17060SPaolo Bonzini goto no_reg_update; 61631e17060SPaolo Bonzini case R_TXD2: 6172fdd171eSFrancisco Iglesias tx_data_bytes(&s->tx_fifo, (uint32_t)value, 2, 6182fdd171eSFrancisco Iglesias s->regs[R_CONFIG] & R_CONFIG_ENDIAN); 61931e17060SPaolo Bonzini goto no_reg_update; 62031e17060SPaolo Bonzini case R_TXD3: 6212fdd171eSFrancisco Iglesias tx_data_bytes(&s->tx_fifo, (uint32_t)value, 3, 6222fdd171eSFrancisco Iglesias s->regs[R_CONFIG] & R_CONFIG_ENDIAN); 62331e17060SPaolo Bonzini goto no_reg_update; 62431e17060SPaolo Bonzini } 62531e17060SPaolo Bonzini s->regs[addr] = (s->regs[addr] & ~mask) | (value & mask); 62631e17060SPaolo Bonzini no_reg_update: 627c4f08ffeSPeter Crosthwaite xilinx_spips_update_cs_lines(s); 628275e28ccSFrancisco Iglesias xilinx_spips_check_flush(s); 62931e17060SPaolo Bonzini xilinx_spips_update_cs_lines(s); 630c4f08ffeSPeter Crosthwaite xilinx_spips_update_ixr(s); 63131e17060SPaolo Bonzini } 63231e17060SPaolo Bonzini 63331e17060SPaolo Bonzini static const MemoryRegionOps spips_ops = { 63431e17060SPaolo Bonzini .read = xilinx_spips_read, 63531e17060SPaolo Bonzini .write = xilinx_spips_write, 63631e17060SPaolo Bonzini .endianness = DEVICE_LITTLE_ENDIAN, 63731e17060SPaolo Bonzini }; 63831e17060SPaolo Bonzini 639252b99baSKONRAD Frederic static void xilinx_qspips_invalidate_mmio_ptr(XilinxQSPIPS *q) 640252b99baSKONRAD Frederic { 641252b99baSKONRAD Frederic XilinxSPIPS *s = &q->parent_obj; 642252b99baSKONRAD Frederic 64383c3a1f6SKONRAD Frederic if ((q->mmio_execution_enabled) && (q->lqspi_cached_addr != ~0ULL)) { 644252b99baSKONRAD Frederic /* Invalidate the current mapped mmio */ 645252b99baSKONRAD Frederic memory_region_invalidate_mmio_ptr(&s->mmlqspi, q->lqspi_cached_addr, 646252b99baSKONRAD Frederic LQSPI_CACHE_SIZE); 647252b99baSKONRAD Frederic } 64883c3a1f6SKONRAD Frederic 64983c3a1f6SKONRAD Frederic q->lqspi_cached_addr = ~0ULL; 650252b99baSKONRAD Frederic } 651252b99baSKONRAD Frederic 652b5cd9143SPeter Crosthwaite static void xilinx_qspips_write(void *opaque, hwaddr addr, 653b5cd9143SPeter Crosthwaite uint64_t value, unsigned size) 654b5cd9143SPeter Crosthwaite { 655b5cd9143SPeter Crosthwaite XilinxQSPIPS *q = XILINX_QSPIPS(opaque); 656ef06ca39SFrancisco Iglesias XilinxSPIPS *s = XILINX_SPIPS(opaque); 657b5cd9143SPeter Crosthwaite 658b5cd9143SPeter Crosthwaite xilinx_spips_write(opaque, addr, value, size); 659b5cd9143SPeter Crosthwaite addr >>= 2; 660b5cd9143SPeter Crosthwaite 661b5cd9143SPeter Crosthwaite if (addr == R_LQSPI_CFG) { 662252b99baSKONRAD Frederic xilinx_qspips_invalidate_mmio_ptr(q); 663b5cd9143SPeter Crosthwaite } 664ef06ca39SFrancisco Iglesias if (s->regs[R_CMND] & R_CMND_RXFIFO_DRAIN) { 665ef06ca39SFrancisco Iglesias fifo8_reset(&s->rx_fifo); 666ef06ca39SFrancisco Iglesias } 667b5cd9143SPeter Crosthwaite } 668b5cd9143SPeter Crosthwaite 669b5cd9143SPeter Crosthwaite static const MemoryRegionOps qspips_ops = { 670b5cd9143SPeter Crosthwaite .read = xilinx_spips_read, 671b5cd9143SPeter Crosthwaite .write = xilinx_qspips_write, 672b5cd9143SPeter Crosthwaite .endianness = DEVICE_LITTLE_ENDIAN, 673b5cd9143SPeter Crosthwaite }; 674b5cd9143SPeter Crosthwaite 67531e17060SPaolo Bonzini #define LQSPI_CACHE_SIZE 1024 67631e17060SPaolo Bonzini 677252b99baSKONRAD Frederic static void lqspi_load_cache(void *opaque, hwaddr addr) 67831e17060SPaolo Bonzini { 6796b91f015SPeter Crosthwaite XilinxQSPIPS *q = opaque; 68031e17060SPaolo Bonzini XilinxSPIPS *s = opaque; 681252b99baSKONRAD Frederic int i; 682252b99baSKONRAD Frederic int flash_addr = ((addr & ~(LQSPI_CACHE_SIZE - 1)) 683252b99baSKONRAD Frederic / num_effective_busses(s)); 68431e17060SPaolo Bonzini int slave = flash_addr >> LQSPI_ADDRESS_BITS; 68531e17060SPaolo Bonzini int cache_entry = 0; 68615408b42SPeter Crosthwaite uint32_t u_page_save = s->regs[R_LQSPI_STS] & ~LQSPI_CFG_U_PAGE; 68715408b42SPeter Crosthwaite 688252b99baSKONRAD Frederic if (addr < q->lqspi_cached_addr || 689252b99baSKONRAD Frederic addr > q->lqspi_cached_addr + LQSPI_CACHE_SIZE - 4) { 690252b99baSKONRAD Frederic xilinx_qspips_invalidate_mmio_ptr(q); 69115408b42SPeter Crosthwaite s->regs[R_LQSPI_STS] &= ~LQSPI_CFG_U_PAGE; 69215408b42SPeter Crosthwaite s->regs[R_LQSPI_STS] |= slave ? LQSPI_CFG_U_PAGE : 0; 69331e17060SPaolo Bonzini 6944a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "config reg status: %08x\n", s->regs[R_LQSPI_CFG]); 69531e17060SPaolo Bonzini 69631e17060SPaolo Bonzini fifo8_reset(&s->tx_fifo); 69731e17060SPaolo Bonzini fifo8_reset(&s->rx_fifo); 69831e17060SPaolo Bonzini 69931e17060SPaolo Bonzini /* instruction */ 7004a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "pushing read instruction: %02x\n", 7014a5b6fa8SPeter Crosthwaite (unsigned)(uint8_t)(s->regs[R_LQSPI_CFG] & 7024a5b6fa8SPeter Crosthwaite LQSPI_CFG_INST_CODE)); 70331e17060SPaolo Bonzini fifo8_push(&s->tx_fifo, s->regs[R_LQSPI_CFG] & LQSPI_CFG_INST_CODE); 70431e17060SPaolo Bonzini /* read address */ 7054a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "pushing read address %06x\n", flash_addr); 706*fbfaa507SFrancisco Iglesias if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_ADDR4) { 707*fbfaa507SFrancisco Iglesias fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 24)); 708*fbfaa507SFrancisco Iglesias } 70931e17060SPaolo Bonzini fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 16)); 71031e17060SPaolo Bonzini fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 8)); 71131e17060SPaolo Bonzini fifo8_push(&s->tx_fifo, (uint8_t)flash_addr); 71231e17060SPaolo Bonzini /* mode bits */ 71331e17060SPaolo Bonzini if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_MODE_EN) { 71431e17060SPaolo Bonzini fifo8_push(&s->tx_fifo, extract32(s->regs[R_LQSPI_CFG], 71531e17060SPaolo Bonzini LQSPI_CFG_MODE_SHIFT, 71631e17060SPaolo Bonzini LQSPI_CFG_MODE_WIDTH)); 71731e17060SPaolo Bonzini } 71831e17060SPaolo Bonzini /* dummy bytes */ 71931e17060SPaolo Bonzini for (i = 0; i < (extract32(s->regs[R_LQSPI_CFG], LQSPI_CFG_DUMMY_SHIFT, 72031e17060SPaolo Bonzini LQSPI_CFG_DUMMY_WIDTH)); ++i) { 7214a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "pushing dummy byte\n"); 72231e17060SPaolo Bonzini fifo8_push(&s->tx_fifo, 0); 72331e17060SPaolo Bonzini } 724c4f08ffeSPeter Crosthwaite xilinx_spips_update_cs_lines(s); 72531e17060SPaolo Bonzini xilinx_spips_flush_txfifo(s); 72631e17060SPaolo Bonzini fifo8_reset(&s->rx_fifo); 72731e17060SPaolo Bonzini 7284a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "starting QSPI data read\n"); 72931e17060SPaolo Bonzini 730b0b7ae62SPeter Crosthwaite while (cache_entry < LQSPI_CACHE_SIZE) { 731b0b7ae62SPeter Crosthwaite for (i = 0; i < 64; ++i) { 7322fdd171eSFrancisco Iglesias tx_data_bytes(&s->tx_fifo, 0, 1, false); 733a66418f6SPeter Crosthwaite } 73431e17060SPaolo Bonzini xilinx_spips_flush_txfifo(s); 735b0b7ae62SPeter Crosthwaite for (i = 0; i < 64; ++i) { 7362fdd171eSFrancisco Iglesias rx_data_bytes(&s->rx_fifo, &q->lqspi_buf[cache_entry++], 1); 737a66418f6SPeter Crosthwaite } 73831e17060SPaolo Bonzini } 73931e17060SPaolo Bonzini 74015408b42SPeter Crosthwaite s->regs[R_LQSPI_STS] &= ~LQSPI_CFG_U_PAGE; 74115408b42SPeter Crosthwaite s->regs[R_LQSPI_STS] |= u_page_save; 74231e17060SPaolo Bonzini xilinx_spips_update_cs_lines(s); 74331e17060SPaolo Bonzini 744b0b7ae62SPeter Crosthwaite q->lqspi_cached_addr = flash_addr * num_effective_busses(s); 745252b99baSKONRAD Frederic } 746252b99baSKONRAD Frederic } 747252b99baSKONRAD Frederic 748252b99baSKONRAD Frederic static void *lqspi_request_mmio_ptr(void *opaque, hwaddr addr, unsigned *size, 749252b99baSKONRAD Frederic unsigned *offset) 750252b99baSKONRAD Frederic { 751252b99baSKONRAD Frederic XilinxQSPIPS *q = opaque; 75283c3a1f6SKONRAD Frederic hwaddr offset_within_the_region; 753252b99baSKONRAD Frederic 75483c3a1f6SKONRAD Frederic if (!q->mmio_execution_enabled) { 75583c3a1f6SKONRAD Frederic return NULL; 75683c3a1f6SKONRAD Frederic } 75783c3a1f6SKONRAD Frederic 75883c3a1f6SKONRAD Frederic offset_within_the_region = addr & ~(LQSPI_CACHE_SIZE - 1); 759252b99baSKONRAD Frederic lqspi_load_cache(opaque, offset_within_the_region); 760252b99baSKONRAD Frederic *size = LQSPI_CACHE_SIZE; 761252b99baSKONRAD Frederic *offset = offset_within_the_region; 762252b99baSKONRAD Frederic return q->lqspi_buf; 763252b99baSKONRAD Frederic } 764252b99baSKONRAD Frederic 765252b99baSKONRAD Frederic static uint64_t 766252b99baSKONRAD Frederic lqspi_read(void *opaque, hwaddr addr, unsigned int size) 767252b99baSKONRAD Frederic { 768252b99baSKONRAD Frederic XilinxQSPIPS *q = opaque; 769252b99baSKONRAD Frederic uint32_t ret; 770252b99baSKONRAD Frederic 771252b99baSKONRAD Frederic if (addr >= q->lqspi_cached_addr && 772252b99baSKONRAD Frederic addr <= q->lqspi_cached_addr + LQSPI_CACHE_SIZE - 4) { 773252b99baSKONRAD Frederic uint8_t *retp = &q->lqspi_buf[addr - q->lqspi_cached_addr]; 774252b99baSKONRAD Frederic ret = cpu_to_le32(*(uint32_t *)retp); 775252b99baSKONRAD Frederic DB_PRINT_L(1, "addr: %08x, data: %08x\n", (unsigned)addr, 776252b99baSKONRAD Frederic (unsigned)ret); 777252b99baSKONRAD Frederic return ret; 778252b99baSKONRAD Frederic } else { 779252b99baSKONRAD Frederic lqspi_load_cache(opaque, addr); 78031e17060SPaolo Bonzini return lqspi_read(opaque, addr, size); 78131e17060SPaolo Bonzini } 78231e17060SPaolo Bonzini } 78331e17060SPaolo Bonzini 78431e17060SPaolo Bonzini static const MemoryRegionOps lqspi_ops = { 78531e17060SPaolo Bonzini .read = lqspi_read, 786252b99baSKONRAD Frederic .request_ptr = lqspi_request_mmio_ptr, 78731e17060SPaolo Bonzini .endianness = DEVICE_NATIVE_ENDIAN, 78831e17060SPaolo Bonzini .valid = { 789b0b7ae62SPeter Crosthwaite .min_access_size = 1, 79031e17060SPaolo Bonzini .max_access_size = 4 79131e17060SPaolo Bonzini } 79231e17060SPaolo Bonzini }; 79331e17060SPaolo Bonzini 79431e17060SPaolo Bonzini static void xilinx_spips_realize(DeviceState *dev, Error **errp) 79531e17060SPaolo Bonzini { 79631e17060SPaolo Bonzini XilinxSPIPS *s = XILINX_SPIPS(dev); 79731e17060SPaolo Bonzini SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 79810e60b35SPeter Crosthwaite XilinxSPIPSClass *xsc = XILINX_SPIPS_GET_CLASS(s); 799c8cccba3SPaolo Bonzini qemu_irq *cs; 80031e17060SPaolo Bonzini int i; 80131e17060SPaolo Bonzini 8024a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "realized spips\n"); 80331e17060SPaolo Bonzini 80431e17060SPaolo Bonzini s->spi = g_new(SSIBus *, s->num_busses); 80531e17060SPaolo Bonzini for (i = 0; i < s->num_busses; ++i) { 80631e17060SPaolo Bonzini char bus_name[16]; 80731e17060SPaolo Bonzini snprintf(bus_name, 16, "spi%d", i); 80831e17060SPaolo Bonzini s->spi[i] = ssi_create_bus(dev, bus_name); 80931e17060SPaolo Bonzini } 81031e17060SPaolo Bonzini 81131e17060SPaolo Bonzini s->cs_lines = g_new0(qemu_irq, s->num_cs * s->num_busses); 812ef06ca39SFrancisco Iglesias s->cs_lines_state = g_new0(bool, s->num_cs * s->num_busses); 813c8cccba3SPaolo Bonzini for (i = 0, cs = s->cs_lines; i < s->num_busses; ++i, cs += s->num_cs) { 814c8cccba3SPaolo Bonzini ssi_auto_connect_slaves(DEVICE(s), cs, s->spi[i]); 815c8cccba3SPaolo Bonzini } 816c8cccba3SPaolo Bonzini 81731e17060SPaolo Bonzini sysbus_init_irq(sbd, &s->irq); 81831e17060SPaolo Bonzini for (i = 0; i < s->num_cs * s->num_busses; ++i) { 81931e17060SPaolo Bonzini sysbus_init_irq(sbd, &s->cs_lines[i]); 82031e17060SPaolo Bonzini } 82131e17060SPaolo Bonzini 82229776739SPaolo Bonzini memory_region_init_io(&s->iomem, OBJECT(s), xsc->reg_ops, s, 8236363235bSAlistair Francis "spi", XLNX_SPIPS_R_MAX * 4); 82431e17060SPaolo Bonzini sysbus_init_mmio(sbd, &s->iomem); 82531e17060SPaolo Bonzini 8266b91f015SPeter Crosthwaite s->irqline = -1; 8276b91f015SPeter Crosthwaite 82810e60b35SPeter Crosthwaite fifo8_create(&s->rx_fifo, xsc->rx_fifo_size); 82910e60b35SPeter Crosthwaite fifo8_create(&s->tx_fifo, xsc->tx_fifo_size); 8306b91f015SPeter Crosthwaite } 8316b91f015SPeter Crosthwaite 8326b91f015SPeter Crosthwaite static void xilinx_qspips_realize(DeviceState *dev, Error **errp) 8336b91f015SPeter Crosthwaite { 8346b91f015SPeter Crosthwaite XilinxSPIPS *s = XILINX_SPIPS(dev); 8356b91f015SPeter Crosthwaite XilinxQSPIPS *q = XILINX_QSPIPS(dev); 8366b91f015SPeter Crosthwaite SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 8376b91f015SPeter Crosthwaite 8384a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "realized qspips\n"); 8396b91f015SPeter Crosthwaite 8406b91f015SPeter Crosthwaite s->num_busses = 2; 8416b91f015SPeter Crosthwaite s->num_cs = 2; 8426b91f015SPeter Crosthwaite s->num_txrx_bytes = 4; 8436b91f015SPeter Crosthwaite 8446b91f015SPeter Crosthwaite xilinx_spips_realize(dev, errp); 84529776739SPaolo Bonzini memory_region_init_io(&s->mmlqspi, OBJECT(s), &lqspi_ops, s, "lqspi", 84631e17060SPaolo Bonzini (1 << LQSPI_ADDRESS_BITS) * 2); 84731e17060SPaolo Bonzini sysbus_init_mmio(sbd, &s->mmlqspi); 84831e17060SPaolo Bonzini 8496b91f015SPeter Crosthwaite q->lqspi_cached_addr = ~0ULL; 85083c3a1f6SKONRAD Frederic 85183c3a1f6SKONRAD Frederic /* mmio_execution breaks migration better aborting than having strange 85283c3a1f6SKONRAD Frederic * bugs. 85383c3a1f6SKONRAD Frederic */ 85483c3a1f6SKONRAD Frederic if (q->mmio_execution_enabled) { 85583c3a1f6SKONRAD Frederic error_setg(&q->migration_blocker, 85683c3a1f6SKONRAD Frederic "enabling mmio_execution breaks migration"); 85783c3a1f6SKONRAD Frederic migrate_add_blocker(q->migration_blocker, &error_fatal); 85883c3a1f6SKONRAD Frederic } 85931e17060SPaolo Bonzini } 86031e17060SPaolo Bonzini 86131e17060SPaolo Bonzini static int xilinx_spips_post_load(void *opaque, int version_id) 86231e17060SPaolo Bonzini { 86331e17060SPaolo Bonzini xilinx_spips_update_ixr((XilinxSPIPS *)opaque); 86431e17060SPaolo Bonzini xilinx_spips_update_cs_lines((XilinxSPIPS *)opaque); 86531e17060SPaolo Bonzini return 0; 86631e17060SPaolo Bonzini } 86731e17060SPaolo Bonzini 86831e17060SPaolo Bonzini static const VMStateDescription vmstate_xilinx_spips = { 86931e17060SPaolo Bonzini .name = "xilinx_spips", 87031e17060SPaolo Bonzini .version_id = 2, 87131e17060SPaolo Bonzini .minimum_version_id = 2, 87231e17060SPaolo Bonzini .post_load = xilinx_spips_post_load, 87331e17060SPaolo Bonzini .fields = (VMStateField[]) { 87431e17060SPaolo Bonzini VMSTATE_FIFO8(tx_fifo, XilinxSPIPS), 87531e17060SPaolo Bonzini VMSTATE_FIFO8(rx_fifo, XilinxSPIPS), 8766363235bSAlistair Francis VMSTATE_UINT32_ARRAY(regs, XilinxSPIPS, XLNX_SPIPS_R_MAX), 87731e17060SPaolo Bonzini VMSTATE_UINT8(snoop_state, XilinxSPIPS), 87831e17060SPaolo Bonzini VMSTATE_END_OF_LIST() 87931e17060SPaolo Bonzini } 88031e17060SPaolo Bonzini }; 88131e17060SPaolo Bonzini 88283c3a1f6SKONRAD Frederic static Property xilinx_qspips_properties[] = { 88383c3a1f6SKONRAD Frederic /* We had to turn this off for 2.10 as it is not compatible with migration. 88483c3a1f6SKONRAD Frederic * It can be enabled but will prevent the device to be migrated. 88583c3a1f6SKONRAD Frederic * This will go aways when a fix will be released. 88683c3a1f6SKONRAD Frederic */ 88783c3a1f6SKONRAD Frederic DEFINE_PROP_BOOL("x-mmio-exec", XilinxQSPIPS, mmio_execution_enabled, 88883c3a1f6SKONRAD Frederic false), 88983c3a1f6SKONRAD Frederic DEFINE_PROP_END_OF_LIST(), 89083c3a1f6SKONRAD Frederic }; 89183c3a1f6SKONRAD Frederic 89231e17060SPaolo Bonzini static Property xilinx_spips_properties[] = { 89331e17060SPaolo Bonzini DEFINE_PROP_UINT8("num-busses", XilinxSPIPS, num_busses, 1), 89431e17060SPaolo Bonzini DEFINE_PROP_UINT8("num-ss-bits", XilinxSPIPS, num_cs, 4), 89531e17060SPaolo Bonzini DEFINE_PROP_UINT8("num-txrx-bytes", XilinxSPIPS, num_txrx_bytes, 1), 89631e17060SPaolo Bonzini DEFINE_PROP_END_OF_LIST(), 89731e17060SPaolo Bonzini }; 8986b91f015SPeter Crosthwaite 8996b91f015SPeter Crosthwaite static void xilinx_qspips_class_init(ObjectClass *klass, void * data) 9006b91f015SPeter Crosthwaite { 9016b91f015SPeter Crosthwaite DeviceClass *dc = DEVICE_CLASS(klass); 90210e60b35SPeter Crosthwaite XilinxSPIPSClass *xsc = XILINX_SPIPS_CLASS(klass); 9036b91f015SPeter Crosthwaite 9046b91f015SPeter Crosthwaite dc->realize = xilinx_qspips_realize; 90583c3a1f6SKONRAD Frederic dc->props = xilinx_qspips_properties; 906b5cd9143SPeter Crosthwaite xsc->reg_ops = &qspips_ops; 90710e60b35SPeter Crosthwaite xsc->rx_fifo_size = RXFF_A_Q; 90810e60b35SPeter Crosthwaite xsc->tx_fifo_size = TXFF_A_Q; 9096b91f015SPeter Crosthwaite } 9106b91f015SPeter Crosthwaite 91131e17060SPaolo Bonzini static void xilinx_spips_class_init(ObjectClass *klass, void *data) 91231e17060SPaolo Bonzini { 91331e17060SPaolo Bonzini DeviceClass *dc = DEVICE_CLASS(klass); 91410e60b35SPeter Crosthwaite XilinxSPIPSClass *xsc = XILINX_SPIPS_CLASS(klass); 91531e17060SPaolo Bonzini 91631e17060SPaolo Bonzini dc->realize = xilinx_spips_realize; 91731e17060SPaolo Bonzini dc->reset = xilinx_spips_reset; 91831e17060SPaolo Bonzini dc->props = xilinx_spips_properties; 91931e17060SPaolo Bonzini dc->vmsd = &vmstate_xilinx_spips; 92010e60b35SPeter Crosthwaite 921b5cd9143SPeter Crosthwaite xsc->reg_ops = &spips_ops; 92210e60b35SPeter Crosthwaite xsc->rx_fifo_size = RXFF_A; 92310e60b35SPeter Crosthwaite xsc->tx_fifo_size = TXFF_A; 92431e17060SPaolo Bonzini } 92531e17060SPaolo Bonzini 92631e17060SPaolo Bonzini static const TypeInfo xilinx_spips_info = { 92731e17060SPaolo Bonzini .name = TYPE_XILINX_SPIPS, 92831e17060SPaolo Bonzini .parent = TYPE_SYS_BUS_DEVICE, 92931e17060SPaolo Bonzini .instance_size = sizeof(XilinxSPIPS), 93031e17060SPaolo Bonzini .class_init = xilinx_spips_class_init, 93110e60b35SPeter Crosthwaite .class_size = sizeof(XilinxSPIPSClass), 93231e17060SPaolo Bonzini }; 93331e17060SPaolo Bonzini 9346b91f015SPeter Crosthwaite static const TypeInfo xilinx_qspips_info = { 9356b91f015SPeter Crosthwaite .name = TYPE_XILINX_QSPIPS, 9366b91f015SPeter Crosthwaite .parent = TYPE_XILINX_SPIPS, 9376b91f015SPeter Crosthwaite .instance_size = sizeof(XilinxQSPIPS), 9386b91f015SPeter Crosthwaite .class_init = xilinx_qspips_class_init, 9396b91f015SPeter Crosthwaite }; 9406b91f015SPeter Crosthwaite 94131e17060SPaolo Bonzini static void xilinx_spips_register_types(void) 94231e17060SPaolo Bonzini { 94331e17060SPaolo Bonzini type_register_static(&xilinx_spips_info); 9446b91f015SPeter Crosthwaite type_register_static(&xilinx_qspips_info); 94531e17060SPaolo Bonzini } 94631e17060SPaolo Bonzini 94731e17060SPaolo Bonzini type_init(xilinx_spips_register_types) 948