131e17060SPaolo Bonzini /* 231e17060SPaolo Bonzini * QEMU model of the Xilinx Zynq SPI controller 331e17060SPaolo Bonzini * 431e17060SPaolo Bonzini * Copyright (c) 2012 Peter A. G. Crosthwaite 531e17060SPaolo Bonzini * 631e17060SPaolo Bonzini * Permission is hereby granted, free of charge, to any person obtaining a copy 731e17060SPaolo Bonzini * of this software and associated documentation files (the "Software"), to deal 831e17060SPaolo Bonzini * in the Software without restriction, including without limitation the rights 931e17060SPaolo Bonzini * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 1031e17060SPaolo Bonzini * copies of the Software, and to permit persons to whom the Software is 1131e17060SPaolo Bonzini * furnished to do so, subject to the following conditions: 1231e17060SPaolo Bonzini * 1331e17060SPaolo Bonzini * The above copyright notice and this permission notice shall be included in 1431e17060SPaolo Bonzini * all copies or substantial portions of the Software. 1531e17060SPaolo Bonzini * 1631e17060SPaolo Bonzini * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1731e17060SPaolo Bonzini * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1831e17060SPaolo Bonzini * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 1931e17060SPaolo Bonzini * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 2031e17060SPaolo Bonzini * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 2131e17060SPaolo Bonzini * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 2231e17060SPaolo Bonzini * THE SOFTWARE. 2331e17060SPaolo Bonzini */ 2431e17060SPaolo Bonzini 258ef94f0bSPeter Maydell #include "qemu/osdep.h" 2631e17060SPaolo Bonzini #include "hw/sysbus.h" 2731e17060SPaolo Bonzini #include "sysemu/sysemu.h" 2831e17060SPaolo Bonzini #include "hw/ptimer.h" 2931e17060SPaolo Bonzini #include "qemu/log.h" 3031e17060SPaolo Bonzini #include "qemu/bitops.h" 316363235bSAlistair Francis #include "hw/ssi/xilinx_spips.h" 3283c3a1f6SKONRAD Frederic #include "qapi/error.h" 33ef06ca39SFrancisco Iglesias #include "hw/register.h" 34c95997a3SFrancisco Iglesias #include "sysemu/dma.h" 3583c3a1f6SKONRAD Frederic #include "migration/blocker.h" 3631e17060SPaolo Bonzini 374a5b6fa8SPeter Crosthwaite #ifndef XILINX_SPIPS_ERR_DEBUG 384a5b6fa8SPeter Crosthwaite #define XILINX_SPIPS_ERR_DEBUG 0 394a5b6fa8SPeter Crosthwaite #endif 404a5b6fa8SPeter Crosthwaite 414a5b6fa8SPeter Crosthwaite #define DB_PRINT_L(level, ...) do { \ 424a5b6fa8SPeter Crosthwaite if (XILINX_SPIPS_ERR_DEBUG > (level)) { \ 4331e17060SPaolo Bonzini fprintf(stderr, ": %s: ", __func__); \ 4431e17060SPaolo Bonzini fprintf(stderr, ## __VA_ARGS__); \ 454a5b6fa8SPeter Crosthwaite } \ 462562755eSEric Blake } while (0) 4731e17060SPaolo Bonzini 4831e17060SPaolo Bonzini /* config register */ 4931e17060SPaolo Bonzini #define R_CONFIG (0x00 / 4) 50c8f8f9fbSPeter Maydell #define IFMODE (1U << 31) 512fdd171eSFrancisco Iglesias #define R_CONFIG_ENDIAN (1 << 26) 5231e17060SPaolo Bonzini #define MODEFAIL_GEN_EN (1 << 17) 5331e17060SPaolo Bonzini #define MAN_START_COM (1 << 16) 5431e17060SPaolo Bonzini #define MAN_START_EN (1 << 15) 5531e17060SPaolo Bonzini #define MANUAL_CS (1 << 14) 5631e17060SPaolo Bonzini #define CS (0xF << 10) 5731e17060SPaolo Bonzini #define CS_SHIFT (10) 5831e17060SPaolo Bonzini #define PERI_SEL (1 << 9) 5931e17060SPaolo Bonzini #define REF_CLK (1 << 8) 6031e17060SPaolo Bonzini #define FIFO_WIDTH (3 << 6) 6131e17060SPaolo Bonzini #define BAUD_RATE_DIV (7 << 3) 6231e17060SPaolo Bonzini #define CLK_PH (1 << 2) 6331e17060SPaolo Bonzini #define CLK_POL (1 << 1) 6431e17060SPaolo Bonzini #define MODE_SEL (1 << 0) 652133a5f6SPeter Crosthwaite #define R_CONFIG_RSVD (0x7bf40000) 6631e17060SPaolo Bonzini 6731e17060SPaolo Bonzini /* interrupt mechanism */ 6831e17060SPaolo Bonzini #define R_INTR_STATUS (0x04 / 4) 694f0da466SAlistair Francis #define R_INTR_STATUS_RESET (0x104) 7031e17060SPaolo Bonzini #define R_INTR_EN (0x08 / 4) 7131e17060SPaolo Bonzini #define R_INTR_DIS (0x0C / 4) 7231e17060SPaolo Bonzini #define R_INTR_MASK (0x10 / 4) 7331e17060SPaolo Bonzini #define IXR_TX_FIFO_UNDERFLOW (1 << 6) 74c95997a3SFrancisco Iglesias /* Poll timeout not implemented */ 75c95997a3SFrancisco Iglesias #define IXR_RX_FIFO_EMPTY (1 << 11) 76c95997a3SFrancisco Iglesias #define IXR_GENERIC_FIFO_FULL (1 << 10) 77c95997a3SFrancisco Iglesias #define IXR_GENERIC_FIFO_NOT_FULL (1 << 9) 78c95997a3SFrancisco Iglesias #define IXR_TX_FIFO_EMPTY (1 << 8) 79c95997a3SFrancisco Iglesias #define IXR_GENERIC_FIFO_EMPTY (1 << 7) 8031e17060SPaolo Bonzini #define IXR_RX_FIFO_FULL (1 << 5) 8131e17060SPaolo Bonzini #define IXR_RX_FIFO_NOT_EMPTY (1 << 4) 8231e17060SPaolo Bonzini #define IXR_TX_FIFO_FULL (1 << 3) 8331e17060SPaolo Bonzini #define IXR_TX_FIFO_NOT_FULL (1 << 2) 8431e17060SPaolo Bonzini #define IXR_TX_FIFO_MODE_FAIL (1 << 1) 8531e17060SPaolo Bonzini #define IXR_RX_FIFO_OVERFLOW (1 << 0) 86c95997a3SFrancisco Iglesias #define IXR_ALL ((1 << 13) - 1) 87c95997a3SFrancisco Iglesias #define GQSPI_IXR_MASK 0xFBE 88c95997a3SFrancisco Iglesias #define IXR_SELF_CLEAR \ 89c95997a3SFrancisco Iglesias (IXR_GENERIC_FIFO_EMPTY \ 90c95997a3SFrancisco Iglesias | IXR_GENERIC_FIFO_FULL \ 91c95997a3SFrancisco Iglesias | IXR_GENERIC_FIFO_NOT_FULL \ 92c95997a3SFrancisco Iglesias | IXR_TX_FIFO_EMPTY \ 93c95997a3SFrancisco Iglesias | IXR_TX_FIFO_FULL \ 94c95997a3SFrancisco Iglesias | IXR_TX_FIFO_NOT_FULL \ 95c95997a3SFrancisco Iglesias | IXR_RX_FIFO_EMPTY \ 96c95997a3SFrancisco Iglesias | IXR_RX_FIFO_FULL \ 97c95997a3SFrancisco Iglesias | IXR_RX_FIFO_NOT_EMPTY) 9831e17060SPaolo Bonzini 9931e17060SPaolo Bonzini #define R_EN (0x14 / 4) 10031e17060SPaolo Bonzini #define R_DELAY (0x18 / 4) 10131e17060SPaolo Bonzini #define R_TX_DATA (0x1C / 4) 10231e17060SPaolo Bonzini #define R_RX_DATA (0x20 / 4) 10331e17060SPaolo Bonzini #define R_SLAVE_IDLE_COUNT (0x24 / 4) 10431e17060SPaolo Bonzini #define R_TX_THRES (0x28 / 4) 10531e17060SPaolo Bonzini #define R_RX_THRES (0x2C / 4) 1064f0da466SAlistair Francis #define R_GPIO (0x30 / 4) 1074f0da466SAlistair Francis #define R_LPBK_DLY_ADJ (0x38 / 4) 1084f0da466SAlistair Francis #define R_LPBK_DLY_ADJ_RESET (0x33) 10931e17060SPaolo Bonzini #define R_TXD1 (0x80 / 4) 11031e17060SPaolo Bonzini #define R_TXD2 (0x84 / 4) 11131e17060SPaolo Bonzini #define R_TXD3 (0x88 / 4) 11231e17060SPaolo Bonzini 11331e17060SPaolo Bonzini #define R_LQSPI_CFG (0xa0 / 4) 11431e17060SPaolo Bonzini #define R_LQSPI_CFG_RESET 0x03A002EB 115c8f8f9fbSPeter Maydell #define LQSPI_CFG_LQ_MODE (1U << 31) 11631e17060SPaolo Bonzini #define LQSPI_CFG_TWO_MEM (1 << 30) 117fbfaa507SFrancisco Iglesias #define LQSPI_CFG_SEP_BUS (1 << 29) 11831e17060SPaolo Bonzini #define LQSPI_CFG_U_PAGE (1 << 28) 119fbfaa507SFrancisco Iglesias #define LQSPI_CFG_ADDR4 (1 << 27) 12031e17060SPaolo Bonzini #define LQSPI_CFG_MODE_EN (1 << 25) 12131e17060SPaolo Bonzini #define LQSPI_CFG_MODE_WIDTH 8 12231e17060SPaolo Bonzini #define LQSPI_CFG_MODE_SHIFT 16 12331e17060SPaolo Bonzini #define LQSPI_CFG_DUMMY_WIDTH 3 12431e17060SPaolo Bonzini #define LQSPI_CFG_DUMMY_SHIFT 8 12531e17060SPaolo Bonzini #define LQSPI_CFG_INST_CODE 0xFF 12631e17060SPaolo Bonzini 127ef06ca39SFrancisco Iglesias #define R_CMND (0xc0 / 4) 128ef06ca39SFrancisco Iglesias #define R_CMND_RXFIFO_DRAIN (1 << 19) 129ef06ca39SFrancisco Iglesias FIELD(CMND, PARTIAL_BYTE_LEN, 16, 3) 130ef06ca39SFrancisco Iglesias #define R_CMND_EXT_ADD (1 << 15) 131ef06ca39SFrancisco Iglesias FIELD(CMND, RX_DISCARD, 8, 7) 132ef06ca39SFrancisco Iglesias FIELD(CMND, DUMMY_CYCLES, 2, 6) 133ef06ca39SFrancisco Iglesias #define R_CMND_DMA_EN (1 << 1) 134ef06ca39SFrancisco Iglesias #define R_CMND_PUSH_WAIT (1 << 0) 135275e28ccSFrancisco Iglesias #define R_TRANSFER_SIZE (0xc4 / 4) 13631e17060SPaolo Bonzini #define R_LQSPI_STS (0xA4 / 4) 13731e17060SPaolo Bonzini #define LQSPI_STS_WR_RECVD (1 << 1) 13831e17060SPaolo Bonzini 13931e17060SPaolo Bonzini #define R_MOD_ID (0xFC / 4) 14031e17060SPaolo Bonzini 141c95997a3SFrancisco Iglesias #define R_GQSPI_SELECT (0x144 / 4) 142c95997a3SFrancisco Iglesias FIELD(GQSPI_SELECT, GENERIC_QSPI_EN, 0, 1) 143c95997a3SFrancisco Iglesias #define R_GQSPI_ISR (0x104 / 4) 144c95997a3SFrancisco Iglesias #define R_GQSPI_IER (0x108 / 4) 145c95997a3SFrancisco Iglesias #define R_GQSPI_IDR (0x10c / 4) 146c95997a3SFrancisco Iglesias #define R_GQSPI_IMR (0x110 / 4) 1474f0da466SAlistair Francis #define R_GQSPI_IMR_RESET (0xfbe) 148c95997a3SFrancisco Iglesias #define R_GQSPI_TX_THRESH (0x128 / 4) 149c95997a3SFrancisco Iglesias #define R_GQSPI_RX_THRESH (0x12c / 4) 1504f0da466SAlistair Francis #define R_GQSPI_GPIO (0x130 / 4) 1514f0da466SAlistair Francis #define R_GQSPI_LPBK_DLY_ADJ (0x138 / 4) 1524f0da466SAlistair Francis #define R_GQSPI_LPBK_DLY_ADJ_RESET (0x33) 153c95997a3SFrancisco Iglesias #define R_GQSPI_CNFG (0x100 / 4) 154c95997a3SFrancisco Iglesias FIELD(GQSPI_CNFG, MODE_EN, 30, 2) 155c95997a3SFrancisco Iglesias FIELD(GQSPI_CNFG, GEN_FIFO_START_MODE, 29, 1) 156c95997a3SFrancisco Iglesias FIELD(GQSPI_CNFG, GEN_FIFO_START, 28, 1) 157c95997a3SFrancisco Iglesias FIELD(GQSPI_CNFG, ENDIAN, 26, 1) 158c95997a3SFrancisco Iglesias /* Poll timeout not implemented */ 159c95997a3SFrancisco Iglesias FIELD(GQSPI_CNFG, EN_POLL_TIMEOUT, 20, 1) 160c95997a3SFrancisco Iglesias /* QEMU doesnt care about any of these last three */ 161c95997a3SFrancisco Iglesias FIELD(GQSPI_CNFG, BR, 3, 3) 162c95997a3SFrancisco Iglesias FIELD(GQSPI_CNFG, CPH, 2, 1) 163c95997a3SFrancisco Iglesias FIELD(GQSPI_CNFG, CPL, 1, 1) 164c95997a3SFrancisco Iglesias #define R_GQSPI_GEN_FIFO (0x140 / 4) 165c95997a3SFrancisco Iglesias #define R_GQSPI_TXD (0x11c / 4) 166c95997a3SFrancisco Iglesias #define R_GQSPI_RXD (0x120 / 4) 167c95997a3SFrancisco Iglesias #define R_GQSPI_FIFO_CTRL (0x14c / 4) 168c95997a3SFrancisco Iglesias FIELD(GQSPI_FIFO_CTRL, RX_FIFO_RESET, 2, 1) 169c95997a3SFrancisco Iglesias FIELD(GQSPI_FIFO_CTRL, TX_FIFO_RESET, 1, 1) 170c95997a3SFrancisco Iglesias FIELD(GQSPI_FIFO_CTRL, GENERIC_FIFO_RESET, 0, 1) 171c95997a3SFrancisco Iglesias #define R_GQSPI_GFIFO_THRESH (0x150 / 4) 172c95997a3SFrancisco Iglesias #define R_GQSPI_DATA_STS (0x15c / 4) 173c95997a3SFrancisco Iglesias /* We use the snapshot register to hold the core state for the currently 174c95997a3SFrancisco Iglesias * or most recently executed command. So the generic fifo format is defined 175c95997a3SFrancisco Iglesias * for the snapshot register 176c95997a3SFrancisco Iglesias */ 177c95997a3SFrancisco Iglesias #define R_GQSPI_GF_SNAPSHOT (0x160 / 4) 178c95997a3SFrancisco Iglesias FIELD(GQSPI_GF_SNAPSHOT, POLL, 19, 1) 179c95997a3SFrancisco Iglesias FIELD(GQSPI_GF_SNAPSHOT, STRIPE, 18, 1) 180c95997a3SFrancisco Iglesias FIELD(GQSPI_GF_SNAPSHOT, RECIEVE, 17, 1) 181c95997a3SFrancisco Iglesias FIELD(GQSPI_GF_SNAPSHOT, TRANSMIT, 16, 1) 182c95997a3SFrancisco Iglesias FIELD(GQSPI_GF_SNAPSHOT, DATA_BUS_SELECT, 14, 2) 183c95997a3SFrancisco Iglesias FIELD(GQSPI_GF_SNAPSHOT, CHIP_SELECT, 12, 2) 184c95997a3SFrancisco Iglesias FIELD(GQSPI_GF_SNAPSHOT, SPI_MODE, 10, 2) 185c95997a3SFrancisco Iglesias FIELD(GQSPI_GF_SNAPSHOT, EXPONENT, 9, 1) 186c95997a3SFrancisco Iglesias FIELD(GQSPI_GF_SNAPSHOT, DATA_XFER, 8, 1) 187c95997a3SFrancisco Iglesias FIELD(GQSPI_GF_SNAPSHOT, IMMEDIATE_DATA, 0, 8) 1884f0da466SAlistair Francis #define R_GQSPI_MOD_ID (0x1fc / 4) 1894f0da466SAlistair Francis #define R_GQSPI_MOD_ID_RESET (0x10a0000) 1904f0da466SAlistair Francis 1914f0da466SAlistair Francis #define R_QSPIDMA_DST_CTRL (0x80c / 4) 1924f0da466SAlistair Francis #define R_QSPIDMA_DST_CTRL_RESET (0x803ffa00) 1934f0da466SAlistair Francis #define R_QSPIDMA_DST_I_MASK (0x820 / 4) 1944f0da466SAlistair Francis #define R_QSPIDMA_DST_I_MASK_RESET (0xfe) 1954f0da466SAlistair Francis #define R_QSPIDMA_DST_CTRL2 (0x824 / 4) 1964f0da466SAlistair Francis #define R_QSPIDMA_DST_CTRL2_RESET (0x081bfff8) 1974f0da466SAlistair Francis 19831e17060SPaolo Bonzini /* size of TXRX FIFOs */ 199c95997a3SFrancisco Iglesias #define RXFF_A (128) 200c95997a3SFrancisco Iglesias #define TXFF_A (128) 20131e17060SPaolo Bonzini 20210e60b35SPeter Crosthwaite #define RXFF_A_Q (64 * 4) 20310e60b35SPeter Crosthwaite #define TXFF_A_Q (64 * 4) 20410e60b35SPeter Crosthwaite 20531e17060SPaolo Bonzini /* 16MB per linear region */ 20631e17060SPaolo Bonzini #define LQSPI_ADDRESS_BITS 24 20731e17060SPaolo Bonzini 20831e17060SPaolo Bonzini #define SNOOP_CHECKING 0xFF 209ef06ca39SFrancisco Iglesias #define SNOOP_ADDR 0xF0 210ef06ca39SFrancisco Iglesias #define SNOOP_NONE 0xEE 21131e17060SPaolo Bonzini #define SNOOP_STRIPING 0 21231e17060SPaolo Bonzini 213*fbe5dac7SFrancisco Iglesias #define MIN_NUM_BUSSES 1 214*fbe5dac7SFrancisco Iglesias #define MAX_NUM_BUSSES 2 215*fbe5dac7SFrancisco Iglesias 21631e17060SPaolo Bonzini static inline int num_effective_busses(XilinxSPIPS *s) 21731e17060SPaolo Bonzini { 21831e17060SPaolo Bonzini return (s->regs[R_LQSPI_CFG] & LQSPI_CFG_SEP_BUS && 21931e17060SPaolo Bonzini s->regs[R_LQSPI_CFG] & LQSPI_CFG_TWO_MEM) ? s->num_busses : 1; 22031e17060SPaolo Bonzini } 22131e17060SPaolo Bonzini 222c95997a3SFrancisco Iglesias static void xilinx_spips_update_cs(XilinxSPIPS *s, int field) 223c4f08ffeSPeter Crosthwaite { 224c95997a3SFrancisco Iglesias int i; 22531e17060SPaolo Bonzini 22631e17060SPaolo Bonzini for (i = 0; i < s->num_cs; i++) { 227c95997a3SFrancisco Iglesias bool old_state = s->cs_lines_state[i]; 228c95997a3SFrancisco Iglesias bool new_state = field & (1 << i); 22931e17060SPaolo Bonzini 230c95997a3SFrancisco Iglesias if (old_state != new_state) { 231c95997a3SFrancisco Iglesias s->cs_lines_state[i] = new_state; 232ef06ca39SFrancisco Iglesias s->rx_discard = ARRAY_FIELD_EX32(s->regs, CMND, RX_DISCARD); 233c95997a3SFrancisco Iglesias DB_PRINT_L(1, "%sselecting slave %d\n", new_state ? "" : "de", i); 234ef06ca39SFrancisco Iglesias } 235c95997a3SFrancisco Iglesias qemu_set_irq(s->cs_lines[i], !new_state); 23631e17060SPaolo Bonzini } 237c95997a3SFrancisco Iglesias if (!(field & ((1 << s->num_cs) - 1))) { 23831e17060SPaolo Bonzini s->snoop_state = SNOOP_CHECKING; 239ef06ca39SFrancisco Iglesias s->cmd_dummies = 0; 240ef06ca39SFrancisco Iglesias s->link_state = 1; 241ef06ca39SFrancisco Iglesias s->link_state_next = 1; 242ef06ca39SFrancisco Iglesias s->link_state_next_when = 0; 2434a5b6fa8SPeter Crosthwaite DB_PRINT_L(1, "moving to snoop check state\n"); 24431e17060SPaolo Bonzini } 24531e17060SPaolo Bonzini } 24631e17060SPaolo Bonzini 247c95997a3SFrancisco Iglesias static void xlnx_zynqmp_qspips_update_cs_lines(XlnxZynqMPQSPIPS *s) 248c95997a3SFrancisco Iglesias { 249c95997a3SFrancisco Iglesias if (s->regs[R_GQSPI_GF_SNAPSHOT]) { 250c95997a3SFrancisco Iglesias int field = ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, CHIP_SELECT); 251c95997a3SFrancisco Iglesias xilinx_spips_update_cs(XILINX_SPIPS(s), field); 252c95997a3SFrancisco Iglesias } 253c95997a3SFrancisco Iglesias } 254c95997a3SFrancisco Iglesias 255c95997a3SFrancisco Iglesias static void xilinx_spips_update_cs_lines(XilinxSPIPS *s) 256c95997a3SFrancisco Iglesias { 257c95997a3SFrancisco Iglesias int field = ~((s->regs[R_CONFIG] & CS) >> CS_SHIFT); 258c95997a3SFrancisco Iglesias 259c95997a3SFrancisco Iglesias /* In dual parallel, mirror low CS to both */ 260c95997a3SFrancisco Iglesias if (num_effective_busses(s) == 2) { 261c95997a3SFrancisco Iglesias /* Single bit chip-select for qspi */ 262c95997a3SFrancisco Iglesias field &= 0x1; 263c95997a3SFrancisco Iglesias field |= field << 1; 264c95997a3SFrancisco Iglesias /* Dual stack U-Page */ 265c95997a3SFrancisco Iglesias } else if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_TWO_MEM && 266c95997a3SFrancisco Iglesias s->regs[R_LQSPI_STS] & LQSPI_CFG_U_PAGE) { 267c95997a3SFrancisco Iglesias /* Single bit chip-select for qspi */ 268c95997a3SFrancisco Iglesias field &= 0x1; 269c95997a3SFrancisco Iglesias /* change from CS0 to CS1 */ 270c95997a3SFrancisco Iglesias field <<= 1; 271c95997a3SFrancisco Iglesias } 272c95997a3SFrancisco Iglesias /* Auto CS */ 273c95997a3SFrancisco Iglesias if (!(s->regs[R_CONFIG] & MANUAL_CS) && 274c95997a3SFrancisco Iglesias fifo8_is_empty(&s->tx_fifo)) { 275c95997a3SFrancisco Iglesias field = 0; 276c95997a3SFrancisco Iglesias } 277c95997a3SFrancisco Iglesias xilinx_spips_update_cs(s, field); 278c95997a3SFrancisco Iglesias } 279c95997a3SFrancisco Iglesias 28031e17060SPaolo Bonzini static void xilinx_spips_update_ixr(XilinxSPIPS *s) 28131e17060SPaolo Bonzini { 282c95997a3SFrancisco Iglesias if (!(s->regs[R_LQSPI_CFG] & LQSPI_CFG_LQ_MODE)) { 283c95997a3SFrancisco Iglesias s->regs[R_INTR_STATUS] &= ~IXR_SELF_CLEAR; 28431e17060SPaolo Bonzini s->regs[R_INTR_STATUS] |= 28531e17060SPaolo Bonzini (fifo8_is_full(&s->rx_fifo) ? IXR_RX_FIFO_FULL : 0) | 286c95997a3SFrancisco Iglesias (s->rx_fifo.num >= s->regs[R_RX_THRES] ? 287c95997a3SFrancisco Iglesias IXR_RX_FIFO_NOT_EMPTY : 0) | 28831e17060SPaolo Bonzini (fifo8_is_full(&s->tx_fifo) ? IXR_TX_FIFO_FULL : 0) | 289c95997a3SFrancisco Iglesias (fifo8_is_empty(&s->tx_fifo) ? IXR_TX_FIFO_EMPTY : 0) | 29031e17060SPaolo Bonzini (s->tx_fifo.num < s->regs[R_TX_THRES] ? IXR_TX_FIFO_NOT_FULL : 0); 291c95997a3SFrancisco Iglesias } 29231e17060SPaolo Bonzini int new_irqline = !!(s->regs[R_INTR_MASK] & s->regs[R_INTR_STATUS] & 29331e17060SPaolo Bonzini IXR_ALL); 29431e17060SPaolo Bonzini if (new_irqline != s->irqline) { 29531e17060SPaolo Bonzini s->irqline = new_irqline; 29631e17060SPaolo Bonzini qemu_set_irq(s->irq, s->irqline); 29731e17060SPaolo Bonzini } 29831e17060SPaolo Bonzini } 29931e17060SPaolo Bonzini 300c95997a3SFrancisco Iglesias static void xlnx_zynqmp_qspips_update_ixr(XlnxZynqMPQSPIPS *s) 301c95997a3SFrancisco Iglesias { 302c95997a3SFrancisco Iglesias uint32_t gqspi_int; 303c95997a3SFrancisco Iglesias int new_irqline; 304c95997a3SFrancisco Iglesias 305c95997a3SFrancisco Iglesias s->regs[R_GQSPI_ISR] &= ~IXR_SELF_CLEAR; 306c95997a3SFrancisco Iglesias s->regs[R_GQSPI_ISR] |= 307c95997a3SFrancisco Iglesias (fifo32_is_empty(&s->fifo_g) ? IXR_GENERIC_FIFO_EMPTY : 0) | 308c95997a3SFrancisco Iglesias (fifo32_is_full(&s->fifo_g) ? IXR_GENERIC_FIFO_FULL : 0) | 309c95997a3SFrancisco Iglesias (s->fifo_g.fifo.num < s->regs[R_GQSPI_GFIFO_THRESH] ? 310c95997a3SFrancisco Iglesias IXR_GENERIC_FIFO_NOT_FULL : 0) | 311c95997a3SFrancisco Iglesias (fifo8_is_empty(&s->rx_fifo_g) ? IXR_RX_FIFO_EMPTY : 0) | 312c95997a3SFrancisco Iglesias (fifo8_is_full(&s->rx_fifo_g) ? IXR_RX_FIFO_FULL : 0) | 313c95997a3SFrancisco Iglesias (s->rx_fifo_g.num >= s->regs[R_GQSPI_RX_THRESH] ? 314c95997a3SFrancisco Iglesias IXR_RX_FIFO_NOT_EMPTY : 0) | 315c95997a3SFrancisco Iglesias (fifo8_is_empty(&s->tx_fifo_g) ? IXR_TX_FIFO_EMPTY : 0) | 316c95997a3SFrancisco Iglesias (fifo8_is_full(&s->tx_fifo_g) ? IXR_TX_FIFO_FULL : 0) | 317c95997a3SFrancisco Iglesias (s->tx_fifo_g.num < s->regs[R_GQSPI_TX_THRESH] ? 318c95997a3SFrancisco Iglesias IXR_TX_FIFO_NOT_FULL : 0); 319c95997a3SFrancisco Iglesias 320c95997a3SFrancisco Iglesias /* GQSPI Interrupt Trigger Status */ 321c95997a3SFrancisco Iglesias gqspi_int = (~s->regs[R_GQSPI_IMR]) & s->regs[R_GQSPI_ISR] & GQSPI_IXR_MASK; 322c95997a3SFrancisco Iglesias new_irqline = !!(gqspi_int & IXR_ALL); 323c95997a3SFrancisco Iglesias 324c95997a3SFrancisco Iglesias /* drive external interrupt pin */ 325c95997a3SFrancisco Iglesias if (new_irqline != s->gqspi_irqline) { 326c95997a3SFrancisco Iglesias s->gqspi_irqline = new_irqline; 327c95997a3SFrancisco Iglesias qemu_set_irq(XILINX_SPIPS(s)->irq, s->gqspi_irqline); 328c95997a3SFrancisco Iglesias } 329c95997a3SFrancisco Iglesias } 330c95997a3SFrancisco Iglesias 33131e17060SPaolo Bonzini static void xilinx_spips_reset(DeviceState *d) 33231e17060SPaolo Bonzini { 33331e17060SPaolo Bonzini XilinxSPIPS *s = XILINX_SPIPS(d); 33431e17060SPaolo Bonzini 335d3c348b6SAlistair Francis memset(s->regs, 0, sizeof(s->regs)); 33631e17060SPaolo Bonzini 33731e17060SPaolo Bonzini fifo8_reset(&s->rx_fifo); 33831e17060SPaolo Bonzini fifo8_reset(&s->rx_fifo); 33931e17060SPaolo Bonzini /* non zero resets */ 34031e17060SPaolo Bonzini s->regs[R_CONFIG] |= MODEFAIL_GEN_EN; 34131e17060SPaolo Bonzini s->regs[R_SLAVE_IDLE_COUNT] = 0xFF; 34231e17060SPaolo Bonzini s->regs[R_TX_THRES] = 1; 34331e17060SPaolo Bonzini s->regs[R_RX_THRES] = 1; 34431e17060SPaolo Bonzini /* FIXME: move magic number definition somewhere sensible */ 34531e17060SPaolo Bonzini s->regs[R_MOD_ID] = 0x01090106; 34631e17060SPaolo Bonzini s->regs[R_LQSPI_CFG] = R_LQSPI_CFG_RESET; 347ef06ca39SFrancisco Iglesias s->link_state = 1; 348ef06ca39SFrancisco Iglesias s->link_state_next = 1; 349ef06ca39SFrancisco Iglesias s->link_state_next_when = 0; 35031e17060SPaolo Bonzini s->snoop_state = SNOOP_CHECKING; 351ef06ca39SFrancisco Iglesias s->cmd_dummies = 0; 352275e28ccSFrancisco Iglesias s->man_start_com = false; 35331e17060SPaolo Bonzini xilinx_spips_update_ixr(s); 35431e17060SPaolo Bonzini xilinx_spips_update_cs_lines(s); 35531e17060SPaolo Bonzini } 35631e17060SPaolo Bonzini 357c95997a3SFrancisco Iglesias static void xlnx_zynqmp_qspips_reset(DeviceState *d) 358c95997a3SFrancisco Iglesias { 359c95997a3SFrancisco Iglesias XlnxZynqMPQSPIPS *s = XLNX_ZYNQMP_QSPIPS(d); 360c95997a3SFrancisco Iglesias 361c95997a3SFrancisco Iglesias xilinx_spips_reset(d); 362c95997a3SFrancisco Iglesias 363d3c348b6SAlistair Francis memset(s->regs, 0, sizeof(s->regs)); 364d3c348b6SAlistair Francis 365c95997a3SFrancisco Iglesias fifo8_reset(&s->rx_fifo_g); 366c95997a3SFrancisco Iglesias fifo8_reset(&s->rx_fifo_g); 367c95997a3SFrancisco Iglesias fifo32_reset(&s->fifo_g); 3684f0da466SAlistair Francis s->regs[R_INTR_STATUS] = R_INTR_STATUS_RESET; 3694f0da466SAlistair Francis s->regs[R_GPIO] = 1; 3704f0da466SAlistair Francis s->regs[R_LPBK_DLY_ADJ] = R_LPBK_DLY_ADJ_RESET; 3714f0da466SAlistair Francis s->regs[R_GQSPI_GFIFO_THRESH] = 0x10; 3724f0da466SAlistair Francis s->regs[R_MOD_ID] = 0x01090101; 3734f0da466SAlistair Francis s->regs[R_GQSPI_IMR] = R_GQSPI_IMR_RESET; 374c95997a3SFrancisco Iglesias s->regs[R_GQSPI_TX_THRESH] = 1; 375c95997a3SFrancisco Iglesias s->regs[R_GQSPI_RX_THRESH] = 1; 3764f0da466SAlistair Francis s->regs[R_GQSPI_GPIO] = 1; 3774f0da466SAlistair Francis s->regs[R_GQSPI_LPBK_DLY_ADJ] = R_GQSPI_LPBK_DLY_ADJ_RESET; 3784f0da466SAlistair Francis s->regs[R_GQSPI_MOD_ID] = R_GQSPI_MOD_ID_RESET; 3794f0da466SAlistair Francis s->regs[R_QSPIDMA_DST_CTRL] = R_QSPIDMA_DST_CTRL_RESET; 3804f0da466SAlistair Francis s->regs[R_QSPIDMA_DST_I_MASK] = R_QSPIDMA_DST_I_MASK_RESET; 3814f0da466SAlistair Francis s->regs[R_QSPIDMA_DST_CTRL2] = R_QSPIDMA_DST_CTRL2_RESET; 382c95997a3SFrancisco Iglesias s->man_start_com_g = false; 383c95997a3SFrancisco Iglesias s->gqspi_irqline = 0; 384c95997a3SFrancisco Iglesias xlnx_zynqmp_qspips_update_ixr(s); 385c95997a3SFrancisco Iglesias } 386c95997a3SFrancisco Iglesias 387c3725b85SFrancisco Iglesias /* N way (num) in place bit striper. Lay out row wise bits (MSB to LSB) 3889151da25SPeter Crosthwaite * column wise (from element 0 to N-1). num is the length of x, and dir 3899151da25SPeter Crosthwaite * reverses the direction of the transform. Best illustrated by example: 3909151da25SPeter Crosthwaite * Each digit in the below array is a single bit (num == 3): 3919151da25SPeter Crosthwaite * 392c3725b85SFrancisco Iglesias * {{ 76543210, } ----- stripe (dir == false) -----> {{ 741gdaFC, } 393c3725b85SFrancisco Iglesias * { hgfedcba, } { 630fcHEB, } 394c3725b85SFrancisco Iglesias * { HGFEDCBA, }} <---- upstripe (dir == true) ----- { 52hebGDA, }} 3959151da25SPeter Crosthwaite */ 3969151da25SPeter Crosthwaite 3979151da25SPeter Crosthwaite static inline void stripe8(uint8_t *x, int num, bool dir) 3989151da25SPeter Crosthwaite { 3999151da25SPeter Crosthwaite uint8_t r[num]; 4009151da25SPeter Crosthwaite memset(r, 0, sizeof(uint8_t) * num); 4019151da25SPeter Crosthwaite int idx[2] = {0, 0}; 402c3725b85SFrancisco Iglesias int bit[2] = {0, 7}; 4039151da25SPeter Crosthwaite int d = dir; 4049151da25SPeter Crosthwaite 4059151da25SPeter Crosthwaite for (idx[0] = 0; idx[0] < num; ++idx[0]) { 406c3725b85SFrancisco Iglesias for (bit[0] = 7; bit[0] >= 0; bit[0]--) { 407c3725b85SFrancisco Iglesias r[idx[!d]] |= x[idx[d]] & 1 << bit[d] ? 1 << bit[!d] : 0; 4089151da25SPeter Crosthwaite idx[1] = (idx[1] + 1) % num; 4099151da25SPeter Crosthwaite if (!idx[1]) { 410c3725b85SFrancisco Iglesias bit[1]--; 4119151da25SPeter Crosthwaite } 4129151da25SPeter Crosthwaite } 4139151da25SPeter Crosthwaite } 4149151da25SPeter Crosthwaite memcpy(x, r, sizeof(uint8_t) * num); 4159151da25SPeter Crosthwaite } 4169151da25SPeter Crosthwaite 417c95997a3SFrancisco Iglesias static void xlnx_zynqmp_qspips_flush_fifo_g(XlnxZynqMPQSPIPS *s) 418c95997a3SFrancisco Iglesias { 419c95997a3SFrancisco Iglesias while (s->regs[R_GQSPI_DATA_STS] || !fifo32_is_empty(&s->fifo_g)) { 420c95997a3SFrancisco Iglesias uint8_t tx_rx[2] = { 0 }; 421c95997a3SFrancisco Iglesias int num_stripes = 1; 422c95997a3SFrancisco Iglesias uint8_t busses; 423c95997a3SFrancisco Iglesias int i; 424c95997a3SFrancisco Iglesias 425c95997a3SFrancisco Iglesias if (!s->regs[R_GQSPI_DATA_STS]) { 426c95997a3SFrancisco Iglesias uint8_t imm; 427c95997a3SFrancisco Iglesias 428c95997a3SFrancisco Iglesias s->regs[R_GQSPI_GF_SNAPSHOT] = fifo32_pop(&s->fifo_g); 429c95997a3SFrancisco Iglesias DB_PRINT_L(0, "GQSPI command: %x\n", s->regs[R_GQSPI_GF_SNAPSHOT]); 430c95997a3SFrancisco Iglesias if (!s->regs[R_GQSPI_GF_SNAPSHOT]) { 431c95997a3SFrancisco Iglesias DB_PRINT_L(0, "Dummy GQSPI Delay Command Entry, Do nothing"); 432c95997a3SFrancisco Iglesias continue; 433c95997a3SFrancisco Iglesias } 434c95997a3SFrancisco Iglesias xlnx_zynqmp_qspips_update_cs_lines(s); 435c95997a3SFrancisco Iglesias 436c95997a3SFrancisco Iglesias imm = ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, IMMEDIATE_DATA); 437c95997a3SFrancisco Iglesias if (!ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, DATA_XFER)) { 438c95997a3SFrancisco Iglesias /* immedate transfer */ 439c95997a3SFrancisco Iglesias if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, TRANSMIT) || 440c95997a3SFrancisco Iglesias ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, RECIEVE)) { 441c95997a3SFrancisco Iglesias s->regs[R_GQSPI_DATA_STS] = 1; 442c95997a3SFrancisco Iglesias /* CS setup/hold - do nothing */ 443c95997a3SFrancisco Iglesias } else { 444c95997a3SFrancisco Iglesias s->regs[R_GQSPI_DATA_STS] = 0; 445c95997a3SFrancisco Iglesias } 446c95997a3SFrancisco Iglesias } else if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, EXPONENT)) { 447c95997a3SFrancisco Iglesias if (imm > 31) { 448c95997a3SFrancisco Iglesias qemu_log_mask(LOG_UNIMP, "QSPI exponential transfer too" 449c95997a3SFrancisco Iglesias " long - 2 ^ %" PRId8 " requested\n", imm); 450c95997a3SFrancisco Iglesias } 451c95997a3SFrancisco Iglesias s->regs[R_GQSPI_DATA_STS] = 1ul << imm; 452c95997a3SFrancisco Iglesias } else { 453c95997a3SFrancisco Iglesias s->regs[R_GQSPI_DATA_STS] = imm; 454c95997a3SFrancisco Iglesias } 455c95997a3SFrancisco Iglesias } 456c95997a3SFrancisco Iglesias /* Zero length transfer check */ 457c95997a3SFrancisco Iglesias if (!s->regs[R_GQSPI_DATA_STS]) { 458c95997a3SFrancisco Iglesias continue; 459c95997a3SFrancisco Iglesias } 460c95997a3SFrancisco Iglesias if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, RECIEVE) && 461c95997a3SFrancisco Iglesias fifo8_is_full(&s->rx_fifo_g)) { 462c95997a3SFrancisco Iglesias /* No space in RX fifo for transfer - try again later */ 463c95997a3SFrancisco Iglesias return; 464c95997a3SFrancisco Iglesias } 465c95997a3SFrancisco Iglesias if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, STRIPE) && 466c95997a3SFrancisco Iglesias (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, TRANSMIT) || 467c95997a3SFrancisco Iglesias ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, RECIEVE))) { 468c95997a3SFrancisco Iglesias num_stripes = 2; 469c95997a3SFrancisco Iglesias } 470c95997a3SFrancisco Iglesias if (!ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, DATA_XFER)) { 471c95997a3SFrancisco Iglesias tx_rx[0] = ARRAY_FIELD_EX32(s->regs, 472c95997a3SFrancisco Iglesias GQSPI_GF_SNAPSHOT, IMMEDIATE_DATA); 473c95997a3SFrancisco Iglesias } else if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, TRANSMIT)) { 474c95997a3SFrancisco Iglesias for (i = 0; i < num_stripes; ++i) { 475c95997a3SFrancisco Iglesias if (!fifo8_is_empty(&s->tx_fifo_g)) { 476c95997a3SFrancisco Iglesias tx_rx[i] = fifo8_pop(&s->tx_fifo_g); 477c95997a3SFrancisco Iglesias s->tx_fifo_g_align++; 478c95997a3SFrancisco Iglesias } else { 479c95997a3SFrancisco Iglesias return; 480c95997a3SFrancisco Iglesias } 481c95997a3SFrancisco Iglesias } 482c95997a3SFrancisco Iglesias } 483c95997a3SFrancisco Iglesias if (num_stripes == 1) { 484c95997a3SFrancisco Iglesias /* mirror */ 485c95997a3SFrancisco Iglesias tx_rx[1] = tx_rx[0]; 486c95997a3SFrancisco Iglesias } 487c95997a3SFrancisco Iglesias busses = ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, DATA_BUS_SELECT); 488c95997a3SFrancisco Iglesias for (i = 0; i < 2; ++i) { 489c95997a3SFrancisco Iglesias DB_PRINT_L(1, "bus %d tx = %02x\n", i, tx_rx[i]); 490c95997a3SFrancisco Iglesias tx_rx[i] = ssi_transfer(XILINX_SPIPS(s)->spi[i], tx_rx[i]); 491c95997a3SFrancisco Iglesias DB_PRINT_L(1, "bus %d rx = %02x\n", i, tx_rx[i]); 492c95997a3SFrancisco Iglesias } 493c95997a3SFrancisco Iglesias if (s->regs[R_GQSPI_DATA_STS] > 1 && 494c95997a3SFrancisco Iglesias busses == 0x3 && num_stripes == 2) { 495c95997a3SFrancisco Iglesias s->regs[R_GQSPI_DATA_STS] -= 2; 496c95997a3SFrancisco Iglesias } else if (s->regs[R_GQSPI_DATA_STS] > 0) { 497c95997a3SFrancisco Iglesias s->regs[R_GQSPI_DATA_STS]--; 498c95997a3SFrancisco Iglesias } 499c95997a3SFrancisco Iglesias if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, RECIEVE)) { 500c95997a3SFrancisco Iglesias for (i = 0; i < 2; ++i) { 501c95997a3SFrancisco Iglesias if (busses & (1 << i)) { 502c95997a3SFrancisco Iglesias DB_PRINT_L(1, "bus %d push_byte = %02x\n", i, tx_rx[i]); 503c95997a3SFrancisco Iglesias fifo8_push(&s->rx_fifo_g, tx_rx[i]); 504c95997a3SFrancisco Iglesias s->rx_fifo_g_align++; 505c95997a3SFrancisco Iglesias } 506c95997a3SFrancisco Iglesias } 507c95997a3SFrancisco Iglesias } 508c95997a3SFrancisco Iglesias if (!s->regs[R_GQSPI_DATA_STS]) { 509c95997a3SFrancisco Iglesias for (; s->tx_fifo_g_align % 4; s->tx_fifo_g_align++) { 510c95997a3SFrancisco Iglesias fifo8_pop(&s->tx_fifo_g); 511c95997a3SFrancisco Iglesias } 512c95997a3SFrancisco Iglesias for (; s->rx_fifo_g_align % 4; s->rx_fifo_g_align++) { 513c95997a3SFrancisco Iglesias fifo8_push(&s->rx_fifo_g, 0); 514c95997a3SFrancisco Iglesias } 515c95997a3SFrancisco Iglesias } 516c95997a3SFrancisco Iglesias } 517c95997a3SFrancisco Iglesias } 518c95997a3SFrancisco Iglesias 519ef06ca39SFrancisco Iglesias static int xilinx_spips_num_dummies(XilinxQSPIPS *qs, uint8_t command) 520ef06ca39SFrancisco Iglesias { 521ef06ca39SFrancisco Iglesias if (!qs) { 522ef06ca39SFrancisco Iglesias /* The SPI device is not a QSPI device */ 523ef06ca39SFrancisco Iglesias return -1; 524ef06ca39SFrancisco Iglesias } 525ef06ca39SFrancisco Iglesias 526ef06ca39SFrancisco Iglesias switch (command) { /* check for dummies */ 527ef06ca39SFrancisco Iglesias case READ: /* no dummy bytes/cycles */ 528ef06ca39SFrancisco Iglesias case PP: 529ef06ca39SFrancisco Iglesias case DPP: 530ef06ca39SFrancisco Iglesias case QPP: 531ef06ca39SFrancisco Iglesias case READ_4: 532ef06ca39SFrancisco Iglesias case PP_4: 533ef06ca39SFrancisco Iglesias case QPP_4: 534ef06ca39SFrancisco Iglesias return 0; 535ef06ca39SFrancisco Iglesias case FAST_READ: 536ef06ca39SFrancisco Iglesias case DOR: 537ef06ca39SFrancisco Iglesias case QOR: 538ef06ca39SFrancisco Iglesias case DOR_4: 539ef06ca39SFrancisco Iglesias case QOR_4: 540ef06ca39SFrancisco Iglesias return 1; 541ef06ca39SFrancisco Iglesias case DIOR: 542ef06ca39SFrancisco Iglesias case FAST_READ_4: 543ef06ca39SFrancisco Iglesias case DIOR_4: 544ef06ca39SFrancisco Iglesias return 2; 545ef06ca39SFrancisco Iglesias case QIOR: 546ef06ca39SFrancisco Iglesias case QIOR_4: 547ef06ca39SFrancisco Iglesias return 5; 548ef06ca39SFrancisco Iglesias default: 549ef06ca39SFrancisco Iglesias return -1; 550ef06ca39SFrancisco Iglesias } 551ef06ca39SFrancisco Iglesias } 552ef06ca39SFrancisco Iglesias 553ef06ca39SFrancisco Iglesias static inline uint8_t get_addr_length(XilinxSPIPS *s, uint8_t cmd) 554ef06ca39SFrancisco Iglesias { 555ef06ca39SFrancisco Iglesias switch (cmd) { 556ef06ca39SFrancisco Iglesias case PP_4: 557ef06ca39SFrancisco Iglesias case QPP_4: 558ef06ca39SFrancisco Iglesias case READ_4: 559ef06ca39SFrancisco Iglesias case QIOR_4: 560ef06ca39SFrancisco Iglesias case FAST_READ_4: 561ef06ca39SFrancisco Iglesias case DOR_4: 562ef06ca39SFrancisco Iglesias case QOR_4: 563ef06ca39SFrancisco Iglesias case DIOR_4: 564ef06ca39SFrancisco Iglesias return 4; 565ef06ca39SFrancisco Iglesias default: 566ef06ca39SFrancisco Iglesias return (s->regs[R_CMND] & R_CMND_EXT_ADD) ? 4 : 3; 567ef06ca39SFrancisco Iglesias } 568ef06ca39SFrancisco Iglesias } 569ef06ca39SFrancisco Iglesias 57031e17060SPaolo Bonzini static void xilinx_spips_flush_txfifo(XilinxSPIPS *s) 57131e17060SPaolo Bonzini { 5724a5b6fa8SPeter Crosthwaite int debug_level = 0; 573ef06ca39SFrancisco Iglesias XilinxQSPIPS *q = (XilinxQSPIPS *) object_dynamic_cast(OBJECT(s), 574ef06ca39SFrancisco Iglesias TYPE_XILINX_QSPIPS); 5754a5b6fa8SPeter Crosthwaite 57631e17060SPaolo Bonzini for (;;) { 57731e17060SPaolo Bonzini int i; 57831e17060SPaolo Bonzini uint8_t tx = 0; 579*fbe5dac7SFrancisco Iglesias uint8_t tx_rx[MAX_NUM_BUSSES] = { 0 }; 580ef06ca39SFrancisco Iglesias uint8_t dummy_cycles = 0; 581ef06ca39SFrancisco Iglesias uint8_t addr_length; 58231e17060SPaolo Bonzini 58331e17060SPaolo Bonzini if (fifo8_is_empty(&s->tx_fifo)) { 58431e17060SPaolo Bonzini xilinx_spips_update_ixr(s); 58531e17060SPaolo Bonzini return; 5869151da25SPeter Crosthwaite } else if (s->snoop_state == SNOOP_STRIPING) { 5879151da25SPeter Crosthwaite for (i = 0; i < num_effective_busses(s); ++i) { 5889151da25SPeter Crosthwaite tx_rx[i] = fifo8_pop(&s->tx_fifo); 5899151da25SPeter Crosthwaite } 5909151da25SPeter Crosthwaite stripe8(tx_rx, num_effective_busses(s), false); 591ef06ca39SFrancisco Iglesias } else if (s->snoop_state >= SNOOP_ADDR) { 59231e17060SPaolo Bonzini tx = fifo8_pop(&s->tx_fifo); 5939151da25SPeter Crosthwaite for (i = 0; i < num_effective_busses(s); ++i) { 5949151da25SPeter Crosthwaite tx_rx[i] = tx; 59531e17060SPaolo Bonzini } 596ef06ca39SFrancisco Iglesias } else { 597ef06ca39SFrancisco Iglesias /* Extract a dummy byte and generate dummy cycles according to the 598ef06ca39SFrancisco Iglesias * link state */ 599ef06ca39SFrancisco Iglesias tx = fifo8_pop(&s->tx_fifo); 600ef06ca39SFrancisco Iglesias dummy_cycles = 8 / s->link_state; 60131e17060SPaolo Bonzini } 6029151da25SPeter Crosthwaite 6039151da25SPeter Crosthwaite for (i = 0; i < num_effective_busses(s); ++i) { 604c3725b85SFrancisco Iglesias int bus = num_effective_busses(s) - 1 - i; 605ef06ca39SFrancisco Iglesias if (dummy_cycles) { 606ef06ca39SFrancisco Iglesias int d; 607ef06ca39SFrancisco Iglesias for (d = 0; d < dummy_cycles; ++d) { 608ef06ca39SFrancisco Iglesias tx_rx[0] = ssi_transfer(s->spi[bus], (uint32_t)tx_rx[0]); 609ef06ca39SFrancisco Iglesias } 610ef06ca39SFrancisco Iglesias } else { 6114a5b6fa8SPeter Crosthwaite DB_PRINT_L(debug_level, "tx = %02x\n", tx_rx[i]); 612c3725b85SFrancisco Iglesias tx_rx[i] = ssi_transfer(s->spi[bus], (uint32_t)tx_rx[i]); 6134a5b6fa8SPeter Crosthwaite DB_PRINT_L(debug_level, "rx = %02x\n", tx_rx[i]); 6149151da25SPeter Crosthwaite } 615ef06ca39SFrancisco Iglesias } 6169151da25SPeter Crosthwaite 617ef06ca39SFrancisco Iglesias if (s->regs[R_CMND] & R_CMND_RXFIFO_DRAIN) { 618ef06ca39SFrancisco Iglesias DB_PRINT_L(debug_level, "dircarding drained rx byte\n"); 619ef06ca39SFrancisco Iglesias /* Do nothing */ 620ef06ca39SFrancisco Iglesias } else if (s->rx_discard) { 621ef06ca39SFrancisco Iglesias DB_PRINT_L(debug_level, "dircarding discarded rx byte\n"); 622ef06ca39SFrancisco Iglesias s->rx_discard -= 8 / s->link_state; 623ef06ca39SFrancisco Iglesias } else if (fifo8_is_full(&s->rx_fifo)) { 62431e17060SPaolo Bonzini s->regs[R_INTR_STATUS] |= IXR_RX_FIFO_OVERFLOW; 6254a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "rx FIFO overflow"); 6269151da25SPeter Crosthwaite } else if (s->snoop_state == SNOOP_STRIPING) { 6279151da25SPeter Crosthwaite stripe8(tx_rx, num_effective_busses(s), true); 6289151da25SPeter Crosthwaite for (i = 0; i < num_effective_busses(s); ++i) { 6299151da25SPeter Crosthwaite fifo8_push(&s->rx_fifo, (uint8_t)tx_rx[i]); 630ef06ca39SFrancisco Iglesias DB_PRINT_L(debug_level, "pushing striped rx byte\n"); 6319151da25SPeter Crosthwaite } 63231e17060SPaolo Bonzini } else { 633ef06ca39SFrancisco Iglesias DB_PRINT_L(debug_level, "pushing unstriped rx byte\n"); 6349151da25SPeter Crosthwaite fifo8_push(&s->rx_fifo, (uint8_t)tx_rx[0]); 63531e17060SPaolo Bonzini } 63631e17060SPaolo Bonzini 637ef06ca39SFrancisco Iglesias if (s->link_state_next_when) { 638ef06ca39SFrancisco Iglesias s->link_state_next_when--; 639ef06ca39SFrancisco Iglesias if (!s->link_state_next_when) { 640ef06ca39SFrancisco Iglesias s->link_state = s->link_state_next; 641ef06ca39SFrancisco Iglesias } 642ef06ca39SFrancisco Iglesias } 643ef06ca39SFrancisco Iglesias 6444a5b6fa8SPeter Crosthwaite DB_PRINT_L(debug_level, "initial snoop state: %x\n", 6454a5b6fa8SPeter Crosthwaite (unsigned)s->snoop_state); 64631e17060SPaolo Bonzini switch (s->snoop_state) { 64731e17060SPaolo Bonzini case (SNOOP_CHECKING): 648ef06ca39SFrancisco Iglesias /* Store the count of dummy bytes in the txfifo */ 649ef06ca39SFrancisco Iglesias s->cmd_dummies = xilinx_spips_num_dummies(q, tx); 650ef06ca39SFrancisco Iglesias addr_length = get_addr_length(s, tx); 651ef06ca39SFrancisco Iglesias if (s->cmd_dummies < 0) { 65231e17060SPaolo Bonzini s->snoop_state = SNOOP_NONE; 653ef06ca39SFrancisco Iglesias } else { 654ef06ca39SFrancisco Iglesias s->snoop_state = SNOOP_ADDR + addr_length - 1; 655ef06ca39SFrancisco Iglesias } 656ef06ca39SFrancisco Iglesias switch (tx) { 657ef06ca39SFrancisco Iglesias case DPP: 658ef06ca39SFrancisco Iglesias case DOR: 659ef06ca39SFrancisco Iglesias case DOR_4: 660ef06ca39SFrancisco Iglesias s->link_state_next = 2; 661ef06ca39SFrancisco Iglesias s->link_state_next_when = addr_length + s->cmd_dummies; 662ef06ca39SFrancisco Iglesias break; 663ef06ca39SFrancisco Iglesias case QPP: 664ef06ca39SFrancisco Iglesias case QPP_4: 665ef06ca39SFrancisco Iglesias case QOR: 666ef06ca39SFrancisco Iglesias case QOR_4: 667ef06ca39SFrancisco Iglesias s->link_state_next = 4; 668ef06ca39SFrancisco Iglesias s->link_state_next_when = addr_length + s->cmd_dummies; 669ef06ca39SFrancisco Iglesias break; 670ef06ca39SFrancisco Iglesias case DIOR: 671ef06ca39SFrancisco Iglesias case DIOR_4: 672ef06ca39SFrancisco Iglesias s->link_state = 2; 673ef06ca39SFrancisco Iglesias break; 674ef06ca39SFrancisco Iglesias case QIOR: 675ef06ca39SFrancisco Iglesias case QIOR_4: 676ef06ca39SFrancisco Iglesias s->link_state = 4; 677ef06ca39SFrancisco Iglesias break; 678ef06ca39SFrancisco Iglesias } 679ef06ca39SFrancisco Iglesias break; 680ef06ca39SFrancisco Iglesias case (SNOOP_ADDR): 681ef06ca39SFrancisco Iglesias /* Address has been transmitted, transmit dummy cycles now if 682ef06ca39SFrancisco Iglesias * needed */ 683ef06ca39SFrancisco Iglesias if (s->cmd_dummies < 0) { 684ef06ca39SFrancisco Iglesias s->snoop_state = SNOOP_NONE; 685ef06ca39SFrancisco Iglesias } else { 686ef06ca39SFrancisco Iglesias s->snoop_state = s->cmd_dummies; 68731e17060SPaolo Bonzini } 68831e17060SPaolo Bonzini break; 68931e17060SPaolo Bonzini case (SNOOP_STRIPING): 69031e17060SPaolo Bonzini case (SNOOP_NONE): 6914a5b6fa8SPeter Crosthwaite /* Once we hit the boring stuff - squelch debug noise */ 6924a5b6fa8SPeter Crosthwaite if (!debug_level) { 6934a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "squelching debug info ....\n"); 6944a5b6fa8SPeter Crosthwaite debug_level = 1; 6954a5b6fa8SPeter Crosthwaite } 69631e17060SPaolo Bonzini break; 69731e17060SPaolo Bonzini default: 69831e17060SPaolo Bonzini s->snoop_state--; 69931e17060SPaolo Bonzini } 7004a5b6fa8SPeter Crosthwaite DB_PRINT_L(debug_level, "final snoop state: %x\n", 7014a5b6fa8SPeter Crosthwaite (unsigned)s->snoop_state); 70231e17060SPaolo Bonzini } 70331e17060SPaolo Bonzini } 70431e17060SPaolo Bonzini 7052fdd171eSFrancisco Iglesias static inline void tx_data_bytes(Fifo8 *fifo, uint32_t value, int num, bool be) 7062fdd171eSFrancisco Iglesias { 7072fdd171eSFrancisco Iglesias int i; 7082fdd171eSFrancisco Iglesias for (i = 0; i < num && !fifo8_is_full(fifo); ++i) { 7092fdd171eSFrancisco Iglesias if (be) { 7102fdd171eSFrancisco Iglesias fifo8_push(fifo, (uint8_t)(value >> 24)); 7112fdd171eSFrancisco Iglesias value <<= 8; 7122fdd171eSFrancisco Iglesias } else { 7132fdd171eSFrancisco Iglesias fifo8_push(fifo, (uint8_t)value); 7142fdd171eSFrancisco Iglesias value >>= 8; 7152fdd171eSFrancisco Iglesias } 7162fdd171eSFrancisco Iglesias } 7172fdd171eSFrancisco Iglesias } 7182fdd171eSFrancisco Iglesias 719275e28ccSFrancisco Iglesias static void xilinx_spips_check_zero_pump(XilinxSPIPS *s) 720275e28ccSFrancisco Iglesias { 721275e28ccSFrancisco Iglesias if (!s->regs[R_TRANSFER_SIZE]) { 722275e28ccSFrancisco Iglesias return; 723275e28ccSFrancisco Iglesias } 724275e28ccSFrancisco Iglesias if (!fifo8_is_empty(&s->tx_fifo) && s->regs[R_CMND] & R_CMND_PUSH_WAIT) { 725275e28ccSFrancisco Iglesias return; 726275e28ccSFrancisco Iglesias } 727275e28ccSFrancisco Iglesias /* 728275e28ccSFrancisco Iglesias * The zero pump must never fill tx fifo such that rx overflow is 729275e28ccSFrancisco Iglesias * possible 730275e28ccSFrancisco Iglesias */ 731275e28ccSFrancisco Iglesias while (s->regs[R_TRANSFER_SIZE] && 732275e28ccSFrancisco Iglesias s->rx_fifo.num + s->tx_fifo.num < RXFF_A_Q - 3) { 733275e28ccSFrancisco Iglesias /* endianess just doesn't matter when zero pumping */ 734275e28ccSFrancisco Iglesias tx_data_bytes(&s->tx_fifo, 0, 4, false); 735275e28ccSFrancisco Iglesias s->regs[R_TRANSFER_SIZE] &= ~0x03ull; 736275e28ccSFrancisco Iglesias s->regs[R_TRANSFER_SIZE] -= 4; 737275e28ccSFrancisco Iglesias } 738275e28ccSFrancisco Iglesias } 739275e28ccSFrancisco Iglesias 740275e28ccSFrancisco Iglesias static void xilinx_spips_check_flush(XilinxSPIPS *s) 741275e28ccSFrancisco Iglesias { 742275e28ccSFrancisco Iglesias if (s->man_start_com || 743275e28ccSFrancisco Iglesias (!fifo8_is_empty(&s->tx_fifo) && 744275e28ccSFrancisco Iglesias !(s->regs[R_CONFIG] & MAN_START_EN))) { 745275e28ccSFrancisco Iglesias xilinx_spips_check_zero_pump(s); 746275e28ccSFrancisco Iglesias xilinx_spips_flush_txfifo(s); 747275e28ccSFrancisco Iglesias } 748275e28ccSFrancisco Iglesias if (fifo8_is_empty(&s->tx_fifo) && !s->regs[R_TRANSFER_SIZE]) { 749275e28ccSFrancisco Iglesias s->man_start_com = false; 750275e28ccSFrancisco Iglesias } 751275e28ccSFrancisco Iglesias xilinx_spips_update_ixr(s); 752275e28ccSFrancisco Iglesias } 753275e28ccSFrancisco Iglesias 754c95997a3SFrancisco Iglesias static void xlnx_zynqmp_qspips_check_flush(XlnxZynqMPQSPIPS *s) 755c95997a3SFrancisco Iglesias { 756c95997a3SFrancisco Iglesias bool gqspi_has_work = s->regs[R_GQSPI_DATA_STS] || 757c95997a3SFrancisco Iglesias !fifo32_is_empty(&s->fifo_g); 758c95997a3SFrancisco Iglesias 759c95997a3SFrancisco Iglesias if (ARRAY_FIELD_EX32(s->regs, GQSPI_SELECT, GENERIC_QSPI_EN)) { 760c95997a3SFrancisco Iglesias if (s->man_start_com_g || (gqspi_has_work && 761c95997a3SFrancisco Iglesias !ARRAY_FIELD_EX32(s->regs, GQSPI_CNFG, GEN_FIFO_START_MODE))) { 762c95997a3SFrancisco Iglesias xlnx_zynqmp_qspips_flush_fifo_g(s); 763c95997a3SFrancisco Iglesias } 764c95997a3SFrancisco Iglesias } else { 765c95997a3SFrancisco Iglesias xilinx_spips_check_flush(XILINX_SPIPS(s)); 766c95997a3SFrancisco Iglesias } 767c95997a3SFrancisco Iglesias if (!gqspi_has_work) { 768c95997a3SFrancisco Iglesias s->man_start_com_g = false; 769c95997a3SFrancisco Iglesias } 770c95997a3SFrancisco Iglesias xlnx_zynqmp_qspips_update_ixr(s); 771c95997a3SFrancisco Iglesias } 772c95997a3SFrancisco Iglesias 7732fdd171eSFrancisco Iglesias static inline int rx_data_bytes(Fifo8 *fifo, uint8_t *value, int max) 77431e17060SPaolo Bonzini { 77531e17060SPaolo Bonzini int i; 77631e17060SPaolo Bonzini 7772fdd171eSFrancisco Iglesias for (i = 0; i < max && !fifo8_is_empty(fifo); ++i) { 7782fdd171eSFrancisco Iglesias value[i] = fifo8_pop(fifo); 77931e17060SPaolo Bonzini } 7802fdd171eSFrancisco Iglesias return max - i; 78131e17060SPaolo Bonzini } 78231e17060SPaolo Bonzini 783c95997a3SFrancisco Iglesias static const void *pop_buf(Fifo8 *fifo, uint32_t max, uint32_t *num) 784c95997a3SFrancisco Iglesias { 785c95997a3SFrancisco Iglesias void *ret; 786c95997a3SFrancisco Iglesias 787c95997a3SFrancisco Iglesias if (max == 0 || max > fifo->num) { 788c95997a3SFrancisco Iglesias abort(); 789c95997a3SFrancisco Iglesias } 790c95997a3SFrancisco Iglesias *num = MIN(fifo->capacity - fifo->head, max); 791c95997a3SFrancisco Iglesias ret = &fifo->data[fifo->head]; 792c95997a3SFrancisco Iglesias fifo->head += *num; 793c95997a3SFrancisco Iglesias fifo->head %= fifo->capacity; 794c95997a3SFrancisco Iglesias fifo->num -= *num; 795c95997a3SFrancisco Iglesias return ret; 796c95997a3SFrancisco Iglesias } 797c95997a3SFrancisco Iglesias 798c95997a3SFrancisco Iglesias static void xlnx_zynqmp_qspips_notify(void *opaque) 799c95997a3SFrancisco Iglesias { 800c95997a3SFrancisco Iglesias XlnxZynqMPQSPIPS *rq = XLNX_ZYNQMP_QSPIPS(opaque); 801c95997a3SFrancisco Iglesias XilinxSPIPS *s = XILINX_SPIPS(rq); 802c95997a3SFrancisco Iglesias Fifo8 *recv_fifo; 803c95997a3SFrancisco Iglesias 804c95997a3SFrancisco Iglesias if (ARRAY_FIELD_EX32(rq->regs, GQSPI_SELECT, GENERIC_QSPI_EN)) { 805c95997a3SFrancisco Iglesias if (!(ARRAY_FIELD_EX32(rq->regs, GQSPI_CNFG, MODE_EN) == 2)) { 806c95997a3SFrancisco Iglesias return; 807c95997a3SFrancisco Iglesias } 808c95997a3SFrancisco Iglesias recv_fifo = &rq->rx_fifo_g; 809c95997a3SFrancisco Iglesias } else { 810c95997a3SFrancisco Iglesias if (!(s->regs[R_CMND] & R_CMND_DMA_EN)) { 811c95997a3SFrancisco Iglesias return; 812c95997a3SFrancisco Iglesias } 813c95997a3SFrancisco Iglesias recv_fifo = &s->rx_fifo; 814c95997a3SFrancisco Iglesias } 815c95997a3SFrancisco Iglesias while (recv_fifo->num >= 4 816c95997a3SFrancisco Iglesias && stream_can_push(rq->dma, xlnx_zynqmp_qspips_notify, rq)) 817c95997a3SFrancisco Iglesias { 818c95997a3SFrancisco Iglesias size_t ret; 819c95997a3SFrancisco Iglesias uint32_t num; 820c95997a3SFrancisco Iglesias const void *rxd = pop_buf(recv_fifo, 4, &num); 821c95997a3SFrancisco Iglesias 822c95997a3SFrancisco Iglesias memcpy(rq->dma_buf, rxd, num); 823c95997a3SFrancisco Iglesias 824c95997a3SFrancisco Iglesias ret = stream_push(rq->dma, rq->dma_buf, 4); 825c95997a3SFrancisco Iglesias assert(ret == 4); 826c95997a3SFrancisco Iglesias xlnx_zynqmp_qspips_check_flush(rq); 827c95997a3SFrancisco Iglesias } 828c95997a3SFrancisco Iglesias } 829c95997a3SFrancisco Iglesias 83031e17060SPaolo Bonzini static uint64_t xilinx_spips_read(void *opaque, hwaddr addr, 83131e17060SPaolo Bonzini unsigned size) 83231e17060SPaolo Bonzini { 83331e17060SPaolo Bonzini XilinxSPIPS *s = opaque; 83431e17060SPaolo Bonzini uint32_t mask = ~0; 83531e17060SPaolo Bonzini uint32_t ret; 836b0b7ae62SPeter Crosthwaite uint8_t rx_buf[4]; 8372fdd171eSFrancisco Iglesias int shortfall; 83831e17060SPaolo Bonzini 83931e17060SPaolo Bonzini addr >>= 2; 84031e17060SPaolo Bonzini switch (addr) { 84131e17060SPaolo Bonzini case R_CONFIG: 8422133a5f6SPeter Crosthwaite mask = ~(R_CONFIG_RSVD | MAN_START_COM); 84331e17060SPaolo Bonzini break; 84431e17060SPaolo Bonzini case R_INTR_STATUS: 84587920b44SPeter Crosthwaite ret = s->regs[addr] & IXR_ALL; 84687920b44SPeter Crosthwaite s->regs[addr] = 0; 8474a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret); 8482e1cf2c9SFrancisco Iglesias xilinx_spips_update_ixr(s); 84987920b44SPeter Crosthwaite return ret; 85031e17060SPaolo Bonzini case R_INTR_MASK: 85131e17060SPaolo Bonzini mask = IXR_ALL; 85231e17060SPaolo Bonzini break; 85331e17060SPaolo Bonzini case R_EN: 85431e17060SPaolo Bonzini mask = 0x1; 85531e17060SPaolo Bonzini break; 85631e17060SPaolo Bonzini case R_SLAVE_IDLE_COUNT: 85731e17060SPaolo Bonzini mask = 0xFF; 85831e17060SPaolo Bonzini break; 85931e17060SPaolo Bonzini case R_MOD_ID: 86031e17060SPaolo Bonzini mask = 0x01FFFFFF; 86131e17060SPaolo Bonzini break; 86231e17060SPaolo Bonzini case R_INTR_EN: 86331e17060SPaolo Bonzini case R_INTR_DIS: 86431e17060SPaolo Bonzini case R_TX_DATA: 86531e17060SPaolo Bonzini mask = 0; 86631e17060SPaolo Bonzini break; 86731e17060SPaolo Bonzini case R_RX_DATA: 868b0b7ae62SPeter Crosthwaite memset(rx_buf, 0, sizeof(rx_buf)); 8692fdd171eSFrancisco Iglesias shortfall = rx_data_bytes(&s->rx_fifo, rx_buf, s->num_txrx_bytes); 8702fdd171eSFrancisco Iglesias ret = s->regs[R_CONFIG] & R_CONFIG_ENDIAN ? 8712fdd171eSFrancisco Iglesias cpu_to_be32(*(uint32_t *)rx_buf) : 8722fdd171eSFrancisco Iglesias cpu_to_le32(*(uint32_t *)rx_buf); 8732fdd171eSFrancisco Iglesias if (!(s->regs[R_CONFIG] & R_CONFIG_ENDIAN)) { 8742fdd171eSFrancisco Iglesias ret <<= 8 * shortfall; 8752fdd171eSFrancisco Iglesias } 8764a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret); 877c95997a3SFrancisco Iglesias xilinx_spips_check_flush(s); 87831e17060SPaolo Bonzini xilinx_spips_update_ixr(s); 87931e17060SPaolo Bonzini return ret; 88031e17060SPaolo Bonzini } 8814a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4, 8824a5b6fa8SPeter Crosthwaite s->regs[addr] & mask); 88331e17060SPaolo Bonzini return s->regs[addr] & mask; 88431e17060SPaolo Bonzini 88531e17060SPaolo Bonzini } 88631e17060SPaolo Bonzini 887c95997a3SFrancisco Iglesias static uint64_t xlnx_zynqmp_qspips_read(void *opaque, 888c95997a3SFrancisco Iglesias hwaddr addr, unsigned size) 889c95997a3SFrancisco Iglesias { 890c95997a3SFrancisco Iglesias XlnxZynqMPQSPIPS *s = XLNX_ZYNQMP_QSPIPS(opaque); 891c95997a3SFrancisco Iglesias uint32_t reg = addr / 4; 892c95997a3SFrancisco Iglesias uint32_t ret; 893c95997a3SFrancisco Iglesias uint8_t rx_buf[4]; 894c95997a3SFrancisco Iglesias int shortfall; 895c95997a3SFrancisco Iglesias 896c95997a3SFrancisco Iglesias if (reg <= R_MOD_ID) { 897c95997a3SFrancisco Iglesias return xilinx_spips_read(opaque, addr, size); 898c95997a3SFrancisco Iglesias } else { 899c95997a3SFrancisco Iglesias switch (reg) { 900c95997a3SFrancisco Iglesias case R_GQSPI_RXD: 901c95997a3SFrancisco Iglesias if (fifo8_is_empty(&s->rx_fifo_g)) { 902c95997a3SFrancisco Iglesias qemu_log_mask(LOG_GUEST_ERROR, 903c95997a3SFrancisco Iglesias "Read from empty GQSPI RX FIFO\n"); 904c95997a3SFrancisco Iglesias return 0; 905c95997a3SFrancisco Iglesias } 906c95997a3SFrancisco Iglesias memset(rx_buf, 0, sizeof(rx_buf)); 907c95997a3SFrancisco Iglesias shortfall = rx_data_bytes(&s->rx_fifo_g, rx_buf, 908c95997a3SFrancisco Iglesias XILINX_SPIPS(s)->num_txrx_bytes); 909c95997a3SFrancisco Iglesias ret = ARRAY_FIELD_EX32(s->regs, GQSPI_CNFG, ENDIAN) ? 910c95997a3SFrancisco Iglesias cpu_to_be32(*(uint32_t *)rx_buf) : 911c95997a3SFrancisco Iglesias cpu_to_le32(*(uint32_t *)rx_buf); 912c95997a3SFrancisco Iglesias if (!ARRAY_FIELD_EX32(s->regs, GQSPI_CNFG, ENDIAN)) { 913c95997a3SFrancisco Iglesias ret <<= 8 * shortfall; 914c95997a3SFrancisco Iglesias } 915c95997a3SFrancisco Iglesias xlnx_zynqmp_qspips_check_flush(s); 916c95997a3SFrancisco Iglesias xlnx_zynqmp_qspips_update_ixr(s); 917c95997a3SFrancisco Iglesias return ret; 918c95997a3SFrancisco Iglesias default: 919c95997a3SFrancisco Iglesias return s->regs[reg]; 920c95997a3SFrancisco Iglesias } 921c95997a3SFrancisco Iglesias } 922c95997a3SFrancisco Iglesias } 923c95997a3SFrancisco Iglesias 92431e17060SPaolo Bonzini static void xilinx_spips_write(void *opaque, hwaddr addr, 92531e17060SPaolo Bonzini uint64_t value, unsigned size) 92631e17060SPaolo Bonzini { 92731e17060SPaolo Bonzini int mask = ~0; 92831e17060SPaolo Bonzini XilinxSPIPS *s = opaque; 92931e17060SPaolo Bonzini 9304a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr, (unsigned)value); 93131e17060SPaolo Bonzini addr >>= 2; 93231e17060SPaolo Bonzini switch (addr) { 93331e17060SPaolo Bonzini case R_CONFIG: 9342133a5f6SPeter Crosthwaite mask = ~(R_CONFIG_RSVD | MAN_START_COM); 935275e28ccSFrancisco Iglesias if ((value & MAN_START_COM) && (s->regs[R_CONFIG] & MAN_START_EN)) { 936275e28ccSFrancisco Iglesias s->man_start_com = true; 93731e17060SPaolo Bonzini } 93831e17060SPaolo Bonzini break; 93931e17060SPaolo Bonzini case R_INTR_STATUS: 94031e17060SPaolo Bonzini mask = IXR_ALL; 94131e17060SPaolo Bonzini s->regs[R_INTR_STATUS] &= ~(mask & value); 94231e17060SPaolo Bonzini goto no_reg_update; 94331e17060SPaolo Bonzini case R_INTR_DIS: 94431e17060SPaolo Bonzini mask = IXR_ALL; 94531e17060SPaolo Bonzini s->regs[R_INTR_MASK] &= ~(mask & value); 94631e17060SPaolo Bonzini goto no_reg_update; 94731e17060SPaolo Bonzini case R_INTR_EN: 94831e17060SPaolo Bonzini mask = IXR_ALL; 94931e17060SPaolo Bonzini s->regs[R_INTR_MASK] |= mask & value; 95031e17060SPaolo Bonzini goto no_reg_update; 95131e17060SPaolo Bonzini case R_EN: 95231e17060SPaolo Bonzini mask = 0x1; 95331e17060SPaolo Bonzini break; 95431e17060SPaolo Bonzini case R_SLAVE_IDLE_COUNT: 95531e17060SPaolo Bonzini mask = 0xFF; 95631e17060SPaolo Bonzini break; 95731e17060SPaolo Bonzini case R_RX_DATA: 95831e17060SPaolo Bonzini case R_INTR_MASK: 95931e17060SPaolo Bonzini case R_MOD_ID: 96031e17060SPaolo Bonzini mask = 0; 96131e17060SPaolo Bonzini break; 96231e17060SPaolo Bonzini case R_TX_DATA: 9632fdd171eSFrancisco Iglesias tx_data_bytes(&s->tx_fifo, (uint32_t)value, s->num_txrx_bytes, 9642fdd171eSFrancisco Iglesias s->regs[R_CONFIG] & R_CONFIG_ENDIAN); 96531e17060SPaolo Bonzini goto no_reg_update; 96631e17060SPaolo Bonzini case R_TXD1: 9672fdd171eSFrancisco Iglesias tx_data_bytes(&s->tx_fifo, (uint32_t)value, 1, 9682fdd171eSFrancisco Iglesias s->regs[R_CONFIG] & R_CONFIG_ENDIAN); 96931e17060SPaolo Bonzini goto no_reg_update; 97031e17060SPaolo Bonzini case R_TXD2: 9712fdd171eSFrancisco Iglesias tx_data_bytes(&s->tx_fifo, (uint32_t)value, 2, 9722fdd171eSFrancisco Iglesias s->regs[R_CONFIG] & R_CONFIG_ENDIAN); 97331e17060SPaolo Bonzini goto no_reg_update; 97431e17060SPaolo Bonzini case R_TXD3: 9752fdd171eSFrancisco Iglesias tx_data_bytes(&s->tx_fifo, (uint32_t)value, 3, 9762fdd171eSFrancisco Iglesias s->regs[R_CONFIG] & R_CONFIG_ENDIAN); 97731e17060SPaolo Bonzini goto no_reg_update; 97831e17060SPaolo Bonzini } 97931e17060SPaolo Bonzini s->regs[addr] = (s->regs[addr] & ~mask) | (value & mask); 98031e17060SPaolo Bonzini no_reg_update: 981c4f08ffeSPeter Crosthwaite xilinx_spips_update_cs_lines(s); 982275e28ccSFrancisco Iglesias xilinx_spips_check_flush(s); 98331e17060SPaolo Bonzini xilinx_spips_update_cs_lines(s); 984c4f08ffeSPeter Crosthwaite xilinx_spips_update_ixr(s); 98531e17060SPaolo Bonzini } 98631e17060SPaolo Bonzini 98731e17060SPaolo Bonzini static const MemoryRegionOps spips_ops = { 98831e17060SPaolo Bonzini .read = xilinx_spips_read, 98931e17060SPaolo Bonzini .write = xilinx_spips_write, 99031e17060SPaolo Bonzini .endianness = DEVICE_LITTLE_ENDIAN, 99131e17060SPaolo Bonzini }; 99231e17060SPaolo Bonzini 993252b99baSKONRAD Frederic static void xilinx_qspips_invalidate_mmio_ptr(XilinxQSPIPS *q) 994252b99baSKONRAD Frederic { 995252b99baSKONRAD Frederic XilinxSPIPS *s = &q->parent_obj; 996252b99baSKONRAD Frederic 99783c3a1f6SKONRAD Frederic if ((q->mmio_execution_enabled) && (q->lqspi_cached_addr != ~0ULL)) { 998252b99baSKONRAD Frederic /* Invalidate the current mapped mmio */ 999252b99baSKONRAD Frederic memory_region_invalidate_mmio_ptr(&s->mmlqspi, q->lqspi_cached_addr, 1000252b99baSKONRAD Frederic LQSPI_CACHE_SIZE); 1001252b99baSKONRAD Frederic } 100283c3a1f6SKONRAD Frederic 100383c3a1f6SKONRAD Frederic q->lqspi_cached_addr = ~0ULL; 1004252b99baSKONRAD Frederic } 1005252b99baSKONRAD Frederic 1006b5cd9143SPeter Crosthwaite static void xilinx_qspips_write(void *opaque, hwaddr addr, 1007b5cd9143SPeter Crosthwaite uint64_t value, unsigned size) 1008b5cd9143SPeter Crosthwaite { 1009b5cd9143SPeter Crosthwaite XilinxQSPIPS *q = XILINX_QSPIPS(opaque); 1010ef06ca39SFrancisco Iglesias XilinxSPIPS *s = XILINX_SPIPS(opaque); 1011b5cd9143SPeter Crosthwaite 1012b5cd9143SPeter Crosthwaite xilinx_spips_write(opaque, addr, value, size); 1013b5cd9143SPeter Crosthwaite addr >>= 2; 1014b5cd9143SPeter Crosthwaite 1015b5cd9143SPeter Crosthwaite if (addr == R_LQSPI_CFG) { 1016252b99baSKONRAD Frederic xilinx_qspips_invalidate_mmio_ptr(q); 1017b5cd9143SPeter Crosthwaite } 1018ef06ca39SFrancisco Iglesias if (s->regs[R_CMND] & R_CMND_RXFIFO_DRAIN) { 1019ef06ca39SFrancisco Iglesias fifo8_reset(&s->rx_fifo); 1020ef06ca39SFrancisco Iglesias } 1021b5cd9143SPeter Crosthwaite } 1022b5cd9143SPeter Crosthwaite 1023c95997a3SFrancisco Iglesias static void xlnx_zynqmp_qspips_write(void *opaque, hwaddr addr, 1024c95997a3SFrancisco Iglesias uint64_t value, unsigned size) 1025c95997a3SFrancisco Iglesias { 1026c95997a3SFrancisco Iglesias XlnxZynqMPQSPIPS *s = XLNX_ZYNQMP_QSPIPS(opaque); 1027c95997a3SFrancisco Iglesias uint32_t reg = addr / 4; 1028c95997a3SFrancisco Iglesias 1029c95997a3SFrancisco Iglesias if (reg <= R_MOD_ID) { 1030c95997a3SFrancisco Iglesias xilinx_qspips_write(opaque, addr, value, size); 1031c95997a3SFrancisco Iglesias } else { 1032c95997a3SFrancisco Iglesias switch (reg) { 1033c95997a3SFrancisco Iglesias case R_GQSPI_CNFG: 1034c95997a3SFrancisco Iglesias if (FIELD_EX32(value, GQSPI_CNFG, GEN_FIFO_START) && 1035c95997a3SFrancisco Iglesias ARRAY_FIELD_EX32(s->regs, GQSPI_CNFG, GEN_FIFO_START_MODE)) { 1036c95997a3SFrancisco Iglesias s->man_start_com_g = true; 1037c95997a3SFrancisco Iglesias } 1038c95997a3SFrancisco Iglesias s->regs[reg] = value & ~(R_GQSPI_CNFG_GEN_FIFO_START_MASK); 1039c95997a3SFrancisco Iglesias break; 1040c95997a3SFrancisco Iglesias case R_GQSPI_GEN_FIFO: 1041c95997a3SFrancisco Iglesias if (!fifo32_is_full(&s->fifo_g)) { 1042c95997a3SFrancisco Iglesias fifo32_push(&s->fifo_g, value); 1043c95997a3SFrancisco Iglesias } 1044c95997a3SFrancisco Iglesias break; 1045c95997a3SFrancisco Iglesias case R_GQSPI_TXD: 1046c95997a3SFrancisco Iglesias tx_data_bytes(&s->tx_fifo_g, (uint32_t)value, 4, 1047c95997a3SFrancisco Iglesias ARRAY_FIELD_EX32(s->regs, GQSPI_CNFG, ENDIAN)); 1048c95997a3SFrancisco Iglesias break; 1049c95997a3SFrancisco Iglesias case R_GQSPI_FIFO_CTRL: 1050c95997a3SFrancisco Iglesias if (FIELD_EX32(value, GQSPI_FIFO_CTRL, GENERIC_FIFO_RESET)) { 1051c95997a3SFrancisco Iglesias fifo32_reset(&s->fifo_g); 1052c95997a3SFrancisco Iglesias } 1053c95997a3SFrancisco Iglesias if (FIELD_EX32(value, GQSPI_FIFO_CTRL, TX_FIFO_RESET)) { 1054c95997a3SFrancisco Iglesias fifo8_reset(&s->tx_fifo_g); 1055c95997a3SFrancisco Iglesias } 1056c95997a3SFrancisco Iglesias if (FIELD_EX32(value, GQSPI_FIFO_CTRL, RX_FIFO_RESET)) { 1057c95997a3SFrancisco Iglesias fifo8_reset(&s->rx_fifo_g); 1058c95997a3SFrancisco Iglesias } 1059c95997a3SFrancisco Iglesias break; 1060c95997a3SFrancisco Iglesias case R_GQSPI_IDR: 1061c95997a3SFrancisco Iglesias s->regs[R_GQSPI_IMR] |= value; 1062c95997a3SFrancisco Iglesias break; 1063c95997a3SFrancisco Iglesias case R_GQSPI_IER: 1064c95997a3SFrancisco Iglesias s->regs[R_GQSPI_IMR] &= ~value; 1065c95997a3SFrancisco Iglesias break; 1066c95997a3SFrancisco Iglesias case R_GQSPI_ISR: 1067c95997a3SFrancisco Iglesias s->regs[R_GQSPI_ISR] &= ~value; 1068c95997a3SFrancisco Iglesias break; 1069c95997a3SFrancisco Iglesias case R_GQSPI_IMR: 1070c95997a3SFrancisco Iglesias case R_GQSPI_RXD: 1071c95997a3SFrancisco Iglesias case R_GQSPI_GF_SNAPSHOT: 1072c95997a3SFrancisco Iglesias case R_GQSPI_MOD_ID: 1073c95997a3SFrancisco Iglesias break; 1074c95997a3SFrancisco Iglesias default: 1075c95997a3SFrancisco Iglesias s->regs[reg] = value; 1076c95997a3SFrancisco Iglesias break; 1077c95997a3SFrancisco Iglesias } 1078c95997a3SFrancisco Iglesias xlnx_zynqmp_qspips_update_cs_lines(s); 1079c95997a3SFrancisco Iglesias xlnx_zynqmp_qspips_check_flush(s); 1080c95997a3SFrancisco Iglesias xlnx_zynqmp_qspips_update_cs_lines(s); 1081c95997a3SFrancisco Iglesias xlnx_zynqmp_qspips_update_ixr(s); 1082c95997a3SFrancisco Iglesias } 1083c95997a3SFrancisco Iglesias xlnx_zynqmp_qspips_notify(s); 1084c95997a3SFrancisco Iglesias } 1085c95997a3SFrancisco Iglesias 1086b5cd9143SPeter Crosthwaite static const MemoryRegionOps qspips_ops = { 1087b5cd9143SPeter Crosthwaite .read = xilinx_spips_read, 1088b5cd9143SPeter Crosthwaite .write = xilinx_qspips_write, 1089b5cd9143SPeter Crosthwaite .endianness = DEVICE_LITTLE_ENDIAN, 1090b5cd9143SPeter Crosthwaite }; 1091b5cd9143SPeter Crosthwaite 1092c95997a3SFrancisco Iglesias static const MemoryRegionOps xlnx_zynqmp_qspips_ops = { 1093c95997a3SFrancisco Iglesias .read = xlnx_zynqmp_qspips_read, 1094c95997a3SFrancisco Iglesias .write = xlnx_zynqmp_qspips_write, 1095c95997a3SFrancisco Iglesias .endianness = DEVICE_LITTLE_ENDIAN, 1096c95997a3SFrancisco Iglesias }; 1097c95997a3SFrancisco Iglesias 109831e17060SPaolo Bonzini #define LQSPI_CACHE_SIZE 1024 109931e17060SPaolo Bonzini 1100252b99baSKONRAD Frederic static void lqspi_load_cache(void *opaque, hwaddr addr) 110131e17060SPaolo Bonzini { 11026b91f015SPeter Crosthwaite XilinxQSPIPS *q = opaque; 110331e17060SPaolo Bonzini XilinxSPIPS *s = opaque; 1104252b99baSKONRAD Frederic int i; 1105252b99baSKONRAD Frederic int flash_addr = ((addr & ~(LQSPI_CACHE_SIZE - 1)) 1106252b99baSKONRAD Frederic / num_effective_busses(s)); 110731e17060SPaolo Bonzini int slave = flash_addr >> LQSPI_ADDRESS_BITS; 110831e17060SPaolo Bonzini int cache_entry = 0; 110915408b42SPeter Crosthwaite uint32_t u_page_save = s->regs[R_LQSPI_STS] & ~LQSPI_CFG_U_PAGE; 111015408b42SPeter Crosthwaite 1111252b99baSKONRAD Frederic if (addr < q->lqspi_cached_addr || 1112252b99baSKONRAD Frederic addr > q->lqspi_cached_addr + LQSPI_CACHE_SIZE - 4) { 1113252b99baSKONRAD Frederic xilinx_qspips_invalidate_mmio_ptr(q); 111415408b42SPeter Crosthwaite s->regs[R_LQSPI_STS] &= ~LQSPI_CFG_U_PAGE; 111515408b42SPeter Crosthwaite s->regs[R_LQSPI_STS] |= slave ? LQSPI_CFG_U_PAGE : 0; 111631e17060SPaolo Bonzini 11174a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "config reg status: %08x\n", s->regs[R_LQSPI_CFG]); 111831e17060SPaolo Bonzini 111931e17060SPaolo Bonzini fifo8_reset(&s->tx_fifo); 112031e17060SPaolo Bonzini fifo8_reset(&s->rx_fifo); 112131e17060SPaolo Bonzini 112231e17060SPaolo Bonzini /* instruction */ 11234a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "pushing read instruction: %02x\n", 11244a5b6fa8SPeter Crosthwaite (unsigned)(uint8_t)(s->regs[R_LQSPI_CFG] & 11254a5b6fa8SPeter Crosthwaite LQSPI_CFG_INST_CODE)); 112631e17060SPaolo Bonzini fifo8_push(&s->tx_fifo, s->regs[R_LQSPI_CFG] & LQSPI_CFG_INST_CODE); 112731e17060SPaolo Bonzini /* read address */ 11284a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "pushing read address %06x\n", flash_addr); 1129fbfaa507SFrancisco Iglesias if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_ADDR4) { 1130fbfaa507SFrancisco Iglesias fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 24)); 1131fbfaa507SFrancisco Iglesias } 113231e17060SPaolo Bonzini fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 16)); 113331e17060SPaolo Bonzini fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 8)); 113431e17060SPaolo Bonzini fifo8_push(&s->tx_fifo, (uint8_t)flash_addr); 113531e17060SPaolo Bonzini /* mode bits */ 113631e17060SPaolo Bonzini if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_MODE_EN) { 113731e17060SPaolo Bonzini fifo8_push(&s->tx_fifo, extract32(s->regs[R_LQSPI_CFG], 113831e17060SPaolo Bonzini LQSPI_CFG_MODE_SHIFT, 113931e17060SPaolo Bonzini LQSPI_CFG_MODE_WIDTH)); 114031e17060SPaolo Bonzini } 114131e17060SPaolo Bonzini /* dummy bytes */ 114231e17060SPaolo Bonzini for (i = 0; i < (extract32(s->regs[R_LQSPI_CFG], LQSPI_CFG_DUMMY_SHIFT, 114331e17060SPaolo Bonzini LQSPI_CFG_DUMMY_WIDTH)); ++i) { 11444a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "pushing dummy byte\n"); 114531e17060SPaolo Bonzini fifo8_push(&s->tx_fifo, 0); 114631e17060SPaolo Bonzini } 1147c4f08ffeSPeter Crosthwaite xilinx_spips_update_cs_lines(s); 114831e17060SPaolo Bonzini xilinx_spips_flush_txfifo(s); 114931e17060SPaolo Bonzini fifo8_reset(&s->rx_fifo); 115031e17060SPaolo Bonzini 11514a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "starting QSPI data read\n"); 115231e17060SPaolo Bonzini 1153b0b7ae62SPeter Crosthwaite while (cache_entry < LQSPI_CACHE_SIZE) { 1154b0b7ae62SPeter Crosthwaite for (i = 0; i < 64; ++i) { 11552fdd171eSFrancisco Iglesias tx_data_bytes(&s->tx_fifo, 0, 1, false); 1156a66418f6SPeter Crosthwaite } 115731e17060SPaolo Bonzini xilinx_spips_flush_txfifo(s); 1158b0b7ae62SPeter Crosthwaite for (i = 0; i < 64; ++i) { 11592fdd171eSFrancisco Iglesias rx_data_bytes(&s->rx_fifo, &q->lqspi_buf[cache_entry++], 1); 1160a66418f6SPeter Crosthwaite } 116131e17060SPaolo Bonzini } 116231e17060SPaolo Bonzini 116315408b42SPeter Crosthwaite s->regs[R_LQSPI_STS] &= ~LQSPI_CFG_U_PAGE; 116415408b42SPeter Crosthwaite s->regs[R_LQSPI_STS] |= u_page_save; 116531e17060SPaolo Bonzini xilinx_spips_update_cs_lines(s); 116631e17060SPaolo Bonzini 1167b0b7ae62SPeter Crosthwaite q->lqspi_cached_addr = flash_addr * num_effective_busses(s); 1168252b99baSKONRAD Frederic } 1169252b99baSKONRAD Frederic } 1170252b99baSKONRAD Frederic 1171252b99baSKONRAD Frederic static void *lqspi_request_mmio_ptr(void *opaque, hwaddr addr, unsigned *size, 1172252b99baSKONRAD Frederic unsigned *offset) 1173252b99baSKONRAD Frederic { 1174252b99baSKONRAD Frederic XilinxQSPIPS *q = opaque; 117583c3a1f6SKONRAD Frederic hwaddr offset_within_the_region; 1176252b99baSKONRAD Frederic 117783c3a1f6SKONRAD Frederic if (!q->mmio_execution_enabled) { 117883c3a1f6SKONRAD Frederic return NULL; 117983c3a1f6SKONRAD Frederic } 118083c3a1f6SKONRAD Frederic 118183c3a1f6SKONRAD Frederic offset_within_the_region = addr & ~(LQSPI_CACHE_SIZE - 1); 1182252b99baSKONRAD Frederic lqspi_load_cache(opaque, offset_within_the_region); 1183252b99baSKONRAD Frederic *size = LQSPI_CACHE_SIZE; 1184252b99baSKONRAD Frederic *offset = offset_within_the_region; 1185252b99baSKONRAD Frederic return q->lqspi_buf; 1186252b99baSKONRAD Frederic } 1187252b99baSKONRAD Frederic 1188252b99baSKONRAD Frederic static uint64_t 1189252b99baSKONRAD Frederic lqspi_read(void *opaque, hwaddr addr, unsigned int size) 1190252b99baSKONRAD Frederic { 1191252b99baSKONRAD Frederic XilinxQSPIPS *q = opaque; 1192252b99baSKONRAD Frederic uint32_t ret; 1193252b99baSKONRAD Frederic 1194252b99baSKONRAD Frederic if (addr >= q->lqspi_cached_addr && 1195252b99baSKONRAD Frederic addr <= q->lqspi_cached_addr + LQSPI_CACHE_SIZE - 4) { 1196252b99baSKONRAD Frederic uint8_t *retp = &q->lqspi_buf[addr - q->lqspi_cached_addr]; 1197252b99baSKONRAD Frederic ret = cpu_to_le32(*(uint32_t *)retp); 1198252b99baSKONRAD Frederic DB_PRINT_L(1, "addr: %08x, data: %08x\n", (unsigned)addr, 1199252b99baSKONRAD Frederic (unsigned)ret); 1200252b99baSKONRAD Frederic return ret; 1201252b99baSKONRAD Frederic } else { 1202252b99baSKONRAD Frederic lqspi_load_cache(opaque, addr); 120331e17060SPaolo Bonzini return lqspi_read(opaque, addr, size); 120431e17060SPaolo Bonzini } 120531e17060SPaolo Bonzini } 120631e17060SPaolo Bonzini 120731e17060SPaolo Bonzini static const MemoryRegionOps lqspi_ops = { 120831e17060SPaolo Bonzini .read = lqspi_read, 1209252b99baSKONRAD Frederic .request_ptr = lqspi_request_mmio_ptr, 121031e17060SPaolo Bonzini .endianness = DEVICE_NATIVE_ENDIAN, 121131e17060SPaolo Bonzini .valid = { 1212b0b7ae62SPeter Crosthwaite .min_access_size = 1, 121331e17060SPaolo Bonzini .max_access_size = 4 121431e17060SPaolo Bonzini } 121531e17060SPaolo Bonzini }; 121631e17060SPaolo Bonzini 121731e17060SPaolo Bonzini static void xilinx_spips_realize(DeviceState *dev, Error **errp) 121831e17060SPaolo Bonzini { 121931e17060SPaolo Bonzini XilinxSPIPS *s = XILINX_SPIPS(dev); 122031e17060SPaolo Bonzini SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 122110e60b35SPeter Crosthwaite XilinxSPIPSClass *xsc = XILINX_SPIPS_GET_CLASS(s); 1222c8cccba3SPaolo Bonzini qemu_irq *cs; 122331e17060SPaolo Bonzini int i; 122431e17060SPaolo Bonzini 12254a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "realized spips\n"); 122631e17060SPaolo Bonzini 1227*fbe5dac7SFrancisco Iglesias if (s->num_busses > MAX_NUM_BUSSES) { 1228*fbe5dac7SFrancisco Iglesias error_setg(errp, 1229*fbe5dac7SFrancisco Iglesias "requested number of SPI busses %u exceeds maximum %d", 1230*fbe5dac7SFrancisco Iglesias s->num_busses, MAX_NUM_BUSSES); 1231*fbe5dac7SFrancisco Iglesias return; 1232*fbe5dac7SFrancisco Iglesias } 1233*fbe5dac7SFrancisco Iglesias if (s->num_busses < MIN_NUM_BUSSES) { 1234*fbe5dac7SFrancisco Iglesias error_setg(errp, 1235*fbe5dac7SFrancisco Iglesias "requested number of SPI busses %u is below minimum %d", 1236*fbe5dac7SFrancisco Iglesias s->num_busses, MIN_NUM_BUSSES); 1237*fbe5dac7SFrancisco Iglesias return; 1238*fbe5dac7SFrancisco Iglesias } 1239*fbe5dac7SFrancisco Iglesias 124031e17060SPaolo Bonzini s->spi = g_new(SSIBus *, s->num_busses); 124131e17060SPaolo Bonzini for (i = 0; i < s->num_busses; ++i) { 124231e17060SPaolo Bonzini char bus_name[16]; 124331e17060SPaolo Bonzini snprintf(bus_name, 16, "spi%d", i); 124431e17060SPaolo Bonzini s->spi[i] = ssi_create_bus(dev, bus_name); 124531e17060SPaolo Bonzini } 124631e17060SPaolo Bonzini 124731e17060SPaolo Bonzini s->cs_lines = g_new0(qemu_irq, s->num_cs * s->num_busses); 1248ef06ca39SFrancisco Iglesias s->cs_lines_state = g_new0(bool, s->num_cs * s->num_busses); 1249c8cccba3SPaolo Bonzini for (i = 0, cs = s->cs_lines; i < s->num_busses; ++i, cs += s->num_cs) { 1250c8cccba3SPaolo Bonzini ssi_auto_connect_slaves(DEVICE(s), cs, s->spi[i]); 1251c8cccba3SPaolo Bonzini } 1252c8cccba3SPaolo Bonzini 125331e17060SPaolo Bonzini sysbus_init_irq(sbd, &s->irq); 125431e17060SPaolo Bonzini for (i = 0; i < s->num_cs * s->num_busses; ++i) { 125531e17060SPaolo Bonzini sysbus_init_irq(sbd, &s->cs_lines[i]); 125631e17060SPaolo Bonzini } 125731e17060SPaolo Bonzini 125829776739SPaolo Bonzini memory_region_init_io(&s->iomem, OBJECT(s), xsc->reg_ops, s, 1259c95997a3SFrancisco Iglesias "spi", XLNX_ZYNQMP_SPIPS_R_MAX * 4); 126031e17060SPaolo Bonzini sysbus_init_mmio(sbd, &s->iomem); 126131e17060SPaolo Bonzini 12626b91f015SPeter Crosthwaite s->irqline = -1; 12636b91f015SPeter Crosthwaite 126410e60b35SPeter Crosthwaite fifo8_create(&s->rx_fifo, xsc->rx_fifo_size); 126510e60b35SPeter Crosthwaite fifo8_create(&s->tx_fifo, xsc->tx_fifo_size); 12666b91f015SPeter Crosthwaite } 12676b91f015SPeter Crosthwaite 12686b91f015SPeter Crosthwaite static void xilinx_qspips_realize(DeviceState *dev, Error **errp) 12696b91f015SPeter Crosthwaite { 12706b91f015SPeter Crosthwaite XilinxSPIPS *s = XILINX_SPIPS(dev); 12716b91f015SPeter Crosthwaite XilinxQSPIPS *q = XILINX_QSPIPS(dev); 12726b91f015SPeter Crosthwaite SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 12736b91f015SPeter Crosthwaite 12744a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "realized qspips\n"); 12756b91f015SPeter Crosthwaite 12766b91f015SPeter Crosthwaite s->num_busses = 2; 12776b91f015SPeter Crosthwaite s->num_cs = 2; 12786b91f015SPeter Crosthwaite s->num_txrx_bytes = 4; 12796b91f015SPeter Crosthwaite 12806b91f015SPeter Crosthwaite xilinx_spips_realize(dev, errp); 128129776739SPaolo Bonzini memory_region_init_io(&s->mmlqspi, OBJECT(s), &lqspi_ops, s, "lqspi", 128231e17060SPaolo Bonzini (1 << LQSPI_ADDRESS_BITS) * 2); 128331e17060SPaolo Bonzini sysbus_init_mmio(sbd, &s->mmlqspi); 128431e17060SPaolo Bonzini 12856b91f015SPeter Crosthwaite q->lqspi_cached_addr = ~0ULL; 128683c3a1f6SKONRAD Frederic 128783c3a1f6SKONRAD Frederic /* mmio_execution breaks migration better aborting than having strange 128883c3a1f6SKONRAD Frederic * bugs. 128983c3a1f6SKONRAD Frederic */ 129083c3a1f6SKONRAD Frederic if (q->mmio_execution_enabled) { 129183c3a1f6SKONRAD Frederic error_setg(&q->migration_blocker, 129283c3a1f6SKONRAD Frederic "enabling mmio_execution breaks migration"); 129383c3a1f6SKONRAD Frederic migrate_add_blocker(q->migration_blocker, &error_fatal); 129483c3a1f6SKONRAD Frederic } 129531e17060SPaolo Bonzini } 129631e17060SPaolo Bonzini 1297c95997a3SFrancisco Iglesias static void xlnx_zynqmp_qspips_realize(DeviceState *dev, Error **errp) 1298c95997a3SFrancisco Iglesias { 1299c95997a3SFrancisco Iglesias XlnxZynqMPQSPIPS *s = XLNX_ZYNQMP_QSPIPS(dev); 1300c95997a3SFrancisco Iglesias XilinxSPIPSClass *xsc = XILINX_SPIPS_GET_CLASS(s); 1301c95997a3SFrancisco Iglesias 1302c95997a3SFrancisco Iglesias xilinx_qspips_realize(dev, errp); 1303c95997a3SFrancisco Iglesias fifo8_create(&s->rx_fifo_g, xsc->rx_fifo_size); 1304c95997a3SFrancisco Iglesias fifo8_create(&s->tx_fifo_g, xsc->tx_fifo_size); 1305c95997a3SFrancisco Iglesias fifo32_create(&s->fifo_g, 32); 1306c95997a3SFrancisco Iglesias } 1307c95997a3SFrancisco Iglesias 1308c95997a3SFrancisco Iglesias static void xlnx_zynqmp_qspips_init(Object *obj) 1309c95997a3SFrancisco Iglesias { 1310c95997a3SFrancisco Iglesias XlnxZynqMPQSPIPS *rq = XLNX_ZYNQMP_QSPIPS(obj); 1311c95997a3SFrancisco Iglesias 1312c95997a3SFrancisco Iglesias object_property_add_link(obj, "stream-connected-dma", TYPE_STREAM_SLAVE, 1313c95997a3SFrancisco Iglesias (Object **)&rq->dma, 1314c95997a3SFrancisco Iglesias object_property_allow_set_link, 1315c95997a3SFrancisco Iglesias OBJ_PROP_LINK_UNREF_ON_RELEASE, 1316c95997a3SFrancisco Iglesias NULL); 1317c95997a3SFrancisco Iglesias } 1318c95997a3SFrancisco Iglesias 131931e17060SPaolo Bonzini static int xilinx_spips_post_load(void *opaque, int version_id) 132031e17060SPaolo Bonzini { 132131e17060SPaolo Bonzini xilinx_spips_update_ixr((XilinxSPIPS *)opaque); 132231e17060SPaolo Bonzini xilinx_spips_update_cs_lines((XilinxSPIPS *)opaque); 132331e17060SPaolo Bonzini return 0; 132431e17060SPaolo Bonzini } 132531e17060SPaolo Bonzini 132631e17060SPaolo Bonzini static const VMStateDescription vmstate_xilinx_spips = { 132731e17060SPaolo Bonzini .name = "xilinx_spips", 132831e17060SPaolo Bonzini .version_id = 2, 132931e17060SPaolo Bonzini .minimum_version_id = 2, 133031e17060SPaolo Bonzini .post_load = xilinx_spips_post_load, 133131e17060SPaolo Bonzini .fields = (VMStateField[]) { 133231e17060SPaolo Bonzini VMSTATE_FIFO8(tx_fifo, XilinxSPIPS), 133331e17060SPaolo Bonzini VMSTATE_FIFO8(rx_fifo, XilinxSPIPS), 13346363235bSAlistair Francis VMSTATE_UINT32_ARRAY(regs, XilinxSPIPS, XLNX_SPIPS_R_MAX), 133531e17060SPaolo Bonzini VMSTATE_UINT8(snoop_state, XilinxSPIPS), 133631e17060SPaolo Bonzini VMSTATE_END_OF_LIST() 133731e17060SPaolo Bonzini } 133831e17060SPaolo Bonzini }; 133931e17060SPaolo Bonzini 1340c95997a3SFrancisco Iglesias static int xlnx_zynqmp_qspips_post_load(void *opaque, int version_id) 1341c95997a3SFrancisco Iglesias { 1342c95997a3SFrancisco Iglesias XlnxZynqMPQSPIPS *s = (XlnxZynqMPQSPIPS *)opaque; 1343c95997a3SFrancisco Iglesias XilinxSPIPS *qs = XILINX_SPIPS(s); 1344c95997a3SFrancisco Iglesias 1345c95997a3SFrancisco Iglesias if (ARRAY_FIELD_EX32(s->regs, GQSPI_SELECT, GENERIC_QSPI_EN) && 1346c95997a3SFrancisco Iglesias fifo8_is_empty(&qs->rx_fifo) && fifo8_is_empty(&qs->tx_fifo)) { 1347c95997a3SFrancisco Iglesias xlnx_zynqmp_qspips_update_ixr(s); 1348c95997a3SFrancisco Iglesias xlnx_zynqmp_qspips_update_cs_lines(s); 1349c95997a3SFrancisco Iglesias } 1350c95997a3SFrancisco Iglesias return 0; 1351c95997a3SFrancisco Iglesias } 1352c95997a3SFrancisco Iglesias 1353c95997a3SFrancisco Iglesias static const VMStateDescription vmstate_xilinx_qspips = { 1354c95997a3SFrancisco Iglesias .name = "xilinx_qspips", 1355c95997a3SFrancisco Iglesias .version_id = 1, 1356c95997a3SFrancisco Iglesias .minimum_version_id = 1, 1357c95997a3SFrancisco Iglesias .fields = (VMStateField[]) { 1358c95997a3SFrancisco Iglesias VMSTATE_STRUCT(parent_obj, XilinxQSPIPS, 0, 1359c95997a3SFrancisco Iglesias vmstate_xilinx_spips, XilinxSPIPS), 1360c95997a3SFrancisco Iglesias VMSTATE_END_OF_LIST() 1361c95997a3SFrancisco Iglesias } 1362c95997a3SFrancisco Iglesias }; 1363c95997a3SFrancisco Iglesias 1364c95997a3SFrancisco Iglesias static const VMStateDescription vmstate_xlnx_zynqmp_qspips = { 1365c95997a3SFrancisco Iglesias .name = "xlnx_zynqmp_qspips", 1366c95997a3SFrancisco Iglesias .version_id = 1, 1367c95997a3SFrancisco Iglesias .minimum_version_id = 1, 1368c95997a3SFrancisco Iglesias .post_load = xlnx_zynqmp_qspips_post_load, 1369c95997a3SFrancisco Iglesias .fields = (VMStateField[]) { 1370c95997a3SFrancisco Iglesias VMSTATE_STRUCT(parent_obj, XlnxZynqMPQSPIPS, 0, 1371c95997a3SFrancisco Iglesias vmstate_xilinx_qspips, XilinxQSPIPS), 1372c95997a3SFrancisco Iglesias VMSTATE_FIFO8(tx_fifo_g, XlnxZynqMPQSPIPS), 1373c95997a3SFrancisco Iglesias VMSTATE_FIFO8(rx_fifo_g, XlnxZynqMPQSPIPS), 1374c95997a3SFrancisco Iglesias VMSTATE_FIFO32(fifo_g, XlnxZynqMPQSPIPS), 1375c95997a3SFrancisco Iglesias VMSTATE_UINT32_ARRAY(regs, XlnxZynqMPQSPIPS, XLNX_ZYNQMP_SPIPS_R_MAX), 1376c95997a3SFrancisco Iglesias VMSTATE_END_OF_LIST() 1377c95997a3SFrancisco Iglesias } 1378c95997a3SFrancisco Iglesias }; 1379c95997a3SFrancisco Iglesias 138083c3a1f6SKONRAD Frederic static Property xilinx_qspips_properties[] = { 138183c3a1f6SKONRAD Frederic /* We had to turn this off for 2.10 as it is not compatible with migration. 138283c3a1f6SKONRAD Frederic * It can be enabled but will prevent the device to be migrated. 138383c3a1f6SKONRAD Frederic * This will go aways when a fix will be released. 138483c3a1f6SKONRAD Frederic */ 138583c3a1f6SKONRAD Frederic DEFINE_PROP_BOOL("x-mmio-exec", XilinxQSPIPS, mmio_execution_enabled, 138683c3a1f6SKONRAD Frederic false), 138783c3a1f6SKONRAD Frederic DEFINE_PROP_END_OF_LIST(), 138883c3a1f6SKONRAD Frederic }; 138983c3a1f6SKONRAD Frederic 139031e17060SPaolo Bonzini static Property xilinx_spips_properties[] = { 139131e17060SPaolo Bonzini DEFINE_PROP_UINT8("num-busses", XilinxSPIPS, num_busses, 1), 139231e17060SPaolo Bonzini DEFINE_PROP_UINT8("num-ss-bits", XilinxSPIPS, num_cs, 4), 139331e17060SPaolo Bonzini DEFINE_PROP_UINT8("num-txrx-bytes", XilinxSPIPS, num_txrx_bytes, 1), 139431e17060SPaolo Bonzini DEFINE_PROP_END_OF_LIST(), 139531e17060SPaolo Bonzini }; 13966b91f015SPeter Crosthwaite 13976b91f015SPeter Crosthwaite static void xilinx_qspips_class_init(ObjectClass *klass, void * data) 13986b91f015SPeter Crosthwaite { 13996b91f015SPeter Crosthwaite DeviceClass *dc = DEVICE_CLASS(klass); 140010e60b35SPeter Crosthwaite XilinxSPIPSClass *xsc = XILINX_SPIPS_CLASS(klass); 14016b91f015SPeter Crosthwaite 14026b91f015SPeter Crosthwaite dc->realize = xilinx_qspips_realize; 140383c3a1f6SKONRAD Frederic dc->props = xilinx_qspips_properties; 1404b5cd9143SPeter Crosthwaite xsc->reg_ops = &qspips_ops; 140510e60b35SPeter Crosthwaite xsc->rx_fifo_size = RXFF_A_Q; 140610e60b35SPeter Crosthwaite xsc->tx_fifo_size = TXFF_A_Q; 14076b91f015SPeter Crosthwaite } 14086b91f015SPeter Crosthwaite 140931e17060SPaolo Bonzini static void xilinx_spips_class_init(ObjectClass *klass, void *data) 141031e17060SPaolo Bonzini { 141131e17060SPaolo Bonzini DeviceClass *dc = DEVICE_CLASS(klass); 141210e60b35SPeter Crosthwaite XilinxSPIPSClass *xsc = XILINX_SPIPS_CLASS(klass); 141331e17060SPaolo Bonzini 141431e17060SPaolo Bonzini dc->realize = xilinx_spips_realize; 141531e17060SPaolo Bonzini dc->reset = xilinx_spips_reset; 141631e17060SPaolo Bonzini dc->props = xilinx_spips_properties; 141731e17060SPaolo Bonzini dc->vmsd = &vmstate_xilinx_spips; 141810e60b35SPeter Crosthwaite 1419b5cd9143SPeter Crosthwaite xsc->reg_ops = &spips_ops; 142010e60b35SPeter Crosthwaite xsc->rx_fifo_size = RXFF_A; 142110e60b35SPeter Crosthwaite xsc->tx_fifo_size = TXFF_A; 142231e17060SPaolo Bonzini } 142331e17060SPaolo Bonzini 1424c95997a3SFrancisco Iglesias static void xlnx_zynqmp_qspips_class_init(ObjectClass *klass, void * data) 1425c95997a3SFrancisco Iglesias { 1426c95997a3SFrancisco Iglesias DeviceClass *dc = DEVICE_CLASS(klass); 1427c95997a3SFrancisco Iglesias XilinxSPIPSClass *xsc = XILINX_SPIPS_CLASS(klass); 1428c95997a3SFrancisco Iglesias 1429c95997a3SFrancisco Iglesias dc->realize = xlnx_zynqmp_qspips_realize; 1430c95997a3SFrancisco Iglesias dc->reset = xlnx_zynqmp_qspips_reset; 1431c95997a3SFrancisco Iglesias dc->vmsd = &vmstate_xlnx_zynqmp_qspips; 1432c95997a3SFrancisco Iglesias xsc->reg_ops = &xlnx_zynqmp_qspips_ops; 1433c95997a3SFrancisco Iglesias xsc->rx_fifo_size = RXFF_A_Q; 1434c95997a3SFrancisco Iglesias xsc->tx_fifo_size = TXFF_A_Q; 1435c95997a3SFrancisco Iglesias } 1436c95997a3SFrancisco Iglesias 143731e17060SPaolo Bonzini static const TypeInfo xilinx_spips_info = { 143831e17060SPaolo Bonzini .name = TYPE_XILINX_SPIPS, 143931e17060SPaolo Bonzini .parent = TYPE_SYS_BUS_DEVICE, 144031e17060SPaolo Bonzini .instance_size = sizeof(XilinxSPIPS), 144131e17060SPaolo Bonzini .class_init = xilinx_spips_class_init, 144210e60b35SPeter Crosthwaite .class_size = sizeof(XilinxSPIPSClass), 144331e17060SPaolo Bonzini }; 144431e17060SPaolo Bonzini 14456b91f015SPeter Crosthwaite static const TypeInfo xilinx_qspips_info = { 14466b91f015SPeter Crosthwaite .name = TYPE_XILINX_QSPIPS, 14476b91f015SPeter Crosthwaite .parent = TYPE_XILINX_SPIPS, 14486b91f015SPeter Crosthwaite .instance_size = sizeof(XilinxQSPIPS), 14496b91f015SPeter Crosthwaite .class_init = xilinx_qspips_class_init, 14506b91f015SPeter Crosthwaite }; 14516b91f015SPeter Crosthwaite 1452c95997a3SFrancisco Iglesias static const TypeInfo xlnx_zynqmp_qspips_info = { 1453c95997a3SFrancisco Iglesias .name = TYPE_XLNX_ZYNQMP_QSPIPS, 1454c95997a3SFrancisco Iglesias .parent = TYPE_XILINX_QSPIPS, 1455c95997a3SFrancisco Iglesias .instance_size = sizeof(XlnxZynqMPQSPIPS), 1456c95997a3SFrancisco Iglesias .instance_init = xlnx_zynqmp_qspips_init, 1457c95997a3SFrancisco Iglesias .class_init = xlnx_zynqmp_qspips_class_init, 1458c95997a3SFrancisco Iglesias }; 1459c95997a3SFrancisco Iglesias 146031e17060SPaolo Bonzini static void xilinx_spips_register_types(void) 146131e17060SPaolo Bonzini { 146231e17060SPaolo Bonzini type_register_static(&xilinx_spips_info); 14636b91f015SPeter Crosthwaite type_register_static(&xilinx_qspips_info); 1464c95997a3SFrancisco Iglesias type_register_static(&xlnx_zynqmp_qspips_info); 146531e17060SPaolo Bonzini } 146631e17060SPaolo Bonzini 146731e17060SPaolo Bonzini type_init(xilinx_spips_register_types) 1468