131e17060SPaolo Bonzini /* 231e17060SPaolo Bonzini * QEMU model of the Xilinx Zynq SPI controller 331e17060SPaolo Bonzini * 431e17060SPaolo Bonzini * Copyright (c) 2012 Peter A. G. Crosthwaite 531e17060SPaolo Bonzini * 631e17060SPaolo Bonzini * Permission is hereby granted, free of charge, to any person obtaining a copy 731e17060SPaolo Bonzini * of this software and associated documentation files (the "Software"), to deal 831e17060SPaolo Bonzini * in the Software without restriction, including without limitation the rights 931e17060SPaolo Bonzini * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 1031e17060SPaolo Bonzini * copies of the Software, and to permit persons to whom the Software is 1131e17060SPaolo Bonzini * furnished to do so, subject to the following conditions: 1231e17060SPaolo Bonzini * 1331e17060SPaolo Bonzini * The above copyright notice and this permission notice shall be included in 1431e17060SPaolo Bonzini * all copies or substantial portions of the Software. 1531e17060SPaolo Bonzini * 1631e17060SPaolo Bonzini * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1731e17060SPaolo Bonzini * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1831e17060SPaolo Bonzini * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 1931e17060SPaolo Bonzini * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 2031e17060SPaolo Bonzini * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 2131e17060SPaolo Bonzini * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 2231e17060SPaolo Bonzini * THE SOFTWARE. 2331e17060SPaolo Bonzini */ 2431e17060SPaolo Bonzini 258ef94f0bSPeter Maydell #include "qemu/osdep.h" 2631e17060SPaolo Bonzini #include "hw/sysbus.h" 2731e17060SPaolo Bonzini #include "sysemu/sysemu.h" 2864552b6bSMarkus Armbruster #include "hw/irq.h" 2931e17060SPaolo Bonzini #include "hw/ptimer.h" 3031e17060SPaolo Bonzini #include "qemu/log.h" 310b8fa32fSMarkus Armbruster #include "qemu/module.h" 3231e17060SPaolo Bonzini #include "qemu/bitops.h" 336363235bSAlistair Francis #include "hw/ssi/xilinx_spips.h" 3483c3a1f6SKONRAD Frederic #include "qapi/error.h" 35ef06ca39SFrancisco Iglesias #include "hw/register.h" 36c95997a3SFrancisco Iglesias #include "sysemu/dma.h" 3783c3a1f6SKONRAD Frederic #include "migration/blocker.h" 38*d6454270SMarkus Armbruster #include "migration/vmstate.h" 3931e17060SPaolo Bonzini 404a5b6fa8SPeter Crosthwaite #ifndef XILINX_SPIPS_ERR_DEBUG 414a5b6fa8SPeter Crosthwaite #define XILINX_SPIPS_ERR_DEBUG 0 424a5b6fa8SPeter Crosthwaite #endif 434a5b6fa8SPeter Crosthwaite 444a5b6fa8SPeter Crosthwaite #define DB_PRINT_L(level, ...) do { \ 454a5b6fa8SPeter Crosthwaite if (XILINX_SPIPS_ERR_DEBUG > (level)) { \ 4631e17060SPaolo Bonzini fprintf(stderr, ": %s: ", __func__); \ 4731e17060SPaolo Bonzini fprintf(stderr, ## __VA_ARGS__); \ 484a5b6fa8SPeter Crosthwaite } \ 492562755eSEric Blake } while (0) 5031e17060SPaolo Bonzini 5131e17060SPaolo Bonzini /* config register */ 5231e17060SPaolo Bonzini #define R_CONFIG (0x00 / 4) 53c8f8f9fbSPeter Maydell #define IFMODE (1U << 31) 542fdd171eSFrancisco Iglesias #define R_CONFIG_ENDIAN (1 << 26) 5531e17060SPaolo Bonzini #define MODEFAIL_GEN_EN (1 << 17) 5631e17060SPaolo Bonzini #define MAN_START_COM (1 << 16) 5731e17060SPaolo Bonzini #define MAN_START_EN (1 << 15) 5831e17060SPaolo Bonzini #define MANUAL_CS (1 << 14) 5931e17060SPaolo Bonzini #define CS (0xF << 10) 6031e17060SPaolo Bonzini #define CS_SHIFT (10) 6131e17060SPaolo Bonzini #define PERI_SEL (1 << 9) 6231e17060SPaolo Bonzini #define REF_CLK (1 << 8) 6331e17060SPaolo Bonzini #define FIFO_WIDTH (3 << 6) 6431e17060SPaolo Bonzini #define BAUD_RATE_DIV (7 << 3) 6531e17060SPaolo Bonzini #define CLK_PH (1 << 2) 6631e17060SPaolo Bonzini #define CLK_POL (1 << 1) 6731e17060SPaolo Bonzini #define MODE_SEL (1 << 0) 682133a5f6SPeter Crosthwaite #define R_CONFIG_RSVD (0x7bf40000) 6931e17060SPaolo Bonzini 7031e17060SPaolo Bonzini /* interrupt mechanism */ 7131e17060SPaolo Bonzini #define R_INTR_STATUS (0x04 / 4) 724f0da466SAlistair Francis #define R_INTR_STATUS_RESET (0x104) 7331e17060SPaolo Bonzini #define R_INTR_EN (0x08 / 4) 7431e17060SPaolo Bonzini #define R_INTR_DIS (0x0C / 4) 7531e17060SPaolo Bonzini #define R_INTR_MASK (0x10 / 4) 7631e17060SPaolo Bonzini #define IXR_TX_FIFO_UNDERFLOW (1 << 6) 77c95997a3SFrancisco Iglesias /* Poll timeout not implemented */ 78c95997a3SFrancisco Iglesias #define IXR_RX_FIFO_EMPTY (1 << 11) 79c95997a3SFrancisco Iglesias #define IXR_GENERIC_FIFO_FULL (1 << 10) 80c95997a3SFrancisco Iglesias #define IXR_GENERIC_FIFO_NOT_FULL (1 << 9) 81c95997a3SFrancisco Iglesias #define IXR_TX_FIFO_EMPTY (1 << 8) 82c95997a3SFrancisco Iglesias #define IXR_GENERIC_FIFO_EMPTY (1 << 7) 8331e17060SPaolo Bonzini #define IXR_RX_FIFO_FULL (1 << 5) 8431e17060SPaolo Bonzini #define IXR_RX_FIFO_NOT_EMPTY (1 << 4) 8531e17060SPaolo Bonzini #define IXR_TX_FIFO_FULL (1 << 3) 8631e17060SPaolo Bonzini #define IXR_TX_FIFO_NOT_FULL (1 << 2) 8731e17060SPaolo Bonzini #define IXR_TX_FIFO_MODE_FAIL (1 << 1) 8831e17060SPaolo Bonzini #define IXR_RX_FIFO_OVERFLOW (1 << 0) 89c95997a3SFrancisco Iglesias #define IXR_ALL ((1 << 13) - 1) 90c95997a3SFrancisco Iglesias #define GQSPI_IXR_MASK 0xFBE 91c95997a3SFrancisco Iglesias #define IXR_SELF_CLEAR \ 92c95997a3SFrancisco Iglesias (IXR_GENERIC_FIFO_EMPTY \ 93c95997a3SFrancisco Iglesias | IXR_GENERIC_FIFO_FULL \ 94c95997a3SFrancisco Iglesias | IXR_GENERIC_FIFO_NOT_FULL \ 95c95997a3SFrancisco Iglesias | IXR_TX_FIFO_EMPTY \ 96c95997a3SFrancisco Iglesias | IXR_TX_FIFO_FULL \ 97c95997a3SFrancisco Iglesias | IXR_TX_FIFO_NOT_FULL \ 98c95997a3SFrancisco Iglesias | IXR_RX_FIFO_EMPTY \ 99c95997a3SFrancisco Iglesias | IXR_RX_FIFO_FULL \ 100c95997a3SFrancisco Iglesias | IXR_RX_FIFO_NOT_EMPTY) 10131e17060SPaolo Bonzini 10231e17060SPaolo Bonzini #define R_EN (0x14 / 4) 10331e17060SPaolo Bonzini #define R_DELAY (0x18 / 4) 10431e17060SPaolo Bonzini #define R_TX_DATA (0x1C / 4) 10531e17060SPaolo Bonzini #define R_RX_DATA (0x20 / 4) 10631e17060SPaolo Bonzini #define R_SLAVE_IDLE_COUNT (0x24 / 4) 10731e17060SPaolo Bonzini #define R_TX_THRES (0x28 / 4) 10831e17060SPaolo Bonzini #define R_RX_THRES (0x2C / 4) 1094f0da466SAlistair Francis #define R_GPIO (0x30 / 4) 1104f0da466SAlistair Francis #define R_LPBK_DLY_ADJ (0x38 / 4) 1114f0da466SAlistair Francis #define R_LPBK_DLY_ADJ_RESET (0x33) 11231e17060SPaolo Bonzini #define R_TXD1 (0x80 / 4) 11331e17060SPaolo Bonzini #define R_TXD2 (0x84 / 4) 11431e17060SPaolo Bonzini #define R_TXD3 (0x88 / 4) 11531e17060SPaolo Bonzini 11631e17060SPaolo Bonzini #define R_LQSPI_CFG (0xa0 / 4) 11731e17060SPaolo Bonzini #define R_LQSPI_CFG_RESET 0x03A002EB 118c8f8f9fbSPeter Maydell #define LQSPI_CFG_LQ_MODE (1U << 31) 11931e17060SPaolo Bonzini #define LQSPI_CFG_TWO_MEM (1 << 30) 120fbfaa507SFrancisco Iglesias #define LQSPI_CFG_SEP_BUS (1 << 29) 12131e17060SPaolo Bonzini #define LQSPI_CFG_U_PAGE (1 << 28) 122fbfaa507SFrancisco Iglesias #define LQSPI_CFG_ADDR4 (1 << 27) 12331e17060SPaolo Bonzini #define LQSPI_CFG_MODE_EN (1 << 25) 12431e17060SPaolo Bonzini #define LQSPI_CFG_MODE_WIDTH 8 12531e17060SPaolo Bonzini #define LQSPI_CFG_MODE_SHIFT 16 12631e17060SPaolo Bonzini #define LQSPI_CFG_DUMMY_WIDTH 3 12731e17060SPaolo Bonzini #define LQSPI_CFG_DUMMY_SHIFT 8 12831e17060SPaolo Bonzini #define LQSPI_CFG_INST_CODE 0xFF 12931e17060SPaolo Bonzini 130ef06ca39SFrancisco Iglesias #define R_CMND (0xc0 / 4) 131ef06ca39SFrancisco Iglesias #define R_CMND_RXFIFO_DRAIN (1 << 19) 132ef06ca39SFrancisco Iglesias FIELD(CMND, PARTIAL_BYTE_LEN, 16, 3) 133ef06ca39SFrancisco Iglesias #define R_CMND_EXT_ADD (1 << 15) 134ef06ca39SFrancisco Iglesias FIELD(CMND, RX_DISCARD, 8, 7) 135ef06ca39SFrancisco Iglesias FIELD(CMND, DUMMY_CYCLES, 2, 6) 136ef06ca39SFrancisco Iglesias #define R_CMND_DMA_EN (1 << 1) 137ef06ca39SFrancisco Iglesias #define R_CMND_PUSH_WAIT (1 << 0) 138275e28ccSFrancisco Iglesias #define R_TRANSFER_SIZE (0xc4 / 4) 13931e17060SPaolo Bonzini #define R_LQSPI_STS (0xA4 / 4) 14031e17060SPaolo Bonzini #define LQSPI_STS_WR_RECVD (1 << 1) 14131e17060SPaolo Bonzini 14231e17060SPaolo Bonzini #define R_MOD_ID (0xFC / 4) 14331e17060SPaolo Bonzini 144c95997a3SFrancisco Iglesias #define R_GQSPI_SELECT (0x144 / 4) 145c95997a3SFrancisco Iglesias FIELD(GQSPI_SELECT, GENERIC_QSPI_EN, 0, 1) 146c95997a3SFrancisco Iglesias #define R_GQSPI_ISR (0x104 / 4) 147c95997a3SFrancisco Iglesias #define R_GQSPI_IER (0x108 / 4) 148c95997a3SFrancisco Iglesias #define R_GQSPI_IDR (0x10c / 4) 149c95997a3SFrancisco Iglesias #define R_GQSPI_IMR (0x110 / 4) 1504f0da466SAlistair Francis #define R_GQSPI_IMR_RESET (0xfbe) 151c95997a3SFrancisco Iglesias #define R_GQSPI_TX_THRESH (0x128 / 4) 152c95997a3SFrancisco Iglesias #define R_GQSPI_RX_THRESH (0x12c / 4) 1534f0da466SAlistair Francis #define R_GQSPI_GPIO (0x130 / 4) 1544f0da466SAlistair Francis #define R_GQSPI_LPBK_DLY_ADJ (0x138 / 4) 1554f0da466SAlistair Francis #define R_GQSPI_LPBK_DLY_ADJ_RESET (0x33) 156c95997a3SFrancisco Iglesias #define R_GQSPI_CNFG (0x100 / 4) 157c95997a3SFrancisco Iglesias FIELD(GQSPI_CNFG, MODE_EN, 30, 2) 158c95997a3SFrancisco Iglesias FIELD(GQSPI_CNFG, GEN_FIFO_START_MODE, 29, 1) 159c95997a3SFrancisco Iglesias FIELD(GQSPI_CNFG, GEN_FIFO_START, 28, 1) 160c95997a3SFrancisco Iglesias FIELD(GQSPI_CNFG, ENDIAN, 26, 1) 161c95997a3SFrancisco Iglesias /* Poll timeout not implemented */ 162c95997a3SFrancisco Iglesias FIELD(GQSPI_CNFG, EN_POLL_TIMEOUT, 20, 1) 163c95997a3SFrancisco Iglesias /* QEMU doesnt care about any of these last three */ 164c95997a3SFrancisco Iglesias FIELD(GQSPI_CNFG, BR, 3, 3) 165c95997a3SFrancisco Iglesias FIELD(GQSPI_CNFG, CPH, 2, 1) 166c95997a3SFrancisco Iglesias FIELD(GQSPI_CNFG, CPL, 1, 1) 167c95997a3SFrancisco Iglesias #define R_GQSPI_GEN_FIFO (0x140 / 4) 168c95997a3SFrancisco Iglesias #define R_GQSPI_TXD (0x11c / 4) 169c95997a3SFrancisco Iglesias #define R_GQSPI_RXD (0x120 / 4) 170c95997a3SFrancisco Iglesias #define R_GQSPI_FIFO_CTRL (0x14c / 4) 171c95997a3SFrancisco Iglesias FIELD(GQSPI_FIFO_CTRL, RX_FIFO_RESET, 2, 1) 172c95997a3SFrancisco Iglesias FIELD(GQSPI_FIFO_CTRL, TX_FIFO_RESET, 1, 1) 173c95997a3SFrancisco Iglesias FIELD(GQSPI_FIFO_CTRL, GENERIC_FIFO_RESET, 0, 1) 174c95997a3SFrancisco Iglesias #define R_GQSPI_GFIFO_THRESH (0x150 / 4) 175c95997a3SFrancisco Iglesias #define R_GQSPI_DATA_STS (0x15c / 4) 176c95997a3SFrancisco Iglesias /* We use the snapshot register to hold the core state for the currently 177c95997a3SFrancisco Iglesias * or most recently executed command. So the generic fifo format is defined 178c95997a3SFrancisco Iglesias * for the snapshot register 179c95997a3SFrancisco Iglesias */ 180c95997a3SFrancisco Iglesias #define R_GQSPI_GF_SNAPSHOT (0x160 / 4) 181c95997a3SFrancisco Iglesias FIELD(GQSPI_GF_SNAPSHOT, POLL, 19, 1) 182c95997a3SFrancisco Iglesias FIELD(GQSPI_GF_SNAPSHOT, STRIPE, 18, 1) 183c95997a3SFrancisco Iglesias FIELD(GQSPI_GF_SNAPSHOT, RECIEVE, 17, 1) 184c95997a3SFrancisco Iglesias FIELD(GQSPI_GF_SNAPSHOT, TRANSMIT, 16, 1) 185c95997a3SFrancisco Iglesias FIELD(GQSPI_GF_SNAPSHOT, DATA_BUS_SELECT, 14, 2) 186c95997a3SFrancisco Iglesias FIELD(GQSPI_GF_SNAPSHOT, CHIP_SELECT, 12, 2) 187c95997a3SFrancisco Iglesias FIELD(GQSPI_GF_SNAPSHOT, SPI_MODE, 10, 2) 188c95997a3SFrancisco Iglesias FIELD(GQSPI_GF_SNAPSHOT, EXPONENT, 9, 1) 189c95997a3SFrancisco Iglesias FIELD(GQSPI_GF_SNAPSHOT, DATA_XFER, 8, 1) 190c95997a3SFrancisco Iglesias FIELD(GQSPI_GF_SNAPSHOT, IMMEDIATE_DATA, 0, 8) 1914f0da466SAlistair Francis #define R_GQSPI_MOD_ID (0x1fc / 4) 1924f0da466SAlistair Francis #define R_GQSPI_MOD_ID_RESET (0x10a0000) 1934f0da466SAlistair Francis 1944f0da466SAlistair Francis #define R_QSPIDMA_DST_CTRL (0x80c / 4) 1954f0da466SAlistair Francis #define R_QSPIDMA_DST_CTRL_RESET (0x803ffa00) 1964f0da466SAlistair Francis #define R_QSPIDMA_DST_I_MASK (0x820 / 4) 1974f0da466SAlistair Francis #define R_QSPIDMA_DST_I_MASK_RESET (0xfe) 1984f0da466SAlistair Francis #define R_QSPIDMA_DST_CTRL2 (0x824 / 4) 1994f0da466SAlistair Francis #define R_QSPIDMA_DST_CTRL2_RESET (0x081bfff8) 2004f0da466SAlistair Francis 20131e17060SPaolo Bonzini /* size of TXRX FIFOs */ 202c95997a3SFrancisco Iglesias #define RXFF_A (128) 203c95997a3SFrancisco Iglesias #define TXFF_A (128) 20431e17060SPaolo Bonzini 20510e60b35SPeter Crosthwaite #define RXFF_A_Q (64 * 4) 20610e60b35SPeter Crosthwaite #define TXFF_A_Q (64 * 4) 20710e60b35SPeter Crosthwaite 20831e17060SPaolo Bonzini /* 16MB per linear region */ 20931e17060SPaolo Bonzini #define LQSPI_ADDRESS_BITS 24 21031e17060SPaolo Bonzini 21131e17060SPaolo Bonzini #define SNOOP_CHECKING 0xFF 212ef06ca39SFrancisco Iglesias #define SNOOP_ADDR 0xF0 213ef06ca39SFrancisco Iglesias #define SNOOP_NONE 0xEE 21431e17060SPaolo Bonzini #define SNOOP_STRIPING 0 21531e17060SPaolo Bonzini 216fbe5dac7SFrancisco Iglesias #define MIN_NUM_BUSSES 1 217fbe5dac7SFrancisco Iglesias #define MAX_NUM_BUSSES 2 218fbe5dac7SFrancisco Iglesias 21931e17060SPaolo Bonzini static inline int num_effective_busses(XilinxSPIPS *s) 22031e17060SPaolo Bonzini { 22131e17060SPaolo Bonzini return (s->regs[R_LQSPI_CFG] & LQSPI_CFG_SEP_BUS && 22231e17060SPaolo Bonzini s->regs[R_LQSPI_CFG] & LQSPI_CFG_TWO_MEM) ? s->num_busses : 1; 22331e17060SPaolo Bonzini } 22431e17060SPaolo Bonzini 225c95997a3SFrancisco Iglesias static void xilinx_spips_update_cs(XilinxSPIPS *s, int field) 226c4f08ffeSPeter Crosthwaite { 227c95997a3SFrancisco Iglesias int i; 22831e17060SPaolo Bonzini 2290c4a94b8SFrancisco Iglesias for (i = 0; i < s->num_cs * s->num_busses; i++) { 230c95997a3SFrancisco Iglesias bool old_state = s->cs_lines_state[i]; 231c95997a3SFrancisco Iglesias bool new_state = field & (1 << i); 23231e17060SPaolo Bonzini 233c95997a3SFrancisco Iglesias if (old_state != new_state) { 234c95997a3SFrancisco Iglesias s->cs_lines_state[i] = new_state; 235ef06ca39SFrancisco Iglesias s->rx_discard = ARRAY_FIELD_EX32(s->regs, CMND, RX_DISCARD); 236c95997a3SFrancisco Iglesias DB_PRINT_L(1, "%sselecting slave %d\n", new_state ? "" : "de", i); 237ef06ca39SFrancisco Iglesias } 238c95997a3SFrancisco Iglesias qemu_set_irq(s->cs_lines[i], !new_state); 23931e17060SPaolo Bonzini } 2400c4a94b8SFrancisco Iglesias if (!(field & ((1 << (s->num_cs * s->num_busses)) - 1))) { 24131e17060SPaolo Bonzini s->snoop_state = SNOOP_CHECKING; 242ef06ca39SFrancisco Iglesias s->cmd_dummies = 0; 243ef06ca39SFrancisco Iglesias s->link_state = 1; 244ef06ca39SFrancisco Iglesias s->link_state_next = 1; 245ef06ca39SFrancisco Iglesias s->link_state_next_when = 0; 2464a5b6fa8SPeter Crosthwaite DB_PRINT_L(1, "moving to snoop check state\n"); 24731e17060SPaolo Bonzini } 24831e17060SPaolo Bonzini } 24931e17060SPaolo Bonzini 250c95997a3SFrancisco Iglesias static void xlnx_zynqmp_qspips_update_cs_lines(XlnxZynqMPQSPIPS *s) 251c95997a3SFrancisco Iglesias { 252c95997a3SFrancisco Iglesias if (s->regs[R_GQSPI_GF_SNAPSHOT]) { 253c95997a3SFrancisco Iglesias int field = ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, CHIP_SELECT); 2540c4a94b8SFrancisco Iglesias bool upper_cs_sel = field & (1 << 1); 2550c4a94b8SFrancisco Iglesias bool lower_cs_sel = field & 1; 2560c4a94b8SFrancisco Iglesias bool bus0_enabled; 2570c4a94b8SFrancisco Iglesias bool bus1_enabled; 2580c4a94b8SFrancisco Iglesias uint8_t buses; 2590c4a94b8SFrancisco Iglesias int cs = 0; 2600c4a94b8SFrancisco Iglesias 2610c4a94b8SFrancisco Iglesias buses = ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, DATA_BUS_SELECT); 2620c4a94b8SFrancisco Iglesias bus0_enabled = buses & 1; 2630c4a94b8SFrancisco Iglesias bus1_enabled = buses & (1 << 1); 2640c4a94b8SFrancisco Iglesias 2650c4a94b8SFrancisco Iglesias if (bus0_enabled && bus1_enabled) { 2660c4a94b8SFrancisco Iglesias if (lower_cs_sel) { 2670c4a94b8SFrancisco Iglesias cs |= 1; 2680c4a94b8SFrancisco Iglesias } 2690c4a94b8SFrancisco Iglesias if (upper_cs_sel) { 2700c4a94b8SFrancisco Iglesias cs |= 1 << 3; 2710c4a94b8SFrancisco Iglesias } 2720c4a94b8SFrancisco Iglesias } else if (bus0_enabled) { 2730c4a94b8SFrancisco Iglesias if (lower_cs_sel) { 2740c4a94b8SFrancisco Iglesias cs |= 1; 2750c4a94b8SFrancisco Iglesias } 2760c4a94b8SFrancisco Iglesias if (upper_cs_sel) { 2770c4a94b8SFrancisco Iglesias cs |= 1 << 1; 2780c4a94b8SFrancisco Iglesias } 2790c4a94b8SFrancisco Iglesias } else if (bus1_enabled) { 2800c4a94b8SFrancisco Iglesias if (lower_cs_sel) { 2810c4a94b8SFrancisco Iglesias cs |= 1 << 2; 2820c4a94b8SFrancisco Iglesias } 2830c4a94b8SFrancisco Iglesias if (upper_cs_sel) { 2840c4a94b8SFrancisco Iglesias cs |= 1 << 3; 2850c4a94b8SFrancisco Iglesias } 2860c4a94b8SFrancisco Iglesias } 2870c4a94b8SFrancisco Iglesias xilinx_spips_update_cs(XILINX_SPIPS(s), cs); 288c95997a3SFrancisco Iglesias } 289c95997a3SFrancisco Iglesias } 290c95997a3SFrancisco Iglesias 291c95997a3SFrancisco Iglesias static void xilinx_spips_update_cs_lines(XilinxSPIPS *s) 292c95997a3SFrancisco Iglesias { 293c95997a3SFrancisco Iglesias int field = ~((s->regs[R_CONFIG] & CS) >> CS_SHIFT); 294c95997a3SFrancisco Iglesias 295c95997a3SFrancisco Iglesias /* In dual parallel, mirror low CS to both */ 296c95997a3SFrancisco Iglesias if (num_effective_busses(s) == 2) { 297c95997a3SFrancisco Iglesias /* Single bit chip-select for qspi */ 298c95997a3SFrancisco Iglesias field &= 0x1; 2990c4a94b8SFrancisco Iglesias field |= field << 3; 300c95997a3SFrancisco Iglesias /* Dual stack U-Page */ 301c95997a3SFrancisco Iglesias } else if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_TWO_MEM && 302c95997a3SFrancisco Iglesias s->regs[R_LQSPI_STS] & LQSPI_CFG_U_PAGE) { 303c95997a3SFrancisco Iglesias /* Single bit chip-select for qspi */ 304c95997a3SFrancisco Iglesias field &= 0x1; 305c95997a3SFrancisco Iglesias /* change from CS0 to CS1 */ 306c95997a3SFrancisco Iglesias field <<= 1; 307c95997a3SFrancisco Iglesias } 308c95997a3SFrancisco Iglesias /* Auto CS */ 309c95997a3SFrancisco Iglesias if (!(s->regs[R_CONFIG] & MANUAL_CS) && 310c95997a3SFrancisco Iglesias fifo8_is_empty(&s->tx_fifo)) { 311c95997a3SFrancisco Iglesias field = 0; 312c95997a3SFrancisco Iglesias } 313c95997a3SFrancisco Iglesias xilinx_spips_update_cs(s, field); 314c95997a3SFrancisco Iglesias } 315c95997a3SFrancisco Iglesias 31631e17060SPaolo Bonzini static void xilinx_spips_update_ixr(XilinxSPIPS *s) 31731e17060SPaolo Bonzini { 318c95997a3SFrancisco Iglesias if (!(s->regs[R_LQSPI_CFG] & LQSPI_CFG_LQ_MODE)) { 319c95997a3SFrancisco Iglesias s->regs[R_INTR_STATUS] &= ~IXR_SELF_CLEAR; 32031e17060SPaolo Bonzini s->regs[R_INTR_STATUS] |= 32131e17060SPaolo Bonzini (fifo8_is_full(&s->rx_fifo) ? IXR_RX_FIFO_FULL : 0) | 322c95997a3SFrancisco Iglesias (s->rx_fifo.num >= s->regs[R_RX_THRES] ? 323c95997a3SFrancisco Iglesias IXR_RX_FIFO_NOT_EMPTY : 0) | 32431e17060SPaolo Bonzini (fifo8_is_full(&s->tx_fifo) ? IXR_TX_FIFO_FULL : 0) | 325c95997a3SFrancisco Iglesias (fifo8_is_empty(&s->tx_fifo) ? IXR_TX_FIFO_EMPTY : 0) | 32631e17060SPaolo Bonzini (s->tx_fifo.num < s->regs[R_TX_THRES] ? IXR_TX_FIFO_NOT_FULL : 0); 327c95997a3SFrancisco Iglesias } 32831e17060SPaolo Bonzini int new_irqline = !!(s->regs[R_INTR_MASK] & s->regs[R_INTR_STATUS] & 32931e17060SPaolo Bonzini IXR_ALL); 33031e17060SPaolo Bonzini if (new_irqline != s->irqline) { 33131e17060SPaolo Bonzini s->irqline = new_irqline; 33231e17060SPaolo Bonzini qemu_set_irq(s->irq, s->irqline); 33331e17060SPaolo Bonzini } 33431e17060SPaolo Bonzini } 33531e17060SPaolo Bonzini 336c95997a3SFrancisco Iglesias static void xlnx_zynqmp_qspips_update_ixr(XlnxZynqMPQSPIPS *s) 337c95997a3SFrancisco Iglesias { 338c95997a3SFrancisco Iglesias uint32_t gqspi_int; 339c95997a3SFrancisco Iglesias int new_irqline; 340c95997a3SFrancisco Iglesias 341c95997a3SFrancisco Iglesias s->regs[R_GQSPI_ISR] &= ~IXR_SELF_CLEAR; 342c95997a3SFrancisco Iglesias s->regs[R_GQSPI_ISR] |= 343c95997a3SFrancisco Iglesias (fifo32_is_empty(&s->fifo_g) ? IXR_GENERIC_FIFO_EMPTY : 0) | 344c95997a3SFrancisco Iglesias (fifo32_is_full(&s->fifo_g) ? IXR_GENERIC_FIFO_FULL : 0) | 345c95997a3SFrancisco Iglesias (s->fifo_g.fifo.num < s->regs[R_GQSPI_GFIFO_THRESH] ? 346c95997a3SFrancisco Iglesias IXR_GENERIC_FIFO_NOT_FULL : 0) | 347c95997a3SFrancisco Iglesias (fifo8_is_empty(&s->rx_fifo_g) ? IXR_RX_FIFO_EMPTY : 0) | 348c95997a3SFrancisco Iglesias (fifo8_is_full(&s->rx_fifo_g) ? IXR_RX_FIFO_FULL : 0) | 349c95997a3SFrancisco Iglesias (s->rx_fifo_g.num >= s->regs[R_GQSPI_RX_THRESH] ? 350c95997a3SFrancisco Iglesias IXR_RX_FIFO_NOT_EMPTY : 0) | 351c95997a3SFrancisco Iglesias (fifo8_is_empty(&s->tx_fifo_g) ? IXR_TX_FIFO_EMPTY : 0) | 352c95997a3SFrancisco Iglesias (fifo8_is_full(&s->tx_fifo_g) ? IXR_TX_FIFO_FULL : 0) | 353c95997a3SFrancisco Iglesias (s->tx_fifo_g.num < s->regs[R_GQSPI_TX_THRESH] ? 354c95997a3SFrancisco Iglesias IXR_TX_FIFO_NOT_FULL : 0); 355c95997a3SFrancisco Iglesias 356c95997a3SFrancisco Iglesias /* GQSPI Interrupt Trigger Status */ 357c95997a3SFrancisco Iglesias gqspi_int = (~s->regs[R_GQSPI_IMR]) & s->regs[R_GQSPI_ISR] & GQSPI_IXR_MASK; 358c95997a3SFrancisco Iglesias new_irqline = !!(gqspi_int & IXR_ALL); 359c95997a3SFrancisco Iglesias 360c95997a3SFrancisco Iglesias /* drive external interrupt pin */ 361c95997a3SFrancisco Iglesias if (new_irqline != s->gqspi_irqline) { 362c95997a3SFrancisco Iglesias s->gqspi_irqline = new_irqline; 363c95997a3SFrancisco Iglesias qemu_set_irq(XILINX_SPIPS(s)->irq, s->gqspi_irqline); 364c95997a3SFrancisco Iglesias } 365c95997a3SFrancisco Iglesias } 366c95997a3SFrancisco Iglesias 36731e17060SPaolo Bonzini static void xilinx_spips_reset(DeviceState *d) 36831e17060SPaolo Bonzini { 36931e17060SPaolo Bonzini XilinxSPIPS *s = XILINX_SPIPS(d); 37031e17060SPaolo Bonzini 371d3c348b6SAlistair Francis memset(s->regs, 0, sizeof(s->regs)); 37231e17060SPaolo Bonzini 37331e17060SPaolo Bonzini fifo8_reset(&s->rx_fifo); 37431e17060SPaolo Bonzini fifo8_reset(&s->rx_fifo); 37531e17060SPaolo Bonzini /* non zero resets */ 37631e17060SPaolo Bonzini s->regs[R_CONFIG] |= MODEFAIL_GEN_EN; 37731e17060SPaolo Bonzini s->regs[R_SLAVE_IDLE_COUNT] = 0xFF; 37831e17060SPaolo Bonzini s->regs[R_TX_THRES] = 1; 37931e17060SPaolo Bonzini s->regs[R_RX_THRES] = 1; 38031e17060SPaolo Bonzini /* FIXME: move magic number definition somewhere sensible */ 38131e17060SPaolo Bonzini s->regs[R_MOD_ID] = 0x01090106; 38231e17060SPaolo Bonzini s->regs[R_LQSPI_CFG] = R_LQSPI_CFG_RESET; 383ef06ca39SFrancisco Iglesias s->link_state = 1; 384ef06ca39SFrancisco Iglesias s->link_state_next = 1; 385ef06ca39SFrancisco Iglesias s->link_state_next_when = 0; 38631e17060SPaolo Bonzini s->snoop_state = SNOOP_CHECKING; 387ef06ca39SFrancisco Iglesias s->cmd_dummies = 0; 388275e28ccSFrancisco Iglesias s->man_start_com = false; 38931e17060SPaolo Bonzini xilinx_spips_update_ixr(s); 39031e17060SPaolo Bonzini xilinx_spips_update_cs_lines(s); 39131e17060SPaolo Bonzini } 39231e17060SPaolo Bonzini 393c95997a3SFrancisco Iglesias static void xlnx_zynqmp_qspips_reset(DeviceState *d) 394c95997a3SFrancisco Iglesias { 395c95997a3SFrancisco Iglesias XlnxZynqMPQSPIPS *s = XLNX_ZYNQMP_QSPIPS(d); 396c95997a3SFrancisco Iglesias 397c95997a3SFrancisco Iglesias xilinx_spips_reset(d); 398c95997a3SFrancisco Iglesias 399d3c348b6SAlistair Francis memset(s->regs, 0, sizeof(s->regs)); 400d3c348b6SAlistair Francis 401c95997a3SFrancisco Iglesias fifo8_reset(&s->rx_fifo_g); 402c95997a3SFrancisco Iglesias fifo8_reset(&s->rx_fifo_g); 403c95997a3SFrancisco Iglesias fifo32_reset(&s->fifo_g); 4044f0da466SAlistair Francis s->regs[R_INTR_STATUS] = R_INTR_STATUS_RESET; 4054f0da466SAlistair Francis s->regs[R_GPIO] = 1; 4064f0da466SAlistair Francis s->regs[R_LPBK_DLY_ADJ] = R_LPBK_DLY_ADJ_RESET; 4074f0da466SAlistair Francis s->regs[R_GQSPI_GFIFO_THRESH] = 0x10; 4084f0da466SAlistair Francis s->regs[R_MOD_ID] = 0x01090101; 4094f0da466SAlistair Francis s->regs[R_GQSPI_IMR] = R_GQSPI_IMR_RESET; 410c95997a3SFrancisco Iglesias s->regs[R_GQSPI_TX_THRESH] = 1; 411c95997a3SFrancisco Iglesias s->regs[R_GQSPI_RX_THRESH] = 1; 4124f0da466SAlistair Francis s->regs[R_GQSPI_GPIO] = 1; 4134f0da466SAlistair Francis s->regs[R_GQSPI_LPBK_DLY_ADJ] = R_GQSPI_LPBK_DLY_ADJ_RESET; 4144f0da466SAlistair Francis s->regs[R_GQSPI_MOD_ID] = R_GQSPI_MOD_ID_RESET; 4154f0da466SAlistair Francis s->regs[R_QSPIDMA_DST_CTRL] = R_QSPIDMA_DST_CTRL_RESET; 4164f0da466SAlistair Francis s->regs[R_QSPIDMA_DST_I_MASK] = R_QSPIDMA_DST_I_MASK_RESET; 4174f0da466SAlistair Francis s->regs[R_QSPIDMA_DST_CTRL2] = R_QSPIDMA_DST_CTRL2_RESET; 418c95997a3SFrancisco Iglesias s->man_start_com_g = false; 419c95997a3SFrancisco Iglesias s->gqspi_irqline = 0; 420c95997a3SFrancisco Iglesias xlnx_zynqmp_qspips_update_ixr(s); 421c95997a3SFrancisco Iglesias } 422c95997a3SFrancisco Iglesias 423c3725b85SFrancisco Iglesias /* N way (num) in place bit striper. Lay out row wise bits (MSB to LSB) 4249151da25SPeter Crosthwaite * column wise (from element 0 to N-1). num is the length of x, and dir 4259151da25SPeter Crosthwaite * reverses the direction of the transform. Best illustrated by example: 4269151da25SPeter Crosthwaite * Each digit in the below array is a single bit (num == 3): 4279151da25SPeter Crosthwaite * 428c3725b85SFrancisco Iglesias * {{ 76543210, } ----- stripe (dir == false) -----> {{ 741gdaFC, } 429c3725b85SFrancisco Iglesias * { hgfedcba, } { 630fcHEB, } 430c3725b85SFrancisco Iglesias * { HGFEDCBA, }} <---- upstripe (dir == true) ----- { 52hebGDA, }} 4319151da25SPeter Crosthwaite */ 4329151da25SPeter Crosthwaite 4339151da25SPeter Crosthwaite static inline void stripe8(uint8_t *x, int num, bool dir) 4349151da25SPeter Crosthwaite { 435aa64cfaeSPeter Maydell uint8_t r[MAX_NUM_BUSSES]; 4369151da25SPeter Crosthwaite int idx[2] = {0, 0}; 437c3725b85SFrancisco Iglesias int bit[2] = {0, 7}; 4389151da25SPeter Crosthwaite int d = dir; 4399151da25SPeter Crosthwaite 440aa64cfaeSPeter Maydell assert(num <= MAX_NUM_BUSSES); 441aa64cfaeSPeter Maydell memset(r, 0, sizeof(uint8_t) * num); 442aa64cfaeSPeter Maydell 4439151da25SPeter Crosthwaite for (idx[0] = 0; idx[0] < num; ++idx[0]) { 444c3725b85SFrancisco Iglesias for (bit[0] = 7; bit[0] >= 0; bit[0]--) { 445c3725b85SFrancisco Iglesias r[idx[!d]] |= x[idx[d]] & 1 << bit[d] ? 1 << bit[!d] : 0; 4469151da25SPeter Crosthwaite idx[1] = (idx[1] + 1) % num; 4479151da25SPeter Crosthwaite if (!idx[1]) { 448c3725b85SFrancisco Iglesias bit[1]--; 4499151da25SPeter Crosthwaite } 4509151da25SPeter Crosthwaite } 4519151da25SPeter Crosthwaite } 4529151da25SPeter Crosthwaite memcpy(x, r, sizeof(uint8_t) * num); 4539151da25SPeter Crosthwaite } 4549151da25SPeter Crosthwaite 455c95997a3SFrancisco Iglesias static void xlnx_zynqmp_qspips_flush_fifo_g(XlnxZynqMPQSPIPS *s) 456c95997a3SFrancisco Iglesias { 457c95997a3SFrancisco Iglesias while (s->regs[R_GQSPI_DATA_STS] || !fifo32_is_empty(&s->fifo_g)) { 458c95997a3SFrancisco Iglesias uint8_t tx_rx[2] = { 0 }; 459c95997a3SFrancisco Iglesias int num_stripes = 1; 460c95997a3SFrancisco Iglesias uint8_t busses; 461c95997a3SFrancisco Iglesias int i; 462c95997a3SFrancisco Iglesias 463c95997a3SFrancisco Iglesias if (!s->regs[R_GQSPI_DATA_STS]) { 464c95997a3SFrancisco Iglesias uint8_t imm; 465c95997a3SFrancisco Iglesias 466c95997a3SFrancisco Iglesias s->regs[R_GQSPI_GF_SNAPSHOT] = fifo32_pop(&s->fifo_g); 467c95997a3SFrancisco Iglesias DB_PRINT_L(0, "GQSPI command: %x\n", s->regs[R_GQSPI_GF_SNAPSHOT]); 468c95997a3SFrancisco Iglesias if (!s->regs[R_GQSPI_GF_SNAPSHOT]) { 469c95997a3SFrancisco Iglesias DB_PRINT_L(0, "Dummy GQSPI Delay Command Entry, Do nothing"); 470c95997a3SFrancisco Iglesias continue; 471c95997a3SFrancisco Iglesias } 472c95997a3SFrancisco Iglesias xlnx_zynqmp_qspips_update_cs_lines(s); 473c95997a3SFrancisco Iglesias 474c95997a3SFrancisco Iglesias imm = ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, IMMEDIATE_DATA); 475c95997a3SFrancisco Iglesias if (!ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, DATA_XFER)) { 476c95997a3SFrancisco Iglesias /* immedate transfer */ 477c95997a3SFrancisco Iglesias if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, TRANSMIT) || 478c95997a3SFrancisco Iglesias ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, RECIEVE)) { 479c95997a3SFrancisco Iglesias s->regs[R_GQSPI_DATA_STS] = 1; 480c95997a3SFrancisco Iglesias /* CS setup/hold - do nothing */ 481c95997a3SFrancisco Iglesias } else { 482c95997a3SFrancisco Iglesias s->regs[R_GQSPI_DATA_STS] = 0; 483c95997a3SFrancisco Iglesias } 484c95997a3SFrancisco Iglesias } else if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, EXPONENT)) { 485c95997a3SFrancisco Iglesias if (imm > 31) { 486c95997a3SFrancisco Iglesias qemu_log_mask(LOG_UNIMP, "QSPI exponential transfer too" 487c95997a3SFrancisco Iglesias " long - 2 ^ %" PRId8 " requested\n", imm); 488c95997a3SFrancisco Iglesias } 489c95997a3SFrancisco Iglesias s->regs[R_GQSPI_DATA_STS] = 1ul << imm; 490c95997a3SFrancisco Iglesias } else { 491c95997a3SFrancisco Iglesias s->regs[R_GQSPI_DATA_STS] = imm; 492c95997a3SFrancisco Iglesias } 493c95997a3SFrancisco Iglesias } 494c95997a3SFrancisco Iglesias /* Zero length transfer check */ 495c95997a3SFrancisco Iglesias if (!s->regs[R_GQSPI_DATA_STS]) { 496c95997a3SFrancisco Iglesias continue; 497c95997a3SFrancisco Iglesias } 498c95997a3SFrancisco Iglesias if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, RECIEVE) && 499c95997a3SFrancisco Iglesias fifo8_is_full(&s->rx_fifo_g)) { 500c95997a3SFrancisco Iglesias /* No space in RX fifo for transfer - try again later */ 501c95997a3SFrancisco Iglesias return; 502c95997a3SFrancisco Iglesias } 503c95997a3SFrancisco Iglesias if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, STRIPE) && 504c95997a3SFrancisco Iglesias (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, TRANSMIT) || 505c95997a3SFrancisco Iglesias ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, RECIEVE))) { 506c95997a3SFrancisco Iglesias num_stripes = 2; 507c95997a3SFrancisco Iglesias } 508c95997a3SFrancisco Iglesias if (!ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, DATA_XFER)) { 509c95997a3SFrancisco Iglesias tx_rx[0] = ARRAY_FIELD_EX32(s->regs, 510c95997a3SFrancisco Iglesias GQSPI_GF_SNAPSHOT, IMMEDIATE_DATA); 511c95997a3SFrancisco Iglesias } else if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, TRANSMIT)) { 512c95997a3SFrancisco Iglesias for (i = 0; i < num_stripes; ++i) { 513c95997a3SFrancisco Iglesias if (!fifo8_is_empty(&s->tx_fifo_g)) { 514c95997a3SFrancisco Iglesias tx_rx[i] = fifo8_pop(&s->tx_fifo_g); 515c95997a3SFrancisco Iglesias s->tx_fifo_g_align++; 516c95997a3SFrancisco Iglesias } else { 517c95997a3SFrancisco Iglesias return; 518c95997a3SFrancisco Iglesias } 519c95997a3SFrancisco Iglesias } 520c95997a3SFrancisco Iglesias } 521c95997a3SFrancisco Iglesias if (num_stripes == 1) { 522c95997a3SFrancisco Iglesias /* mirror */ 523c95997a3SFrancisco Iglesias tx_rx[1] = tx_rx[0]; 524c95997a3SFrancisco Iglesias } 525c95997a3SFrancisco Iglesias busses = ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, DATA_BUS_SELECT); 526c95997a3SFrancisco Iglesias for (i = 0; i < 2; ++i) { 527c95997a3SFrancisco Iglesias DB_PRINT_L(1, "bus %d tx = %02x\n", i, tx_rx[i]); 528c95997a3SFrancisco Iglesias tx_rx[i] = ssi_transfer(XILINX_SPIPS(s)->spi[i], tx_rx[i]); 529c95997a3SFrancisco Iglesias DB_PRINT_L(1, "bus %d rx = %02x\n", i, tx_rx[i]); 530c95997a3SFrancisco Iglesias } 531c95997a3SFrancisco Iglesias if (s->regs[R_GQSPI_DATA_STS] > 1 && 532c95997a3SFrancisco Iglesias busses == 0x3 && num_stripes == 2) { 533c95997a3SFrancisco Iglesias s->regs[R_GQSPI_DATA_STS] -= 2; 534c95997a3SFrancisco Iglesias } else if (s->regs[R_GQSPI_DATA_STS] > 0) { 535c95997a3SFrancisco Iglesias s->regs[R_GQSPI_DATA_STS]--; 536c95997a3SFrancisco Iglesias } 537c95997a3SFrancisco Iglesias if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, RECIEVE)) { 538c95997a3SFrancisco Iglesias for (i = 0; i < 2; ++i) { 539c95997a3SFrancisco Iglesias if (busses & (1 << i)) { 540c95997a3SFrancisco Iglesias DB_PRINT_L(1, "bus %d push_byte = %02x\n", i, tx_rx[i]); 541c95997a3SFrancisco Iglesias fifo8_push(&s->rx_fifo_g, tx_rx[i]); 542c95997a3SFrancisco Iglesias s->rx_fifo_g_align++; 543c95997a3SFrancisco Iglesias } 544c95997a3SFrancisco Iglesias } 545c95997a3SFrancisco Iglesias } 546c95997a3SFrancisco Iglesias if (!s->regs[R_GQSPI_DATA_STS]) { 547c95997a3SFrancisco Iglesias for (; s->tx_fifo_g_align % 4; s->tx_fifo_g_align++) { 548c95997a3SFrancisco Iglesias fifo8_pop(&s->tx_fifo_g); 549c95997a3SFrancisco Iglesias } 550c95997a3SFrancisco Iglesias for (; s->rx_fifo_g_align % 4; s->rx_fifo_g_align++) { 551c95997a3SFrancisco Iglesias fifo8_push(&s->rx_fifo_g, 0); 552c95997a3SFrancisco Iglesias } 553c95997a3SFrancisco Iglesias } 554c95997a3SFrancisco Iglesias } 555c95997a3SFrancisco Iglesias } 556c95997a3SFrancisco Iglesias 557ef06ca39SFrancisco Iglesias static int xilinx_spips_num_dummies(XilinxQSPIPS *qs, uint8_t command) 558ef06ca39SFrancisco Iglesias { 559ef06ca39SFrancisco Iglesias if (!qs) { 560ef06ca39SFrancisco Iglesias /* The SPI device is not a QSPI device */ 561ef06ca39SFrancisco Iglesias return -1; 562ef06ca39SFrancisco Iglesias } 563ef06ca39SFrancisco Iglesias 564ef06ca39SFrancisco Iglesias switch (command) { /* check for dummies */ 565ef06ca39SFrancisco Iglesias case READ: /* no dummy bytes/cycles */ 566ef06ca39SFrancisco Iglesias case PP: 567ef06ca39SFrancisco Iglesias case DPP: 568ef06ca39SFrancisco Iglesias case QPP: 569ef06ca39SFrancisco Iglesias case READ_4: 570ef06ca39SFrancisco Iglesias case PP_4: 571ef06ca39SFrancisco Iglesias case QPP_4: 572ef06ca39SFrancisco Iglesias return 0; 573ef06ca39SFrancisco Iglesias case FAST_READ: 574ef06ca39SFrancisco Iglesias case DOR: 575ef06ca39SFrancisco Iglesias case QOR: 576ef06ca39SFrancisco Iglesias case DOR_4: 577ef06ca39SFrancisco Iglesias case QOR_4: 578ef06ca39SFrancisco Iglesias return 1; 579ef06ca39SFrancisco Iglesias case DIOR: 580ef06ca39SFrancisco Iglesias case FAST_READ_4: 581ef06ca39SFrancisco Iglesias case DIOR_4: 582ef06ca39SFrancisco Iglesias return 2; 583ef06ca39SFrancisco Iglesias case QIOR: 584ef06ca39SFrancisco Iglesias case QIOR_4: 585b8cc8503SFrancisco Iglesias return 4; 586ef06ca39SFrancisco Iglesias default: 587ef06ca39SFrancisco Iglesias return -1; 588ef06ca39SFrancisco Iglesias } 589ef06ca39SFrancisco Iglesias } 590ef06ca39SFrancisco Iglesias 591ef06ca39SFrancisco Iglesias static inline uint8_t get_addr_length(XilinxSPIPS *s, uint8_t cmd) 592ef06ca39SFrancisco Iglesias { 593ef06ca39SFrancisco Iglesias switch (cmd) { 594ef06ca39SFrancisco Iglesias case PP_4: 595ef06ca39SFrancisco Iglesias case QPP_4: 596ef06ca39SFrancisco Iglesias case READ_4: 597ef06ca39SFrancisco Iglesias case QIOR_4: 598ef06ca39SFrancisco Iglesias case FAST_READ_4: 599ef06ca39SFrancisco Iglesias case DOR_4: 600ef06ca39SFrancisco Iglesias case QOR_4: 601ef06ca39SFrancisco Iglesias case DIOR_4: 602ef06ca39SFrancisco Iglesias return 4; 603ef06ca39SFrancisco Iglesias default: 604ef06ca39SFrancisco Iglesias return (s->regs[R_CMND] & R_CMND_EXT_ADD) ? 4 : 3; 605ef06ca39SFrancisco Iglesias } 606ef06ca39SFrancisco Iglesias } 607ef06ca39SFrancisco Iglesias 60831e17060SPaolo Bonzini static void xilinx_spips_flush_txfifo(XilinxSPIPS *s) 60931e17060SPaolo Bonzini { 6104a5b6fa8SPeter Crosthwaite int debug_level = 0; 611ef06ca39SFrancisco Iglesias XilinxQSPIPS *q = (XilinxQSPIPS *) object_dynamic_cast(OBJECT(s), 612ef06ca39SFrancisco Iglesias TYPE_XILINX_QSPIPS); 6134a5b6fa8SPeter Crosthwaite 61431e17060SPaolo Bonzini for (;;) { 61531e17060SPaolo Bonzini int i; 61631e17060SPaolo Bonzini uint8_t tx = 0; 617fbe5dac7SFrancisco Iglesias uint8_t tx_rx[MAX_NUM_BUSSES] = { 0 }; 618ef06ca39SFrancisco Iglesias uint8_t dummy_cycles = 0; 619ef06ca39SFrancisco Iglesias uint8_t addr_length; 62031e17060SPaolo Bonzini 62131e17060SPaolo Bonzini if (fifo8_is_empty(&s->tx_fifo)) { 62231e17060SPaolo Bonzini xilinx_spips_update_ixr(s); 62331e17060SPaolo Bonzini return; 624fbf32752SSai Pavan Boddu } else if (s->snoop_state == SNOOP_STRIPING || 625fbf32752SSai Pavan Boddu s->snoop_state == SNOOP_NONE) { 6269151da25SPeter Crosthwaite for (i = 0; i < num_effective_busses(s); ++i) { 6279151da25SPeter Crosthwaite tx_rx[i] = fifo8_pop(&s->tx_fifo); 6289151da25SPeter Crosthwaite } 6299151da25SPeter Crosthwaite stripe8(tx_rx, num_effective_busses(s), false); 630ef06ca39SFrancisco Iglesias } else if (s->snoop_state >= SNOOP_ADDR) { 63131e17060SPaolo Bonzini tx = fifo8_pop(&s->tx_fifo); 6329151da25SPeter Crosthwaite for (i = 0; i < num_effective_busses(s); ++i) { 6339151da25SPeter Crosthwaite tx_rx[i] = tx; 63431e17060SPaolo Bonzini } 635ef06ca39SFrancisco Iglesias } else { 636ef06ca39SFrancisco Iglesias /* Extract a dummy byte and generate dummy cycles according to the 637ef06ca39SFrancisco Iglesias * link state */ 638ef06ca39SFrancisco Iglesias tx = fifo8_pop(&s->tx_fifo); 639ef06ca39SFrancisco Iglesias dummy_cycles = 8 / s->link_state; 64031e17060SPaolo Bonzini } 6419151da25SPeter Crosthwaite 6429151da25SPeter Crosthwaite for (i = 0; i < num_effective_busses(s); ++i) { 643c3725b85SFrancisco Iglesias int bus = num_effective_busses(s) - 1 - i; 644ef06ca39SFrancisco Iglesias if (dummy_cycles) { 645ef06ca39SFrancisco Iglesias int d; 646ef06ca39SFrancisco Iglesias for (d = 0; d < dummy_cycles; ++d) { 647ef06ca39SFrancisco Iglesias tx_rx[0] = ssi_transfer(s->spi[bus], (uint32_t)tx_rx[0]); 648ef06ca39SFrancisco Iglesias } 649ef06ca39SFrancisco Iglesias } else { 6504a5b6fa8SPeter Crosthwaite DB_PRINT_L(debug_level, "tx = %02x\n", tx_rx[i]); 651c3725b85SFrancisco Iglesias tx_rx[i] = ssi_transfer(s->spi[bus], (uint32_t)tx_rx[i]); 6524a5b6fa8SPeter Crosthwaite DB_PRINT_L(debug_level, "rx = %02x\n", tx_rx[i]); 6539151da25SPeter Crosthwaite } 654ef06ca39SFrancisco Iglesias } 6559151da25SPeter Crosthwaite 656ef06ca39SFrancisco Iglesias if (s->regs[R_CMND] & R_CMND_RXFIFO_DRAIN) { 657ef06ca39SFrancisco Iglesias DB_PRINT_L(debug_level, "dircarding drained rx byte\n"); 658ef06ca39SFrancisco Iglesias /* Do nothing */ 659ef06ca39SFrancisco Iglesias } else if (s->rx_discard) { 660ef06ca39SFrancisco Iglesias DB_PRINT_L(debug_level, "dircarding discarded rx byte\n"); 661ef06ca39SFrancisco Iglesias s->rx_discard -= 8 / s->link_state; 662ef06ca39SFrancisco Iglesias } else if (fifo8_is_full(&s->rx_fifo)) { 66331e17060SPaolo Bonzini s->regs[R_INTR_STATUS] |= IXR_RX_FIFO_OVERFLOW; 6644a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "rx FIFO overflow"); 6659151da25SPeter Crosthwaite } else if (s->snoop_state == SNOOP_STRIPING) { 6669151da25SPeter Crosthwaite stripe8(tx_rx, num_effective_busses(s), true); 6679151da25SPeter Crosthwaite for (i = 0; i < num_effective_busses(s); ++i) { 6689151da25SPeter Crosthwaite fifo8_push(&s->rx_fifo, (uint8_t)tx_rx[i]); 669ef06ca39SFrancisco Iglesias DB_PRINT_L(debug_level, "pushing striped rx byte\n"); 6709151da25SPeter Crosthwaite } 67131e17060SPaolo Bonzini } else { 672ef06ca39SFrancisco Iglesias DB_PRINT_L(debug_level, "pushing unstriped rx byte\n"); 6739151da25SPeter Crosthwaite fifo8_push(&s->rx_fifo, (uint8_t)tx_rx[0]); 67431e17060SPaolo Bonzini } 67531e17060SPaolo Bonzini 676ef06ca39SFrancisco Iglesias if (s->link_state_next_when) { 677ef06ca39SFrancisco Iglesias s->link_state_next_when--; 678ef06ca39SFrancisco Iglesias if (!s->link_state_next_when) { 679ef06ca39SFrancisco Iglesias s->link_state = s->link_state_next; 680ef06ca39SFrancisco Iglesias } 681ef06ca39SFrancisco Iglesias } 682ef06ca39SFrancisco Iglesias 6834a5b6fa8SPeter Crosthwaite DB_PRINT_L(debug_level, "initial snoop state: %x\n", 6844a5b6fa8SPeter Crosthwaite (unsigned)s->snoop_state); 68531e17060SPaolo Bonzini switch (s->snoop_state) { 68631e17060SPaolo Bonzini case (SNOOP_CHECKING): 687ef06ca39SFrancisco Iglesias /* Store the count of dummy bytes in the txfifo */ 688ef06ca39SFrancisco Iglesias s->cmd_dummies = xilinx_spips_num_dummies(q, tx); 689ef06ca39SFrancisco Iglesias addr_length = get_addr_length(s, tx); 690ef06ca39SFrancisco Iglesias if (s->cmd_dummies < 0) { 69131e17060SPaolo Bonzini s->snoop_state = SNOOP_NONE; 692ef06ca39SFrancisco Iglesias } else { 693ef06ca39SFrancisco Iglesias s->snoop_state = SNOOP_ADDR + addr_length - 1; 694ef06ca39SFrancisco Iglesias } 695ef06ca39SFrancisco Iglesias switch (tx) { 696ef06ca39SFrancisco Iglesias case DPP: 697ef06ca39SFrancisco Iglesias case DOR: 698ef06ca39SFrancisco Iglesias case DOR_4: 699ef06ca39SFrancisco Iglesias s->link_state_next = 2; 700ef06ca39SFrancisco Iglesias s->link_state_next_when = addr_length + s->cmd_dummies; 701ef06ca39SFrancisco Iglesias break; 702ef06ca39SFrancisco Iglesias case QPP: 703ef06ca39SFrancisco Iglesias case QPP_4: 704ef06ca39SFrancisco Iglesias case QOR: 705ef06ca39SFrancisco Iglesias case QOR_4: 706ef06ca39SFrancisco Iglesias s->link_state_next = 4; 707ef06ca39SFrancisco Iglesias s->link_state_next_when = addr_length + s->cmd_dummies; 708ef06ca39SFrancisco Iglesias break; 709ef06ca39SFrancisco Iglesias case DIOR: 710ef06ca39SFrancisco Iglesias case DIOR_4: 711ef06ca39SFrancisco Iglesias s->link_state = 2; 712ef06ca39SFrancisco Iglesias break; 713ef06ca39SFrancisco Iglesias case QIOR: 714ef06ca39SFrancisco Iglesias case QIOR_4: 715ef06ca39SFrancisco Iglesias s->link_state = 4; 716ef06ca39SFrancisco Iglesias break; 717ef06ca39SFrancisco Iglesias } 718ef06ca39SFrancisco Iglesias break; 719ef06ca39SFrancisco Iglesias case (SNOOP_ADDR): 720ef06ca39SFrancisco Iglesias /* Address has been transmitted, transmit dummy cycles now if 721ef06ca39SFrancisco Iglesias * needed */ 722ef06ca39SFrancisco Iglesias if (s->cmd_dummies < 0) { 723ef06ca39SFrancisco Iglesias s->snoop_state = SNOOP_NONE; 724ef06ca39SFrancisco Iglesias } else { 725ef06ca39SFrancisco Iglesias s->snoop_state = s->cmd_dummies; 72631e17060SPaolo Bonzini } 72731e17060SPaolo Bonzini break; 72831e17060SPaolo Bonzini case (SNOOP_STRIPING): 72931e17060SPaolo Bonzini case (SNOOP_NONE): 7304a5b6fa8SPeter Crosthwaite /* Once we hit the boring stuff - squelch debug noise */ 7314a5b6fa8SPeter Crosthwaite if (!debug_level) { 7324a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "squelching debug info ....\n"); 7334a5b6fa8SPeter Crosthwaite debug_level = 1; 7344a5b6fa8SPeter Crosthwaite } 73531e17060SPaolo Bonzini break; 73631e17060SPaolo Bonzini default: 73731e17060SPaolo Bonzini s->snoop_state--; 73831e17060SPaolo Bonzini } 7394a5b6fa8SPeter Crosthwaite DB_PRINT_L(debug_level, "final snoop state: %x\n", 7404a5b6fa8SPeter Crosthwaite (unsigned)s->snoop_state); 74131e17060SPaolo Bonzini } 74231e17060SPaolo Bonzini } 74331e17060SPaolo Bonzini 7442fdd171eSFrancisco Iglesias static inline void tx_data_bytes(Fifo8 *fifo, uint32_t value, int num, bool be) 7452fdd171eSFrancisco Iglesias { 7462fdd171eSFrancisco Iglesias int i; 7472fdd171eSFrancisco Iglesias for (i = 0; i < num && !fifo8_is_full(fifo); ++i) { 7482fdd171eSFrancisco Iglesias if (be) { 7492fdd171eSFrancisco Iglesias fifo8_push(fifo, (uint8_t)(value >> 24)); 7502fdd171eSFrancisco Iglesias value <<= 8; 7512fdd171eSFrancisco Iglesias } else { 7522fdd171eSFrancisco Iglesias fifo8_push(fifo, (uint8_t)value); 7532fdd171eSFrancisco Iglesias value >>= 8; 7542fdd171eSFrancisco Iglesias } 7552fdd171eSFrancisco Iglesias } 7562fdd171eSFrancisco Iglesias } 7572fdd171eSFrancisco Iglesias 758275e28ccSFrancisco Iglesias static void xilinx_spips_check_zero_pump(XilinxSPIPS *s) 759275e28ccSFrancisco Iglesias { 760275e28ccSFrancisco Iglesias if (!s->regs[R_TRANSFER_SIZE]) { 761275e28ccSFrancisco Iglesias return; 762275e28ccSFrancisco Iglesias } 763275e28ccSFrancisco Iglesias if (!fifo8_is_empty(&s->tx_fifo) && s->regs[R_CMND] & R_CMND_PUSH_WAIT) { 764275e28ccSFrancisco Iglesias return; 765275e28ccSFrancisco Iglesias } 766275e28ccSFrancisco Iglesias /* 767275e28ccSFrancisco Iglesias * The zero pump must never fill tx fifo such that rx overflow is 768275e28ccSFrancisco Iglesias * possible 769275e28ccSFrancisco Iglesias */ 770275e28ccSFrancisco Iglesias while (s->regs[R_TRANSFER_SIZE] && 771275e28ccSFrancisco Iglesias s->rx_fifo.num + s->tx_fifo.num < RXFF_A_Q - 3) { 772275e28ccSFrancisco Iglesias /* endianess just doesn't matter when zero pumping */ 773275e28ccSFrancisco Iglesias tx_data_bytes(&s->tx_fifo, 0, 4, false); 774275e28ccSFrancisco Iglesias s->regs[R_TRANSFER_SIZE] &= ~0x03ull; 775275e28ccSFrancisco Iglesias s->regs[R_TRANSFER_SIZE] -= 4; 776275e28ccSFrancisco Iglesias } 777275e28ccSFrancisco Iglesias } 778275e28ccSFrancisco Iglesias 779275e28ccSFrancisco Iglesias static void xilinx_spips_check_flush(XilinxSPIPS *s) 780275e28ccSFrancisco Iglesias { 781275e28ccSFrancisco Iglesias if (s->man_start_com || 782275e28ccSFrancisco Iglesias (!fifo8_is_empty(&s->tx_fifo) && 783275e28ccSFrancisco Iglesias !(s->regs[R_CONFIG] & MAN_START_EN))) { 784275e28ccSFrancisco Iglesias xilinx_spips_check_zero_pump(s); 785275e28ccSFrancisco Iglesias xilinx_spips_flush_txfifo(s); 786275e28ccSFrancisco Iglesias } 787275e28ccSFrancisco Iglesias if (fifo8_is_empty(&s->tx_fifo) && !s->regs[R_TRANSFER_SIZE]) { 788275e28ccSFrancisco Iglesias s->man_start_com = false; 789275e28ccSFrancisco Iglesias } 790275e28ccSFrancisco Iglesias xilinx_spips_update_ixr(s); 791275e28ccSFrancisco Iglesias } 792275e28ccSFrancisco Iglesias 793c95997a3SFrancisco Iglesias static void xlnx_zynqmp_qspips_check_flush(XlnxZynqMPQSPIPS *s) 794c95997a3SFrancisco Iglesias { 795c95997a3SFrancisco Iglesias bool gqspi_has_work = s->regs[R_GQSPI_DATA_STS] || 796c95997a3SFrancisco Iglesias !fifo32_is_empty(&s->fifo_g); 797c95997a3SFrancisco Iglesias 798c95997a3SFrancisco Iglesias if (ARRAY_FIELD_EX32(s->regs, GQSPI_SELECT, GENERIC_QSPI_EN)) { 799c95997a3SFrancisco Iglesias if (s->man_start_com_g || (gqspi_has_work && 800c95997a3SFrancisco Iglesias !ARRAY_FIELD_EX32(s->regs, GQSPI_CNFG, GEN_FIFO_START_MODE))) { 801c95997a3SFrancisco Iglesias xlnx_zynqmp_qspips_flush_fifo_g(s); 802c95997a3SFrancisco Iglesias } 803c95997a3SFrancisco Iglesias } else { 804c95997a3SFrancisco Iglesias xilinx_spips_check_flush(XILINX_SPIPS(s)); 805c95997a3SFrancisco Iglesias } 806c95997a3SFrancisco Iglesias if (!gqspi_has_work) { 807c95997a3SFrancisco Iglesias s->man_start_com_g = false; 808c95997a3SFrancisco Iglesias } 809c95997a3SFrancisco Iglesias xlnx_zynqmp_qspips_update_ixr(s); 810c95997a3SFrancisco Iglesias } 811c95997a3SFrancisco Iglesias 8122fdd171eSFrancisco Iglesias static inline int rx_data_bytes(Fifo8 *fifo, uint8_t *value, int max) 81331e17060SPaolo Bonzini { 81431e17060SPaolo Bonzini int i; 81531e17060SPaolo Bonzini 8162fdd171eSFrancisco Iglesias for (i = 0; i < max && !fifo8_is_empty(fifo); ++i) { 8172fdd171eSFrancisco Iglesias value[i] = fifo8_pop(fifo); 81831e17060SPaolo Bonzini } 8192fdd171eSFrancisco Iglesias return max - i; 82031e17060SPaolo Bonzini } 82131e17060SPaolo Bonzini 822c95997a3SFrancisco Iglesias static const void *pop_buf(Fifo8 *fifo, uint32_t max, uint32_t *num) 823c95997a3SFrancisco Iglesias { 824c95997a3SFrancisco Iglesias void *ret; 825c95997a3SFrancisco Iglesias 826c95997a3SFrancisco Iglesias if (max == 0 || max > fifo->num) { 827c95997a3SFrancisco Iglesias abort(); 828c95997a3SFrancisco Iglesias } 829c95997a3SFrancisco Iglesias *num = MIN(fifo->capacity - fifo->head, max); 830c95997a3SFrancisco Iglesias ret = &fifo->data[fifo->head]; 831c95997a3SFrancisco Iglesias fifo->head += *num; 832c95997a3SFrancisco Iglesias fifo->head %= fifo->capacity; 833c95997a3SFrancisco Iglesias fifo->num -= *num; 834c95997a3SFrancisco Iglesias return ret; 835c95997a3SFrancisco Iglesias } 836c95997a3SFrancisco Iglesias 837c95997a3SFrancisco Iglesias static void xlnx_zynqmp_qspips_notify(void *opaque) 838c95997a3SFrancisco Iglesias { 839c95997a3SFrancisco Iglesias XlnxZynqMPQSPIPS *rq = XLNX_ZYNQMP_QSPIPS(opaque); 840c95997a3SFrancisco Iglesias XilinxSPIPS *s = XILINX_SPIPS(rq); 841c95997a3SFrancisco Iglesias Fifo8 *recv_fifo; 842c95997a3SFrancisco Iglesias 843c95997a3SFrancisco Iglesias if (ARRAY_FIELD_EX32(rq->regs, GQSPI_SELECT, GENERIC_QSPI_EN)) { 844c95997a3SFrancisco Iglesias if (!(ARRAY_FIELD_EX32(rq->regs, GQSPI_CNFG, MODE_EN) == 2)) { 845c95997a3SFrancisco Iglesias return; 846c95997a3SFrancisco Iglesias } 847c95997a3SFrancisco Iglesias recv_fifo = &rq->rx_fifo_g; 848c95997a3SFrancisco Iglesias } else { 849c95997a3SFrancisco Iglesias if (!(s->regs[R_CMND] & R_CMND_DMA_EN)) { 850c95997a3SFrancisco Iglesias return; 851c95997a3SFrancisco Iglesias } 852c95997a3SFrancisco Iglesias recv_fifo = &s->rx_fifo; 853c95997a3SFrancisco Iglesias } 854c95997a3SFrancisco Iglesias while (recv_fifo->num >= 4 855c95997a3SFrancisco Iglesias && stream_can_push(rq->dma, xlnx_zynqmp_qspips_notify, rq)) 856c95997a3SFrancisco Iglesias { 857c95997a3SFrancisco Iglesias size_t ret; 858c95997a3SFrancisco Iglesias uint32_t num; 85921d887cdSSai Pavan Boddu const void *rxd; 86021d887cdSSai Pavan Boddu int len; 86121d887cdSSai Pavan Boddu 86221d887cdSSai Pavan Boddu len = recv_fifo->num >= rq->dma_burst_size ? rq->dma_burst_size : 86321d887cdSSai Pavan Boddu recv_fifo->num; 86421d887cdSSai Pavan Boddu rxd = pop_buf(recv_fifo, len, &num); 865c95997a3SFrancisco Iglesias 866c95997a3SFrancisco Iglesias memcpy(rq->dma_buf, rxd, num); 867c95997a3SFrancisco Iglesias 86821d887cdSSai Pavan Boddu ret = stream_push(rq->dma, rq->dma_buf, num); 86921d887cdSSai Pavan Boddu assert(ret == num); 870c95997a3SFrancisco Iglesias xlnx_zynqmp_qspips_check_flush(rq); 871c95997a3SFrancisco Iglesias } 872c95997a3SFrancisco Iglesias } 873c95997a3SFrancisco Iglesias 87431e17060SPaolo Bonzini static uint64_t xilinx_spips_read(void *opaque, hwaddr addr, 87531e17060SPaolo Bonzini unsigned size) 87631e17060SPaolo Bonzini { 87731e17060SPaolo Bonzini XilinxSPIPS *s = opaque; 87831e17060SPaolo Bonzini uint32_t mask = ~0; 87931e17060SPaolo Bonzini uint32_t ret; 880b0b7ae62SPeter Crosthwaite uint8_t rx_buf[4]; 8812fdd171eSFrancisco Iglesias int shortfall; 88231e17060SPaolo Bonzini 88331e17060SPaolo Bonzini addr >>= 2; 88431e17060SPaolo Bonzini switch (addr) { 88531e17060SPaolo Bonzini case R_CONFIG: 8862133a5f6SPeter Crosthwaite mask = ~(R_CONFIG_RSVD | MAN_START_COM); 88731e17060SPaolo Bonzini break; 88831e17060SPaolo Bonzini case R_INTR_STATUS: 88987920b44SPeter Crosthwaite ret = s->regs[addr] & IXR_ALL; 89087920b44SPeter Crosthwaite s->regs[addr] = 0; 8914a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret); 8922e1cf2c9SFrancisco Iglesias xilinx_spips_update_ixr(s); 89387920b44SPeter Crosthwaite return ret; 89431e17060SPaolo Bonzini case R_INTR_MASK: 89531e17060SPaolo Bonzini mask = IXR_ALL; 89631e17060SPaolo Bonzini break; 89731e17060SPaolo Bonzini case R_EN: 89831e17060SPaolo Bonzini mask = 0x1; 89931e17060SPaolo Bonzini break; 90031e17060SPaolo Bonzini case R_SLAVE_IDLE_COUNT: 90131e17060SPaolo Bonzini mask = 0xFF; 90231e17060SPaolo Bonzini break; 90331e17060SPaolo Bonzini case R_MOD_ID: 90431e17060SPaolo Bonzini mask = 0x01FFFFFF; 90531e17060SPaolo Bonzini break; 90631e17060SPaolo Bonzini case R_INTR_EN: 90731e17060SPaolo Bonzini case R_INTR_DIS: 90831e17060SPaolo Bonzini case R_TX_DATA: 90931e17060SPaolo Bonzini mask = 0; 91031e17060SPaolo Bonzini break; 91131e17060SPaolo Bonzini case R_RX_DATA: 912b0b7ae62SPeter Crosthwaite memset(rx_buf, 0, sizeof(rx_buf)); 9132fdd171eSFrancisco Iglesias shortfall = rx_data_bytes(&s->rx_fifo, rx_buf, s->num_txrx_bytes); 9142fdd171eSFrancisco Iglesias ret = s->regs[R_CONFIG] & R_CONFIG_ENDIAN ? 9152fdd171eSFrancisco Iglesias cpu_to_be32(*(uint32_t *)rx_buf) : 9162fdd171eSFrancisco Iglesias cpu_to_le32(*(uint32_t *)rx_buf); 9172fdd171eSFrancisco Iglesias if (!(s->regs[R_CONFIG] & R_CONFIG_ENDIAN)) { 9182fdd171eSFrancisco Iglesias ret <<= 8 * shortfall; 9192fdd171eSFrancisco Iglesias } 9204a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret); 921c95997a3SFrancisco Iglesias xilinx_spips_check_flush(s); 92231e17060SPaolo Bonzini xilinx_spips_update_ixr(s); 92331e17060SPaolo Bonzini return ret; 92431e17060SPaolo Bonzini } 9254a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4, 9264a5b6fa8SPeter Crosthwaite s->regs[addr] & mask); 92731e17060SPaolo Bonzini return s->regs[addr] & mask; 92831e17060SPaolo Bonzini 92931e17060SPaolo Bonzini } 93031e17060SPaolo Bonzini 931c95997a3SFrancisco Iglesias static uint64_t xlnx_zynqmp_qspips_read(void *opaque, 932c95997a3SFrancisco Iglesias hwaddr addr, unsigned size) 933c95997a3SFrancisco Iglesias { 934c95997a3SFrancisco Iglesias XlnxZynqMPQSPIPS *s = XLNX_ZYNQMP_QSPIPS(opaque); 935c95997a3SFrancisco Iglesias uint32_t reg = addr / 4; 936c95997a3SFrancisco Iglesias uint32_t ret; 937c95997a3SFrancisco Iglesias uint8_t rx_buf[4]; 938c95997a3SFrancisco Iglesias int shortfall; 939c95997a3SFrancisco Iglesias 940c95997a3SFrancisco Iglesias if (reg <= R_MOD_ID) { 941c95997a3SFrancisco Iglesias return xilinx_spips_read(opaque, addr, size); 942c95997a3SFrancisco Iglesias } else { 943c95997a3SFrancisco Iglesias switch (reg) { 944c95997a3SFrancisco Iglesias case R_GQSPI_RXD: 945c95997a3SFrancisco Iglesias if (fifo8_is_empty(&s->rx_fifo_g)) { 946c95997a3SFrancisco Iglesias qemu_log_mask(LOG_GUEST_ERROR, 947c95997a3SFrancisco Iglesias "Read from empty GQSPI RX FIFO\n"); 948c95997a3SFrancisco Iglesias return 0; 949c95997a3SFrancisco Iglesias } 950c95997a3SFrancisco Iglesias memset(rx_buf, 0, sizeof(rx_buf)); 951c95997a3SFrancisco Iglesias shortfall = rx_data_bytes(&s->rx_fifo_g, rx_buf, 952c95997a3SFrancisco Iglesias XILINX_SPIPS(s)->num_txrx_bytes); 953c95997a3SFrancisco Iglesias ret = ARRAY_FIELD_EX32(s->regs, GQSPI_CNFG, ENDIAN) ? 954c95997a3SFrancisco Iglesias cpu_to_be32(*(uint32_t *)rx_buf) : 955c95997a3SFrancisco Iglesias cpu_to_le32(*(uint32_t *)rx_buf); 956c95997a3SFrancisco Iglesias if (!ARRAY_FIELD_EX32(s->regs, GQSPI_CNFG, ENDIAN)) { 957c95997a3SFrancisco Iglesias ret <<= 8 * shortfall; 958c95997a3SFrancisco Iglesias } 959c95997a3SFrancisco Iglesias xlnx_zynqmp_qspips_check_flush(s); 960c95997a3SFrancisco Iglesias xlnx_zynqmp_qspips_update_ixr(s); 961c95997a3SFrancisco Iglesias return ret; 962c95997a3SFrancisco Iglesias default: 963c95997a3SFrancisco Iglesias return s->regs[reg]; 964c95997a3SFrancisco Iglesias } 965c95997a3SFrancisco Iglesias } 966c95997a3SFrancisco Iglesias } 967c95997a3SFrancisco Iglesias 96831e17060SPaolo Bonzini static void xilinx_spips_write(void *opaque, hwaddr addr, 96931e17060SPaolo Bonzini uint64_t value, unsigned size) 97031e17060SPaolo Bonzini { 97131e17060SPaolo Bonzini int mask = ~0; 97231e17060SPaolo Bonzini XilinxSPIPS *s = opaque; 97331e17060SPaolo Bonzini 9744a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr, (unsigned)value); 97531e17060SPaolo Bonzini addr >>= 2; 97631e17060SPaolo Bonzini switch (addr) { 97731e17060SPaolo Bonzini case R_CONFIG: 9782133a5f6SPeter Crosthwaite mask = ~(R_CONFIG_RSVD | MAN_START_COM); 979275e28ccSFrancisco Iglesias if ((value & MAN_START_COM) && (s->regs[R_CONFIG] & MAN_START_EN)) { 980275e28ccSFrancisco Iglesias s->man_start_com = true; 98131e17060SPaolo Bonzini } 98231e17060SPaolo Bonzini break; 98331e17060SPaolo Bonzini case R_INTR_STATUS: 98431e17060SPaolo Bonzini mask = IXR_ALL; 98531e17060SPaolo Bonzini s->regs[R_INTR_STATUS] &= ~(mask & value); 98631e17060SPaolo Bonzini goto no_reg_update; 98731e17060SPaolo Bonzini case R_INTR_DIS: 98831e17060SPaolo Bonzini mask = IXR_ALL; 98931e17060SPaolo Bonzini s->regs[R_INTR_MASK] &= ~(mask & value); 99031e17060SPaolo Bonzini goto no_reg_update; 99131e17060SPaolo Bonzini case R_INTR_EN: 99231e17060SPaolo Bonzini mask = IXR_ALL; 99331e17060SPaolo Bonzini s->regs[R_INTR_MASK] |= mask & value; 99431e17060SPaolo Bonzini goto no_reg_update; 99531e17060SPaolo Bonzini case R_EN: 99631e17060SPaolo Bonzini mask = 0x1; 99731e17060SPaolo Bonzini break; 99831e17060SPaolo Bonzini case R_SLAVE_IDLE_COUNT: 99931e17060SPaolo Bonzini mask = 0xFF; 100031e17060SPaolo Bonzini break; 100131e17060SPaolo Bonzini case R_RX_DATA: 100231e17060SPaolo Bonzini case R_INTR_MASK: 100331e17060SPaolo Bonzini case R_MOD_ID: 100431e17060SPaolo Bonzini mask = 0; 100531e17060SPaolo Bonzini break; 100631e17060SPaolo Bonzini case R_TX_DATA: 10072fdd171eSFrancisco Iglesias tx_data_bytes(&s->tx_fifo, (uint32_t)value, s->num_txrx_bytes, 10082fdd171eSFrancisco Iglesias s->regs[R_CONFIG] & R_CONFIG_ENDIAN); 100931e17060SPaolo Bonzini goto no_reg_update; 101031e17060SPaolo Bonzini case R_TXD1: 10112fdd171eSFrancisco Iglesias tx_data_bytes(&s->tx_fifo, (uint32_t)value, 1, 10122fdd171eSFrancisco Iglesias s->regs[R_CONFIG] & R_CONFIG_ENDIAN); 101331e17060SPaolo Bonzini goto no_reg_update; 101431e17060SPaolo Bonzini case R_TXD2: 10152fdd171eSFrancisco Iglesias tx_data_bytes(&s->tx_fifo, (uint32_t)value, 2, 10162fdd171eSFrancisco Iglesias s->regs[R_CONFIG] & R_CONFIG_ENDIAN); 101731e17060SPaolo Bonzini goto no_reg_update; 101831e17060SPaolo Bonzini case R_TXD3: 10192fdd171eSFrancisco Iglesias tx_data_bytes(&s->tx_fifo, (uint32_t)value, 3, 10202fdd171eSFrancisco Iglesias s->regs[R_CONFIG] & R_CONFIG_ENDIAN); 102131e17060SPaolo Bonzini goto no_reg_update; 102231e17060SPaolo Bonzini } 102331e17060SPaolo Bonzini s->regs[addr] = (s->regs[addr] & ~mask) | (value & mask); 102431e17060SPaolo Bonzini no_reg_update: 1025c4f08ffeSPeter Crosthwaite xilinx_spips_update_cs_lines(s); 1026275e28ccSFrancisco Iglesias xilinx_spips_check_flush(s); 102731e17060SPaolo Bonzini xilinx_spips_update_cs_lines(s); 1028c4f08ffeSPeter Crosthwaite xilinx_spips_update_ixr(s); 102931e17060SPaolo Bonzini } 103031e17060SPaolo Bonzini 103131e17060SPaolo Bonzini static const MemoryRegionOps spips_ops = { 103231e17060SPaolo Bonzini .read = xilinx_spips_read, 103331e17060SPaolo Bonzini .write = xilinx_spips_write, 103431e17060SPaolo Bonzini .endianness = DEVICE_LITTLE_ENDIAN, 103531e17060SPaolo Bonzini }; 103631e17060SPaolo Bonzini 1037252b99baSKONRAD Frederic static void xilinx_qspips_invalidate_mmio_ptr(XilinxQSPIPS *q) 1038252b99baSKONRAD Frederic { 103983c3a1f6SKONRAD Frederic q->lqspi_cached_addr = ~0ULL; 1040252b99baSKONRAD Frederic } 1041252b99baSKONRAD Frederic 1042b5cd9143SPeter Crosthwaite static void xilinx_qspips_write(void *opaque, hwaddr addr, 1043b5cd9143SPeter Crosthwaite uint64_t value, unsigned size) 1044b5cd9143SPeter Crosthwaite { 1045b5cd9143SPeter Crosthwaite XilinxQSPIPS *q = XILINX_QSPIPS(opaque); 1046ef06ca39SFrancisco Iglesias XilinxSPIPS *s = XILINX_SPIPS(opaque); 1047b5cd9143SPeter Crosthwaite 1048b5cd9143SPeter Crosthwaite xilinx_spips_write(opaque, addr, value, size); 1049b5cd9143SPeter Crosthwaite addr >>= 2; 1050b5cd9143SPeter Crosthwaite 1051b5cd9143SPeter Crosthwaite if (addr == R_LQSPI_CFG) { 1052252b99baSKONRAD Frederic xilinx_qspips_invalidate_mmio_ptr(q); 1053b5cd9143SPeter Crosthwaite } 1054ef06ca39SFrancisco Iglesias if (s->regs[R_CMND] & R_CMND_RXFIFO_DRAIN) { 1055ef06ca39SFrancisco Iglesias fifo8_reset(&s->rx_fifo); 1056ef06ca39SFrancisco Iglesias } 1057b5cd9143SPeter Crosthwaite } 1058b5cd9143SPeter Crosthwaite 1059c95997a3SFrancisco Iglesias static void xlnx_zynqmp_qspips_write(void *opaque, hwaddr addr, 1060c95997a3SFrancisco Iglesias uint64_t value, unsigned size) 1061c95997a3SFrancisco Iglesias { 1062c95997a3SFrancisco Iglesias XlnxZynqMPQSPIPS *s = XLNX_ZYNQMP_QSPIPS(opaque); 1063c95997a3SFrancisco Iglesias uint32_t reg = addr / 4; 1064c95997a3SFrancisco Iglesias 1065c95997a3SFrancisco Iglesias if (reg <= R_MOD_ID) { 1066c95997a3SFrancisco Iglesias xilinx_qspips_write(opaque, addr, value, size); 1067c95997a3SFrancisco Iglesias } else { 1068c95997a3SFrancisco Iglesias switch (reg) { 1069c95997a3SFrancisco Iglesias case R_GQSPI_CNFG: 1070c95997a3SFrancisco Iglesias if (FIELD_EX32(value, GQSPI_CNFG, GEN_FIFO_START) && 1071c95997a3SFrancisco Iglesias ARRAY_FIELD_EX32(s->regs, GQSPI_CNFG, GEN_FIFO_START_MODE)) { 1072c95997a3SFrancisco Iglesias s->man_start_com_g = true; 1073c95997a3SFrancisco Iglesias } 1074c95997a3SFrancisco Iglesias s->regs[reg] = value & ~(R_GQSPI_CNFG_GEN_FIFO_START_MASK); 1075c95997a3SFrancisco Iglesias break; 1076c95997a3SFrancisco Iglesias case R_GQSPI_GEN_FIFO: 1077c95997a3SFrancisco Iglesias if (!fifo32_is_full(&s->fifo_g)) { 1078c95997a3SFrancisco Iglesias fifo32_push(&s->fifo_g, value); 1079c95997a3SFrancisco Iglesias } 1080c95997a3SFrancisco Iglesias break; 1081c95997a3SFrancisco Iglesias case R_GQSPI_TXD: 1082c95997a3SFrancisco Iglesias tx_data_bytes(&s->tx_fifo_g, (uint32_t)value, 4, 1083c95997a3SFrancisco Iglesias ARRAY_FIELD_EX32(s->regs, GQSPI_CNFG, ENDIAN)); 1084c95997a3SFrancisco Iglesias break; 1085c95997a3SFrancisco Iglesias case R_GQSPI_FIFO_CTRL: 1086c95997a3SFrancisco Iglesias if (FIELD_EX32(value, GQSPI_FIFO_CTRL, GENERIC_FIFO_RESET)) { 1087c95997a3SFrancisco Iglesias fifo32_reset(&s->fifo_g); 1088c95997a3SFrancisco Iglesias } 1089c95997a3SFrancisco Iglesias if (FIELD_EX32(value, GQSPI_FIFO_CTRL, TX_FIFO_RESET)) { 1090c95997a3SFrancisco Iglesias fifo8_reset(&s->tx_fifo_g); 1091c95997a3SFrancisco Iglesias } 1092c95997a3SFrancisco Iglesias if (FIELD_EX32(value, GQSPI_FIFO_CTRL, RX_FIFO_RESET)) { 1093c95997a3SFrancisco Iglesias fifo8_reset(&s->rx_fifo_g); 1094c95997a3SFrancisco Iglesias } 1095c95997a3SFrancisco Iglesias break; 1096c95997a3SFrancisco Iglesias case R_GQSPI_IDR: 1097c95997a3SFrancisco Iglesias s->regs[R_GQSPI_IMR] |= value; 1098c95997a3SFrancisco Iglesias break; 1099c95997a3SFrancisco Iglesias case R_GQSPI_IER: 1100c95997a3SFrancisco Iglesias s->regs[R_GQSPI_IMR] &= ~value; 1101c95997a3SFrancisco Iglesias break; 1102c95997a3SFrancisco Iglesias case R_GQSPI_ISR: 1103c95997a3SFrancisco Iglesias s->regs[R_GQSPI_ISR] &= ~value; 1104c95997a3SFrancisco Iglesias break; 1105c95997a3SFrancisco Iglesias case R_GQSPI_IMR: 1106c95997a3SFrancisco Iglesias case R_GQSPI_RXD: 1107c95997a3SFrancisco Iglesias case R_GQSPI_GF_SNAPSHOT: 1108c95997a3SFrancisco Iglesias case R_GQSPI_MOD_ID: 1109c95997a3SFrancisco Iglesias break; 1110c95997a3SFrancisco Iglesias default: 1111c95997a3SFrancisco Iglesias s->regs[reg] = value; 1112c95997a3SFrancisco Iglesias break; 1113c95997a3SFrancisco Iglesias } 1114c95997a3SFrancisco Iglesias xlnx_zynqmp_qspips_update_cs_lines(s); 1115c95997a3SFrancisco Iglesias xlnx_zynqmp_qspips_check_flush(s); 1116c95997a3SFrancisco Iglesias xlnx_zynqmp_qspips_update_cs_lines(s); 1117c95997a3SFrancisco Iglesias xlnx_zynqmp_qspips_update_ixr(s); 1118c95997a3SFrancisco Iglesias } 1119c95997a3SFrancisco Iglesias xlnx_zynqmp_qspips_notify(s); 1120c95997a3SFrancisco Iglesias } 1121c95997a3SFrancisco Iglesias 1122b5cd9143SPeter Crosthwaite static const MemoryRegionOps qspips_ops = { 1123b5cd9143SPeter Crosthwaite .read = xilinx_spips_read, 1124b5cd9143SPeter Crosthwaite .write = xilinx_qspips_write, 1125b5cd9143SPeter Crosthwaite .endianness = DEVICE_LITTLE_ENDIAN, 1126b5cd9143SPeter Crosthwaite }; 1127b5cd9143SPeter Crosthwaite 1128c95997a3SFrancisco Iglesias static const MemoryRegionOps xlnx_zynqmp_qspips_ops = { 1129c95997a3SFrancisco Iglesias .read = xlnx_zynqmp_qspips_read, 1130c95997a3SFrancisco Iglesias .write = xlnx_zynqmp_qspips_write, 1131c95997a3SFrancisco Iglesias .endianness = DEVICE_LITTLE_ENDIAN, 1132c95997a3SFrancisco Iglesias }; 1133c95997a3SFrancisco Iglesias 113431e17060SPaolo Bonzini #define LQSPI_CACHE_SIZE 1024 113531e17060SPaolo Bonzini 1136252b99baSKONRAD Frederic static void lqspi_load_cache(void *opaque, hwaddr addr) 113731e17060SPaolo Bonzini { 11386b91f015SPeter Crosthwaite XilinxQSPIPS *q = opaque; 113931e17060SPaolo Bonzini XilinxSPIPS *s = opaque; 1140252b99baSKONRAD Frederic int i; 1141252b99baSKONRAD Frederic int flash_addr = ((addr & ~(LQSPI_CACHE_SIZE - 1)) 1142252b99baSKONRAD Frederic / num_effective_busses(s)); 114331e17060SPaolo Bonzini int slave = flash_addr >> LQSPI_ADDRESS_BITS; 114431e17060SPaolo Bonzini int cache_entry = 0; 114515408b42SPeter Crosthwaite uint32_t u_page_save = s->regs[R_LQSPI_STS] & ~LQSPI_CFG_U_PAGE; 114615408b42SPeter Crosthwaite 1147252b99baSKONRAD Frederic if (addr < q->lqspi_cached_addr || 1148252b99baSKONRAD Frederic addr > q->lqspi_cached_addr + LQSPI_CACHE_SIZE - 4) { 1149252b99baSKONRAD Frederic xilinx_qspips_invalidate_mmio_ptr(q); 115015408b42SPeter Crosthwaite s->regs[R_LQSPI_STS] &= ~LQSPI_CFG_U_PAGE; 115115408b42SPeter Crosthwaite s->regs[R_LQSPI_STS] |= slave ? LQSPI_CFG_U_PAGE : 0; 115231e17060SPaolo Bonzini 11534a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "config reg status: %08x\n", s->regs[R_LQSPI_CFG]); 115431e17060SPaolo Bonzini 115531e17060SPaolo Bonzini fifo8_reset(&s->tx_fifo); 115631e17060SPaolo Bonzini fifo8_reset(&s->rx_fifo); 115731e17060SPaolo Bonzini 115831e17060SPaolo Bonzini /* instruction */ 11594a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "pushing read instruction: %02x\n", 11604a5b6fa8SPeter Crosthwaite (unsigned)(uint8_t)(s->regs[R_LQSPI_CFG] & 11614a5b6fa8SPeter Crosthwaite LQSPI_CFG_INST_CODE)); 116231e17060SPaolo Bonzini fifo8_push(&s->tx_fifo, s->regs[R_LQSPI_CFG] & LQSPI_CFG_INST_CODE); 116331e17060SPaolo Bonzini /* read address */ 11644a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "pushing read address %06x\n", flash_addr); 1165fbfaa507SFrancisco Iglesias if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_ADDR4) { 1166fbfaa507SFrancisco Iglesias fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 24)); 1167fbfaa507SFrancisco Iglesias } 116831e17060SPaolo Bonzini fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 16)); 116931e17060SPaolo Bonzini fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 8)); 117031e17060SPaolo Bonzini fifo8_push(&s->tx_fifo, (uint8_t)flash_addr); 117131e17060SPaolo Bonzini /* mode bits */ 117231e17060SPaolo Bonzini if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_MODE_EN) { 117331e17060SPaolo Bonzini fifo8_push(&s->tx_fifo, extract32(s->regs[R_LQSPI_CFG], 117431e17060SPaolo Bonzini LQSPI_CFG_MODE_SHIFT, 117531e17060SPaolo Bonzini LQSPI_CFG_MODE_WIDTH)); 117631e17060SPaolo Bonzini } 117731e17060SPaolo Bonzini /* dummy bytes */ 117831e17060SPaolo Bonzini for (i = 0; i < (extract32(s->regs[R_LQSPI_CFG], LQSPI_CFG_DUMMY_SHIFT, 117931e17060SPaolo Bonzini LQSPI_CFG_DUMMY_WIDTH)); ++i) { 11804a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "pushing dummy byte\n"); 118131e17060SPaolo Bonzini fifo8_push(&s->tx_fifo, 0); 118231e17060SPaolo Bonzini } 1183c4f08ffeSPeter Crosthwaite xilinx_spips_update_cs_lines(s); 118431e17060SPaolo Bonzini xilinx_spips_flush_txfifo(s); 118531e17060SPaolo Bonzini fifo8_reset(&s->rx_fifo); 118631e17060SPaolo Bonzini 11874a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "starting QSPI data read\n"); 118831e17060SPaolo Bonzini 1189b0b7ae62SPeter Crosthwaite while (cache_entry < LQSPI_CACHE_SIZE) { 1190b0b7ae62SPeter Crosthwaite for (i = 0; i < 64; ++i) { 11912fdd171eSFrancisco Iglesias tx_data_bytes(&s->tx_fifo, 0, 1, false); 1192a66418f6SPeter Crosthwaite } 119331e17060SPaolo Bonzini xilinx_spips_flush_txfifo(s); 1194b0b7ae62SPeter Crosthwaite for (i = 0; i < 64; ++i) { 11952fdd171eSFrancisco Iglesias rx_data_bytes(&s->rx_fifo, &q->lqspi_buf[cache_entry++], 1); 1196a66418f6SPeter Crosthwaite } 119731e17060SPaolo Bonzini } 119831e17060SPaolo Bonzini 119915408b42SPeter Crosthwaite s->regs[R_LQSPI_STS] &= ~LQSPI_CFG_U_PAGE; 120015408b42SPeter Crosthwaite s->regs[R_LQSPI_STS] |= u_page_save; 120131e17060SPaolo Bonzini xilinx_spips_update_cs_lines(s); 120231e17060SPaolo Bonzini 1203b0b7ae62SPeter Crosthwaite q->lqspi_cached_addr = flash_addr * num_effective_busses(s); 1204252b99baSKONRAD Frederic } 1205252b99baSKONRAD Frederic } 1206252b99baSKONRAD Frederic 12075937bd50SPhilippe Mathieu-Daudé static MemTxResult lqspi_read(void *opaque, hwaddr addr, uint64_t *value, 12085937bd50SPhilippe Mathieu-Daudé unsigned size, MemTxAttrs attrs) 1209252b99baSKONRAD Frederic { 12105937bd50SPhilippe Mathieu-Daudé XilinxQSPIPS *q = XILINX_QSPIPS(opaque); 1211252b99baSKONRAD Frederic 1212252b99baSKONRAD Frederic if (addr >= q->lqspi_cached_addr && 1213252b99baSKONRAD Frederic addr <= q->lqspi_cached_addr + LQSPI_CACHE_SIZE - 4) { 1214252b99baSKONRAD Frederic uint8_t *retp = &q->lqspi_buf[addr - q->lqspi_cached_addr]; 12155937bd50SPhilippe Mathieu-Daudé *value = cpu_to_le32(*(uint32_t *)retp); 12165937bd50SPhilippe Mathieu-Daudé DB_PRINT_L(1, "addr: %08" HWADDR_PRIx ", data: %08" PRIx64 "\n", 12175937bd50SPhilippe Mathieu-Daudé addr, *value); 12185937bd50SPhilippe Mathieu-Daudé return MEMTX_OK; 121931e17060SPaolo Bonzini } 12205937bd50SPhilippe Mathieu-Daudé 12215937bd50SPhilippe Mathieu-Daudé lqspi_load_cache(opaque, addr); 12225937bd50SPhilippe Mathieu-Daudé return lqspi_read(opaque, addr, value, size, attrs); 122331e17060SPaolo Bonzini } 122431e17060SPaolo Bonzini 1225936a236cSPhilippe Mathieu-Daudé static MemTxResult lqspi_write(void *opaque, hwaddr offset, uint64_t value, 1226936a236cSPhilippe Mathieu-Daudé unsigned size, MemTxAttrs attrs) 1227936a236cSPhilippe Mathieu-Daudé { 1228936a236cSPhilippe Mathieu-Daudé /* 1229936a236cSPhilippe Mathieu-Daudé * From UG1085, Chapter 24 (Quad-SPI controllers): 1230936a236cSPhilippe Mathieu-Daudé * - Writes are ignored 1231936a236cSPhilippe Mathieu-Daudé * - AXI writes generate an external AXI slave error (SLVERR) 1232936a236cSPhilippe Mathieu-Daudé */ 1233936a236cSPhilippe Mathieu-Daudé qemu_log_mask(LOG_GUEST_ERROR, "%s Unexpected %u-bit access to 0x%" PRIx64 1234936a236cSPhilippe Mathieu-Daudé " (value: 0x%" PRIx64 "\n", 1235936a236cSPhilippe Mathieu-Daudé __func__, size << 3, offset, value); 1236936a236cSPhilippe Mathieu-Daudé 1237936a236cSPhilippe Mathieu-Daudé return MEMTX_ERROR; 1238936a236cSPhilippe Mathieu-Daudé } 1239936a236cSPhilippe Mathieu-Daudé 124031e17060SPaolo Bonzini static const MemoryRegionOps lqspi_ops = { 12415937bd50SPhilippe Mathieu-Daudé .read_with_attrs = lqspi_read, 1242936a236cSPhilippe Mathieu-Daudé .write_with_attrs = lqspi_write, 124331e17060SPaolo Bonzini .endianness = DEVICE_NATIVE_ENDIAN, 1244526668c7SPhilippe Mathieu-Daudé .impl = { 1245526668c7SPhilippe Mathieu-Daudé .min_access_size = 4, 1246526668c7SPhilippe Mathieu-Daudé .max_access_size = 4, 1247526668c7SPhilippe Mathieu-Daudé }, 124831e17060SPaolo Bonzini .valid = { 1249b0b7ae62SPeter Crosthwaite .min_access_size = 1, 125031e17060SPaolo Bonzini .max_access_size = 4 125131e17060SPaolo Bonzini } 125231e17060SPaolo Bonzini }; 125331e17060SPaolo Bonzini 125431e17060SPaolo Bonzini static void xilinx_spips_realize(DeviceState *dev, Error **errp) 125531e17060SPaolo Bonzini { 125631e17060SPaolo Bonzini XilinxSPIPS *s = XILINX_SPIPS(dev); 125731e17060SPaolo Bonzini SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 125810e60b35SPeter Crosthwaite XilinxSPIPSClass *xsc = XILINX_SPIPS_GET_CLASS(s); 1259c8cccba3SPaolo Bonzini qemu_irq *cs; 126031e17060SPaolo Bonzini int i; 126131e17060SPaolo Bonzini 12624a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "realized spips\n"); 126331e17060SPaolo Bonzini 1264fbe5dac7SFrancisco Iglesias if (s->num_busses > MAX_NUM_BUSSES) { 1265fbe5dac7SFrancisco Iglesias error_setg(errp, 1266fbe5dac7SFrancisco Iglesias "requested number of SPI busses %u exceeds maximum %d", 1267fbe5dac7SFrancisco Iglesias s->num_busses, MAX_NUM_BUSSES); 1268fbe5dac7SFrancisco Iglesias return; 1269fbe5dac7SFrancisco Iglesias } 1270fbe5dac7SFrancisco Iglesias if (s->num_busses < MIN_NUM_BUSSES) { 1271fbe5dac7SFrancisco Iglesias error_setg(errp, 1272fbe5dac7SFrancisco Iglesias "requested number of SPI busses %u is below minimum %d", 1273fbe5dac7SFrancisco Iglesias s->num_busses, MIN_NUM_BUSSES); 1274fbe5dac7SFrancisco Iglesias return; 1275fbe5dac7SFrancisco Iglesias } 1276fbe5dac7SFrancisco Iglesias 127731e17060SPaolo Bonzini s->spi = g_new(SSIBus *, s->num_busses); 127831e17060SPaolo Bonzini for (i = 0; i < s->num_busses; ++i) { 127931e17060SPaolo Bonzini char bus_name[16]; 128031e17060SPaolo Bonzini snprintf(bus_name, 16, "spi%d", i); 128131e17060SPaolo Bonzini s->spi[i] = ssi_create_bus(dev, bus_name); 128231e17060SPaolo Bonzini } 128331e17060SPaolo Bonzini 128431e17060SPaolo Bonzini s->cs_lines = g_new0(qemu_irq, s->num_cs * s->num_busses); 1285ef06ca39SFrancisco Iglesias s->cs_lines_state = g_new0(bool, s->num_cs * s->num_busses); 1286c8cccba3SPaolo Bonzini for (i = 0, cs = s->cs_lines; i < s->num_busses; ++i, cs += s->num_cs) { 1287c8cccba3SPaolo Bonzini ssi_auto_connect_slaves(DEVICE(s), cs, s->spi[i]); 1288c8cccba3SPaolo Bonzini } 1289c8cccba3SPaolo Bonzini 129031e17060SPaolo Bonzini sysbus_init_irq(sbd, &s->irq); 129131e17060SPaolo Bonzini for (i = 0; i < s->num_cs * s->num_busses; ++i) { 129231e17060SPaolo Bonzini sysbus_init_irq(sbd, &s->cs_lines[i]); 129331e17060SPaolo Bonzini } 129431e17060SPaolo Bonzini 129529776739SPaolo Bonzini memory_region_init_io(&s->iomem, OBJECT(s), xsc->reg_ops, s, 1296c95997a3SFrancisco Iglesias "spi", XLNX_ZYNQMP_SPIPS_R_MAX * 4); 129731e17060SPaolo Bonzini sysbus_init_mmio(sbd, &s->iomem); 129831e17060SPaolo Bonzini 12996b91f015SPeter Crosthwaite s->irqline = -1; 13006b91f015SPeter Crosthwaite 130110e60b35SPeter Crosthwaite fifo8_create(&s->rx_fifo, xsc->rx_fifo_size); 130210e60b35SPeter Crosthwaite fifo8_create(&s->tx_fifo, xsc->tx_fifo_size); 13036b91f015SPeter Crosthwaite } 13046b91f015SPeter Crosthwaite 13056b91f015SPeter Crosthwaite static void xilinx_qspips_realize(DeviceState *dev, Error **errp) 13066b91f015SPeter Crosthwaite { 13076b91f015SPeter Crosthwaite XilinxSPIPS *s = XILINX_SPIPS(dev); 13086b91f015SPeter Crosthwaite XilinxQSPIPS *q = XILINX_QSPIPS(dev); 13096b91f015SPeter Crosthwaite SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 13106b91f015SPeter Crosthwaite 13114a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "realized qspips\n"); 13126b91f015SPeter Crosthwaite 13136b91f015SPeter Crosthwaite s->num_busses = 2; 13146b91f015SPeter Crosthwaite s->num_cs = 2; 13156b91f015SPeter Crosthwaite s->num_txrx_bytes = 4; 13166b91f015SPeter Crosthwaite 13176b91f015SPeter Crosthwaite xilinx_spips_realize(dev, errp); 131829776739SPaolo Bonzini memory_region_init_io(&s->mmlqspi, OBJECT(s), &lqspi_ops, s, "lqspi", 131931e17060SPaolo Bonzini (1 << LQSPI_ADDRESS_BITS) * 2); 132031e17060SPaolo Bonzini sysbus_init_mmio(sbd, &s->mmlqspi); 132131e17060SPaolo Bonzini 13226b91f015SPeter Crosthwaite q->lqspi_cached_addr = ~0ULL; 132331e17060SPaolo Bonzini } 132431e17060SPaolo Bonzini 1325c95997a3SFrancisco Iglesias static void xlnx_zynqmp_qspips_realize(DeviceState *dev, Error **errp) 1326c95997a3SFrancisco Iglesias { 1327c95997a3SFrancisco Iglesias XlnxZynqMPQSPIPS *s = XLNX_ZYNQMP_QSPIPS(dev); 1328c95997a3SFrancisco Iglesias XilinxSPIPSClass *xsc = XILINX_SPIPS_GET_CLASS(s); 1329c95997a3SFrancisco Iglesias 133021d887cdSSai Pavan Boddu if (s->dma_burst_size > QSPI_DMA_MAX_BURST_SIZE) { 133121d887cdSSai Pavan Boddu error_setg(errp, 133221d887cdSSai Pavan Boddu "qspi dma burst size %u exceeds maximum limit %d", 133321d887cdSSai Pavan Boddu s->dma_burst_size, QSPI_DMA_MAX_BURST_SIZE); 133421d887cdSSai Pavan Boddu return; 133521d887cdSSai Pavan Boddu } 1336c95997a3SFrancisco Iglesias xilinx_qspips_realize(dev, errp); 1337c95997a3SFrancisco Iglesias fifo8_create(&s->rx_fifo_g, xsc->rx_fifo_size); 1338c95997a3SFrancisco Iglesias fifo8_create(&s->tx_fifo_g, xsc->tx_fifo_size); 1339c95997a3SFrancisco Iglesias fifo32_create(&s->fifo_g, 32); 1340c95997a3SFrancisco Iglesias } 1341c95997a3SFrancisco Iglesias 1342c95997a3SFrancisco Iglesias static void xlnx_zynqmp_qspips_init(Object *obj) 1343c95997a3SFrancisco Iglesias { 1344c95997a3SFrancisco Iglesias XlnxZynqMPQSPIPS *rq = XLNX_ZYNQMP_QSPIPS(obj); 1345c95997a3SFrancisco Iglesias 1346c95997a3SFrancisco Iglesias object_property_add_link(obj, "stream-connected-dma", TYPE_STREAM_SLAVE, 1347c95997a3SFrancisco Iglesias (Object **)&rq->dma, 1348c95997a3SFrancisco Iglesias object_property_allow_set_link, 1349265b578cSMarc-André Lureau OBJ_PROP_LINK_STRONG, 1350c95997a3SFrancisco Iglesias NULL); 1351c95997a3SFrancisco Iglesias } 1352c95997a3SFrancisco Iglesias 135331e17060SPaolo Bonzini static int xilinx_spips_post_load(void *opaque, int version_id) 135431e17060SPaolo Bonzini { 135531e17060SPaolo Bonzini xilinx_spips_update_ixr((XilinxSPIPS *)opaque); 135631e17060SPaolo Bonzini xilinx_spips_update_cs_lines((XilinxSPIPS *)opaque); 135731e17060SPaolo Bonzini return 0; 135831e17060SPaolo Bonzini } 135931e17060SPaolo Bonzini 136031e17060SPaolo Bonzini static const VMStateDescription vmstate_xilinx_spips = { 136131e17060SPaolo Bonzini .name = "xilinx_spips", 136231e17060SPaolo Bonzini .version_id = 2, 136331e17060SPaolo Bonzini .minimum_version_id = 2, 136431e17060SPaolo Bonzini .post_load = xilinx_spips_post_load, 136531e17060SPaolo Bonzini .fields = (VMStateField[]) { 136631e17060SPaolo Bonzini VMSTATE_FIFO8(tx_fifo, XilinxSPIPS), 136731e17060SPaolo Bonzini VMSTATE_FIFO8(rx_fifo, XilinxSPIPS), 13686363235bSAlistair Francis VMSTATE_UINT32_ARRAY(regs, XilinxSPIPS, XLNX_SPIPS_R_MAX), 136931e17060SPaolo Bonzini VMSTATE_UINT8(snoop_state, XilinxSPIPS), 137031e17060SPaolo Bonzini VMSTATE_END_OF_LIST() 137131e17060SPaolo Bonzini } 137231e17060SPaolo Bonzini }; 137331e17060SPaolo Bonzini 1374c95997a3SFrancisco Iglesias static int xlnx_zynqmp_qspips_post_load(void *opaque, int version_id) 1375c95997a3SFrancisco Iglesias { 1376c95997a3SFrancisco Iglesias XlnxZynqMPQSPIPS *s = (XlnxZynqMPQSPIPS *)opaque; 1377c95997a3SFrancisco Iglesias XilinxSPIPS *qs = XILINX_SPIPS(s); 1378c95997a3SFrancisco Iglesias 1379c95997a3SFrancisco Iglesias if (ARRAY_FIELD_EX32(s->regs, GQSPI_SELECT, GENERIC_QSPI_EN) && 1380c95997a3SFrancisco Iglesias fifo8_is_empty(&qs->rx_fifo) && fifo8_is_empty(&qs->tx_fifo)) { 1381c95997a3SFrancisco Iglesias xlnx_zynqmp_qspips_update_ixr(s); 1382c95997a3SFrancisco Iglesias xlnx_zynqmp_qspips_update_cs_lines(s); 1383c95997a3SFrancisco Iglesias } 1384c95997a3SFrancisco Iglesias return 0; 1385c95997a3SFrancisco Iglesias } 1386c95997a3SFrancisco Iglesias 1387c95997a3SFrancisco Iglesias static const VMStateDescription vmstate_xilinx_qspips = { 1388c95997a3SFrancisco Iglesias .name = "xilinx_qspips", 1389c95997a3SFrancisco Iglesias .version_id = 1, 1390c95997a3SFrancisco Iglesias .minimum_version_id = 1, 1391c95997a3SFrancisco Iglesias .fields = (VMStateField[]) { 1392c95997a3SFrancisco Iglesias VMSTATE_STRUCT(parent_obj, XilinxQSPIPS, 0, 1393c95997a3SFrancisco Iglesias vmstate_xilinx_spips, XilinxSPIPS), 1394c95997a3SFrancisco Iglesias VMSTATE_END_OF_LIST() 1395c95997a3SFrancisco Iglesias } 1396c95997a3SFrancisco Iglesias }; 1397c95997a3SFrancisco Iglesias 1398c95997a3SFrancisco Iglesias static const VMStateDescription vmstate_xlnx_zynqmp_qspips = { 1399c95997a3SFrancisco Iglesias .name = "xlnx_zynqmp_qspips", 1400c95997a3SFrancisco Iglesias .version_id = 1, 1401c95997a3SFrancisco Iglesias .minimum_version_id = 1, 1402c95997a3SFrancisco Iglesias .post_load = xlnx_zynqmp_qspips_post_load, 1403c95997a3SFrancisco Iglesias .fields = (VMStateField[]) { 1404c95997a3SFrancisco Iglesias VMSTATE_STRUCT(parent_obj, XlnxZynqMPQSPIPS, 0, 1405c95997a3SFrancisco Iglesias vmstate_xilinx_qspips, XilinxQSPIPS), 1406c95997a3SFrancisco Iglesias VMSTATE_FIFO8(tx_fifo_g, XlnxZynqMPQSPIPS), 1407c95997a3SFrancisco Iglesias VMSTATE_FIFO8(rx_fifo_g, XlnxZynqMPQSPIPS), 1408c95997a3SFrancisco Iglesias VMSTATE_FIFO32(fifo_g, XlnxZynqMPQSPIPS), 1409c95997a3SFrancisco Iglesias VMSTATE_UINT32_ARRAY(regs, XlnxZynqMPQSPIPS, XLNX_ZYNQMP_SPIPS_R_MAX), 1410c95997a3SFrancisco Iglesias VMSTATE_END_OF_LIST() 1411c95997a3SFrancisco Iglesias } 1412c95997a3SFrancisco Iglesias }; 1413c95997a3SFrancisco Iglesias 141421d887cdSSai Pavan Boddu static Property xilinx_zynqmp_qspips_properties[] = { 141521d887cdSSai Pavan Boddu DEFINE_PROP_UINT32("dma-burst-size", XlnxZynqMPQSPIPS, dma_burst_size, 64), 141621d887cdSSai Pavan Boddu DEFINE_PROP_END_OF_LIST(), 141721d887cdSSai Pavan Boddu }; 141821d887cdSSai Pavan Boddu 141931e17060SPaolo Bonzini static Property xilinx_spips_properties[] = { 142031e17060SPaolo Bonzini DEFINE_PROP_UINT8("num-busses", XilinxSPIPS, num_busses, 1), 142131e17060SPaolo Bonzini DEFINE_PROP_UINT8("num-ss-bits", XilinxSPIPS, num_cs, 4), 142231e17060SPaolo Bonzini DEFINE_PROP_UINT8("num-txrx-bytes", XilinxSPIPS, num_txrx_bytes, 1), 142331e17060SPaolo Bonzini DEFINE_PROP_END_OF_LIST(), 142431e17060SPaolo Bonzini }; 14256b91f015SPeter Crosthwaite 14266b91f015SPeter Crosthwaite static void xilinx_qspips_class_init(ObjectClass *klass, void * data) 14276b91f015SPeter Crosthwaite { 14286b91f015SPeter Crosthwaite DeviceClass *dc = DEVICE_CLASS(klass); 142910e60b35SPeter Crosthwaite XilinxSPIPSClass *xsc = XILINX_SPIPS_CLASS(klass); 14306b91f015SPeter Crosthwaite 14316b91f015SPeter Crosthwaite dc->realize = xilinx_qspips_realize; 1432b5cd9143SPeter Crosthwaite xsc->reg_ops = &qspips_ops; 143310e60b35SPeter Crosthwaite xsc->rx_fifo_size = RXFF_A_Q; 143410e60b35SPeter Crosthwaite xsc->tx_fifo_size = TXFF_A_Q; 14356b91f015SPeter Crosthwaite } 14366b91f015SPeter Crosthwaite 143731e17060SPaolo Bonzini static void xilinx_spips_class_init(ObjectClass *klass, void *data) 143831e17060SPaolo Bonzini { 143931e17060SPaolo Bonzini DeviceClass *dc = DEVICE_CLASS(klass); 144010e60b35SPeter Crosthwaite XilinxSPIPSClass *xsc = XILINX_SPIPS_CLASS(klass); 144131e17060SPaolo Bonzini 144231e17060SPaolo Bonzini dc->realize = xilinx_spips_realize; 144331e17060SPaolo Bonzini dc->reset = xilinx_spips_reset; 144431e17060SPaolo Bonzini dc->props = xilinx_spips_properties; 144531e17060SPaolo Bonzini dc->vmsd = &vmstate_xilinx_spips; 144610e60b35SPeter Crosthwaite 1447b5cd9143SPeter Crosthwaite xsc->reg_ops = &spips_ops; 144810e60b35SPeter Crosthwaite xsc->rx_fifo_size = RXFF_A; 144910e60b35SPeter Crosthwaite xsc->tx_fifo_size = TXFF_A; 145031e17060SPaolo Bonzini } 145131e17060SPaolo Bonzini 1452c95997a3SFrancisco Iglesias static void xlnx_zynqmp_qspips_class_init(ObjectClass *klass, void * data) 1453c95997a3SFrancisco Iglesias { 1454c95997a3SFrancisco Iglesias DeviceClass *dc = DEVICE_CLASS(klass); 1455c95997a3SFrancisco Iglesias XilinxSPIPSClass *xsc = XILINX_SPIPS_CLASS(klass); 1456c95997a3SFrancisco Iglesias 1457c95997a3SFrancisco Iglesias dc->realize = xlnx_zynqmp_qspips_realize; 1458c95997a3SFrancisco Iglesias dc->reset = xlnx_zynqmp_qspips_reset; 1459c95997a3SFrancisco Iglesias dc->vmsd = &vmstate_xlnx_zynqmp_qspips; 146021d887cdSSai Pavan Boddu dc->props = xilinx_zynqmp_qspips_properties; 1461c95997a3SFrancisco Iglesias xsc->reg_ops = &xlnx_zynqmp_qspips_ops; 1462c95997a3SFrancisco Iglesias xsc->rx_fifo_size = RXFF_A_Q; 1463c95997a3SFrancisco Iglesias xsc->tx_fifo_size = TXFF_A_Q; 1464c95997a3SFrancisco Iglesias } 1465c95997a3SFrancisco Iglesias 146631e17060SPaolo Bonzini static const TypeInfo xilinx_spips_info = { 146731e17060SPaolo Bonzini .name = TYPE_XILINX_SPIPS, 146831e17060SPaolo Bonzini .parent = TYPE_SYS_BUS_DEVICE, 146931e17060SPaolo Bonzini .instance_size = sizeof(XilinxSPIPS), 147031e17060SPaolo Bonzini .class_init = xilinx_spips_class_init, 147110e60b35SPeter Crosthwaite .class_size = sizeof(XilinxSPIPSClass), 147231e17060SPaolo Bonzini }; 147331e17060SPaolo Bonzini 14746b91f015SPeter Crosthwaite static const TypeInfo xilinx_qspips_info = { 14756b91f015SPeter Crosthwaite .name = TYPE_XILINX_QSPIPS, 14766b91f015SPeter Crosthwaite .parent = TYPE_XILINX_SPIPS, 14776b91f015SPeter Crosthwaite .instance_size = sizeof(XilinxQSPIPS), 14786b91f015SPeter Crosthwaite .class_init = xilinx_qspips_class_init, 14796b91f015SPeter Crosthwaite }; 14806b91f015SPeter Crosthwaite 1481c95997a3SFrancisco Iglesias static const TypeInfo xlnx_zynqmp_qspips_info = { 1482c95997a3SFrancisco Iglesias .name = TYPE_XLNX_ZYNQMP_QSPIPS, 1483c95997a3SFrancisco Iglesias .parent = TYPE_XILINX_QSPIPS, 1484c95997a3SFrancisco Iglesias .instance_size = sizeof(XlnxZynqMPQSPIPS), 1485c95997a3SFrancisco Iglesias .instance_init = xlnx_zynqmp_qspips_init, 1486c95997a3SFrancisco Iglesias .class_init = xlnx_zynqmp_qspips_class_init, 1487c95997a3SFrancisco Iglesias }; 1488c95997a3SFrancisco Iglesias 148931e17060SPaolo Bonzini static void xilinx_spips_register_types(void) 149031e17060SPaolo Bonzini { 149131e17060SPaolo Bonzini type_register_static(&xilinx_spips_info); 14926b91f015SPeter Crosthwaite type_register_static(&xilinx_qspips_info); 1493c95997a3SFrancisco Iglesias type_register_static(&xlnx_zynqmp_qspips_info); 149431e17060SPaolo Bonzini } 149531e17060SPaolo Bonzini 149631e17060SPaolo Bonzini type_init(xilinx_spips_register_types) 1497