131e17060SPaolo Bonzini /* 231e17060SPaolo Bonzini * QEMU model of the Xilinx Zynq SPI controller 331e17060SPaolo Bonzini * 431e17060SPaolo Bonzini * Copyright (c) 2012 Peter A. G. Crosthwaite 531e17060SPaolo Bonzini * 631e17060SPaolo Bonzini * Permission is hereby granted, free of charge, to any person obtaining a copy 731e17060SPaolo Bonzini * of this software and associated documentation files (the "Software"), to deal 831e17060SPaolo Bonzini * in the Software without restriction, including without limitation the rights 931e17060SPaolo Bonzini * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 1031e17060SPaolo Bonzini * copies of the Software, and to permit persons to whom the Software is 1131e17060SPaolo Bonzini * furnished to do so, subject to the following conditions: 1231e17060SPaolo Bonzini * 1331e17060SPaolo Bonzini * The above copyright notice and this permission notice shall be included in 1431e17060SPaolo Bonzini * all copies or substantial portions of the Software. 1531e17060SPaolo Bonzini * 1631e17060SPaolo Bonzini * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1731e17060SPaolo Bonzini * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1831e17060SPaolo Bonzini * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 1931e17060SPaolo Bonzini * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 2031e17060SPaolo Bonzini * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 2131e17060SPaolo Bonzini * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 2231e17060SPaolo Bonzini * THE SOFTWARE. 2331e17060SPaolo Bonzini */ 2431e17060SPaolo Bonzini 258ef94f0bSPeter Maydell #include "qemu/osdep.h" 2631e17060SPaolo Bonzini #include "hw/sysbus.h" 2764552b6bSMarkus Armbruster #include "hw/irq.h" 2831e17060SPaolo Bonzini #include "hw/ptimer.h" 29a27bd6c7SMarkus Armbruster #include "hw/qdev-properties.h" 3031e17060SPaolo Bonzini #include "qemu/log.h" 310b8fa32fSMarkus Armbruster #include "qemu/module.h" 3231e17060SPaolo Bonzini #include "qemu/bitops.h" 336363235bSAlistair Francis #include "hw/ssi/xilinx_spips.h" 3483c3a1f6SKONRAD Frederic #include "qapi/error.h" 35ef06ca39SFrancisco Iglesias #include "hw/register.h" 36c95997a3SFrancisco Iglesias #include "sysemu/dma.h" 3783c3a1f6SKONRAD Frederic #include "migration/blocker.h" 38d6454270SMarkus Armbruster #include "migration/vmstate.h" 3931e17060SPaolo Bonzini 404a5b6fa8SPeter Crosthwaite #ifndef XILINX_SPIPS_ERR_DEBUG 414a5b6fa8SPeter Crosthwaite #define XILINX_SPIPS_ERR_DEBUG 0 424a5b6fa8SPeter Crosthwaite #endif 434a5b6fa8SPeter Crosthwaite 444a5b6fa8SPeter Crosthwaite #define DB_PRINT_L(level, ...) do { \ 454a5b6fa8SPeter Crosthwaite if (XILINX_SPIPS_ERR_DEBUG > (level)) { \ 4631e17060SPaolo Bonzini fprintf(stderr, ": %s: ", __func__); \ 4731e17060SPaolo Bonzini fprintf(stderr, ## __VA_ARGS__); \ 484a5b6fa8SPeter Crosthwaite } \ 492562755eSEric Blake } while (0) 5031e17060SPaolo Bonzini 5131e17060SPaolo Bonzini /* config register */ 5231e17060SPaolo Bonzini #define R_CONFIG (0x00 / 4) 53c8f8f9fbSPeter Maydell #define IFMODE (1U << 31) 542fdd171eSFrancisco Iglesias #define R_CONFIG_ENDIAN (1 << 26) 5531e17060SPaolo Bonzini #define MODEFAIL_GEN_EN (1 << 17) 5631e17060SPaolo Bonzini #define MAN_START_COM (1 << 16) 5731e17060SPaolo Bonzini #define MAN_START_EN (1 << 15) 5831e17060SPaolo Bonzini #define MANUAL_CS (1 << 14) 5931e17060SPaolo Bonzini #define CS (0xF << 10) 6031e17060SPaolo Bonzini #define CS_SHIFT (10) 6131e17060SPaolo Bonzini #define PERI_SEL (1 << 9) 6231e17060SPaolo Bonzini #define REF_CLK (1 << 8) 6331e17060SPaolo Bonzini #define FIFO_WIDTH (3 << 6) 6431e17060SPaolo Bonzini #define BAUD_RATE_DIV (7 << 3) 6531e17060SPaolo Bonzini #define CLK_PH (1 << 2) 6631e17060SPaolo Bonzini #define CLK_POL (1 << 1) 6731e17060SPaolo Bonzini #define MODE_SEL (1 << 0) 682133a5f6SPeter Crosthwaite #define R_CONFIG_RSVD (0x7bf40000) 6931e17060SPaolo Bonzini 7031e17060SPaolo Bonzini /* interrupt mechanism */ 7131e17060SPaolo Bonzini #define R_INTR_STATUS (0x04 / 4) 724f0da466SAlistair Francis #define R_INTR_STATUS_RESET (0x104) 7331e17060SPaolo Bonzini #define R_INTR_EN (0x08 / 4) 7431e17060SPaolo Bonzini #define R_INTR_DIS (0x0C / 4) 7531e17060SPaolo Bonzini #define R_INTR_MASK (0x10 / 4) 7631e17060SPaolo Bonzini #define IXR_TX_FIFO_UNDERFLOW (1 << 6) 77c95997a3SFrancisco Iglesias /* Poll timeout not implemented */ 78c95997a3SFrancisco Iglesias #define IXR_RX_FIFO_EMPTY (1 << 11) 79c95997a3SFrancisco Iglesias #define IXR_GENERIC_FIFO_FULL (1 << 10) 80c95997a3SFrancisco Iglesias #define IXR_GENERIC_FIFO_NOT_FULL (1 << 9) 81c95997a3SFrancisco Iglesias #define IXR_TX_FIFO_EMPTY (1 << 8) 82c95997a3SFrancisco Iglesias #define IXR_GENERIC_FIFO_EMPTY (1 << 7) 8331e17060SPaolo Bonzini #define IXR_RX_FIFO_FULL (1 << 5) 8431e17060SPaolo Bonzini #define IXR_RX_FIFO_NOT_EMPTY (1 << 4) 8531e17060SPaolo Bonzini #define IXR_TX_FIFO_FULL (1 << 3) 8631e17060SPaolo Bonzini #define IXR_TX_FIFO_NOT_FULL (1 << 2) 8731e17060SPaolo Bonzini #define IXR_TX_FIFO_MODE_FAIL (1 << 1) 8831e17060SPaolo Bonzini #define IXR_RX_FIFO_OVERFLOW (1 << 0) 89c95997a3SFrancisco Iglesias #define IXR_ALL ((1 << 13) - 1) 90c95997a3SFrancisco Iglesias #define GQSPI_IXR_MASK 0xFBE 91c95997a3SFrancisco Iglesias #define IXR_SELF_CLEAR \ 92c95997a3SFrancisco Iglesias (IXR_GENERIC_FIFO_EMPTY \ 93c95997a3SFrancisco Iglesias | IXR_GENERIC_FIFO_FULL \ 94c95997a3SFrancisco Iglesias | IXR_GENERIC_FIFO_NOT_FULL \ 95c95997a3SFrancisco Iglesias | IXR_TX_FIFO_EMPTY \ 96c95997a3SFrancisco Iglesias | IXR_TX_FIFO_FULL \ 97c95997a3SFrancisco Iglesias | IXR_TX_FIFO_NOT_FULL \ 98c95997a3SFrancisco Iglesias | IXR_RX_FIFO_EMPTY \ 99c95997a3SFrancisco Iglesias | IXR_RX_FIFO_FULL \ 100c95997a3SFrancisco Iglesias | IXR_RX_FIFO_NOT_EMPTY) 10131e17060SPaolo Bonzini 10231e17060SPaolo Bonzini #define R_EN (0x14 / 4) 10331e17060SPaolo Bonzini #define R_DELAY (0x18 / 4) 10431e17060SPaolo Bonzini #define R_TX_DATA (0x1C / 4) 10531e17060SPaolo Bonzini #define R_RX_DATA (0x20 / 4) 10631e17060SPaolo Bonzini #define R_SLAVE_IDLE_COUNT (0x24 / 4) 10731e17060SPaolo Bonzini #define R_TX_THRES (0x28 / 4) 10831e17060SPaolo Bonzini #define R_RX_THRES (0x2C / 4) 1094f0da466SAlistair Francis #define R_GPIO (0x30 / 4) 1104f0da466SAlistair Francis #define R_LPBK_DLY_ADJ (0x38 / 4) 1114f0da466SAlistair Francis #define R_LPBK_DLY_ADJ_RESET (0x33) 1123a6606c7SSai Pavan Boddu #define R_IOU_TAPDLY_BYPASS (0x3C / 4) 11331e17060SPaolo Bonzini #define R_TXD1 (0x80 / 4) 11431e17060SPaolo Bonzini #define R_TXD2 (0x84 / 4) 11531e17060SPaolo Bonzini #define R_TXD3 (0x88 / 4) 11631e17060SPaolo Bonzini 11731e17060SPaolo Bonzini #define R_LQSPI_CFG (0xa0 / 4) 11831e17060SPaolo Bonzini #define R_LQSPI_CFG_RESET 0x03A002EB 119c8f8f9fbSPeter Maydell #define LQSPI_CFG_LQ_MODE (1U << 31) 12031e17060SPaolo Bonzini #define LQSPI_CFG_TWO_MEM (1 << 30) 121fbfaa507SFrancisco Iglesias #define LQSPI_CFG_SEP_BUS (1 << 29) 12231e17060SPaolo Bonzini #define LQSPI_CFG_U_PAGE (1 << 28) 123fbfaa507SFrancisco Iglesias #define LQSPI_CFG_ADDR4 (1 << 27) 12431e17060SPaolo Bonzini #define LQSPI_CFG_MODE_EN (1 << 25) 12531e17060SPaolo Bonzini #define LQSPI_CFG_MODE_WIDTH 8 12631e17060SPaolo Bonzini #define LQSPI_CFG_MODE_SHIFT 16 12731e17060SPaolo Bonzini #define LQSPI_CFG_DUMMY_WIDTH 3 12831e17060SPaolo Bonzini #define LQSPI_CFG_DUMMY_SHIFT 8 12931e17060SPaolo Bonzini #define LQSPI_CFG_INST_CODE 0xFF 13031e17060SPaolo Bonzini 131ef06ca39SFrancisco Iglesias #define R_CMND (0xc0 / 4) 132ef06ca39SFrancisco Iglesias #define R_CMND_RXFIFO_DRAIN (1 << 19) 133ef06ca39SFrancisco Iglesias FIELD(CMND, PARTIAL_BYTE_LEN, 16, 3) 134ef06ca39SFrancisco Iglesias #define R_CMND_EXT_ADD (1 << 15) 135ef06ca39SFrancisco Iglesias FIELD(CMND, RX_DISCARD, 8, 7) 136ef06ca39SFrancisco Iglesias FIELD(CMND, DUMMY_CYCLES, 2, 6) 137ef06ca39SFrancisco Iglesias #define R_CMND_DMA_EN (1 << 1) 138ef06ca39SFrancisco Iglesias #define R_CMND_PUSH_WAIT (1 << 0) 139275e28ccSFrancisco Iglesias #define R_TRANSFER_SIZE (0xc4 / 4) 14031e17060SPaolo Bonzini #define R_LQSPI_STS (0xA4 / 4) 14131e17060SPaolo Bonzini #define LQSPI_STS_WR_RECVD (1 << 1) 14231e17060SPaolo Bonzini 1433a6606c7SSai Pavan Boddu #define R_DUMMY_CYCLE_EN (0xC8 / 4) 1443a6606c7SSai Pavan Boddu #define R_ECO (0xF8 / 4) 14531e17060SPaolo Bonzini #define R_MOD_ID (0xFC / 4) 14631e17060SPaolo Bonzini 147c95997a3SFrancisco Iglesias #define R_GQSPI_SELECT (0x144 / 4) 148c95997a3SFrancisco Iglesias FIELD(GQSPI_SELECT, GENERIC_QSPI_EN, 0, 1) 149c95997a3SFrancisco Iglesias #define R_GQSPI_ISR (0x104 / 4) 150c95997a3SFrancisco Iglesias #define R_GQSPI_IER (0x108 / 4) 151c95997a3SFrancisco Iglesias #define R_GQSPI_IDR (0x10c / 4) 152c95997a3SFrancisco Iglesias #define R_GQSPI_IMR (0x110 / 4) 1534f0da466SAlistair Francis #define R_GQSPI_IMR_RESET (0xfbe) 154c95997a3SFrancisco Iglesias #define R_GQSPI_TX_THRESH (0x128 / 4) 155c95997a3SFrancisco Iglesias #define R_GQSPI_RX_THRESH (0x12c / 4) 1564f0da466SAlistair Francis #define R_GQSPI_GPIO (0x130 / 4) 1574f0da466SAlistair Francis #define R_GQSPI_LPBK_DLY_ADJ (0x138 / 4) 1584f0da466SAlistair Francis #define R_GQSPI_LPBK_DLY_ADJ_RESET (0x33) 159c95997a3SFrancisco Iglesias #define R_GQSPI_CNFG (0x100 / 4) 160c95997a3SFrancisco Iglesias FIELD(GQSPI_CNFG, MODE_EN, 30, 2) 161c95997a3SFrancisco Iglesias FIELD(GQSPI_CNFG, GEN_FIFO_START_MODE, 29, 1) 162c95997a3SFrancisco Iglesias FIELD(GQSPI_CNFG, GEN_FIFO_START, 28, 1) 163c95997a3SFrancisco Iglesias FIELD(GQSPI_CNFG, ENDIAN, 26, 1) 164c95997a3SFrancisco Iglesias /* Poll timeout not implemented */ 165c95997a3SFrancisco Iglesias FIELD(GQSPI_CNFG, EN_POLL_TIMEOUT, 20, 1) 166c95997a3SFrancisco Iglesias /* QEMU doesnt care about any of these last three */ 167c95997a3SFrancisco Iglesias FIELD(GQSPI_CNFG, BR, 3, 3) 168c95997a3SFrancisco Iglesias FIELD(GQSPI_CNFG, CPH, 2, 1) 169c95997a3SFrancisco Iglesias FIELD(GQSPI_CNFG, CPL, 1, 1) 170c95997a3SFrancisco Iglesias #define R_GQSPI_GEN_FIFO (0x140 / 4) 171c95997a3SFrancisco Iglesias #define R_GQSPI_TXD (0x11c / 4) 172c95997a3SFrancisco Iglesias #define R_GQSPI_RXD (0x120 / 4) 173c95997a3SFrancisco Iglesias #define R_GQSPI_FIFO_CTRL (0x14c / 4) 174c95997a3SFrancisco Iglesias FIELD(GQSPI_FIFO_CTRL, RX_FIFO_RESET, 2, 1) 175c95997a3SFrancisco Iglesias FIELD(GQSPI_FIFO_CTRL, TX_FIFO_RESET, 1, 1) 176c95997a3SFrancisco Iglesias FIELD(GQSPI_FIFO_CTRL, GENERIC_FIFO_RESET, 0, 1) 177c95997a3SFrancisco Iglesias #define R_GQSPI_GFIFO_THRESH (0x150 / 4) 178c95997a3SFrancisco Iglesias #define R_GQSPI_DATA_STS (0x15c / 4) 179c95997a3SFrancisco Iglesias /* We use the snapshot register to hold the core state for the currently 180c95997a3SFrancisco Iglesias * or most recently executed command. So the generic fifo format is defined 181c95997a3SFrancisco Iglesias * for the snapshot register 182c95997a3SFrancisco Iglesias */ 183c95997a3SFrancisco Iglesias #define R_GQSPI_GF_SNAPSHOT (0x160 / 4) 184c95997a3SFrancisco Iglesias FIELD(GQSPI_GF_SNAPSHOT, POLL, 19, 1) 185c95997a3SFrancisco Iglesias FIELD(GQSPI_GF_SNAPSHOT, STRIPE, 18, 1) 186c95997a3SFrancisco Iglesias FIELD(GQSPI_GF_SNAPSHOT, RECIEVE, 17, 1) 187c95997a3SFrancisco Iglesias FIELD(GQSPI_GF_SNAPSHOT, TRANSMIT, 16, 1) 188c95997a3SFrancisco Iglesias FIELD(GQSPI_GF_SNAPSHOT, DATA_BUS_SELECT, 14, 2) 189c95997a3SFrancisco Iglesias FIELD(GQSPI_GF_SNAPSHOT, CHIP_SELECT, 12, 2) 190c95997a3SFrancisco Iglesias FIELD(GQSPI_GF_SNAPSHOT, SPI_MODE, 10, 2) 191c95997a3SFrancisco Iglesias FIELD(GQSPI_GF_SNAPSHOT, EXPONENT, 9, 1) 192c95997a3SFrancisco Iglesias FIELD(GQSPI_GF_SNAPSHOT, DATA_XFER, 8, 1) 193c95997a3SFrancisco Iglesias FIELD(GQSPI_GF_SNAPSHOT, IMMEDIATE_DATA, 0, 8) 1944f0da466SAlistair Francis #define R_GQSPI_MOD_ID (0x1fc / 4) 1954f0da466SAlistair Francis #define R_GQSPI_MOD_ID_RESET (0x10a0000) 1964f0da466SAlistair Francis 1974f0da466SAlistair Francis #define R_QSPIDMA_DST_CTRL (0x80c / 4) 1984f0da466SAlistair Francis #define R_QSPIDMA_DST_CTRL_RESET (0x803ffa00) 1994f0da466SAlistair Francis #define R_QSPIDMA_DST_I_MASK (0x820 / 4) 2004f0da466SAlistair Francis #define R_QSPIDMA_DST_I_MASK_RESET (0xfe) 2014f0da466SAlistair Francis #define R_QSPIDMA_DST_CTRL2 (0x824 / 4) 2024f0da466SAlistair Francis #define R_QSPIDMA_DST_CTRL2_RESET (0x081bfff8) 2034f0da466SAlistair Francis 20431e17060SPaolo Bonzini /* size of TXRX FIFOs */ 205c95997a3SFrancisco Iglesias #define RXFF_A (128) 206c95997a3SFrancisco Iglesias #define TXFF_A (128) 20731e17060SPaolo Bonzini 20810e60b35SPeter Crosthwaite #define RXFF_A_Q (64 * 4) 20910e60b35SPeter Crosthwaite #define TXFF_A_Q (64 * 4) 21010e60b35SPeter Crosthwaite 21131e17060SPaolo Bonzini /* 16MB per linear region */ 21231e17060SPaolo Bonzini #define LQSPI_ADDRESS_BITS 24 21331e17060SPaolo Bonzini 21431e17060SPaolo Bonzini #define SNOOP_CHECKING 0xFF 215ef06ca39SFrancisco Iglesias #define SNOOP_ADDR 0xF0 216ef06ca39SFrancisco Iglesias #define SNOOP_NONE 0xEE 21731e17060SPaolo Bonzini #define SNOOP_STRIPING 0 21831e17060SPaolo Bonzini 219fbe5dac7SFrancisco Iglesias #define MIN_NUM_BUSSES 1 220fbe5dac7SFrancisco Iglesias #define MAX_NUM_BUSSES 2 221fbe5dac7SFrancisco Iglesias 22231e17060SPaolo Bonzini static inline int num_effective_busses(XilinxSPIPS *s) 22331e17060SPaolo Bonzini { 22431e17060SPaolo Bonzini return (s->regs[R_LQSPI_CFG] & LQSPI_CFG_SEP_BUS && 22531e17060SPaolo Bonzini s->regs[R_LQSPI_CFG] & LQSPI_CFG_TWO_MEM) ? s->num_busses : 1; 22631e17060SPaolo Bonzini } 22731e17060SPaolo Bonzini 228c95997a3SFrancisco Iglesias static void xilinx_spips_update_cs(XilinxSPIPS *s, int field) 229c4f08ffeSPeter Crosthwaite { 230c95997a3SFrancisco Iglesias int i; 23131e17060SPaolo Bonzini 2320c4a94b8SFrancisco Iglesias for (i = 0; i < s->num_cs * s->num_busses; i++) { 233c95997a3SFrancisco Iglesias bool old_state = s->cs_lines_state[i]; 234c95997a3SFrancisco Iglesias bool new_state = field & (1 << i); 23531e17060SPaolo Bonzini 236c95997a3SFrancisco Iglesias if (old_state != new_state) { 237c95997a3SFrancisco Iglesias s->cs_lines_state[i] = new_state; 238ef06ca39SFrancisco Iglesias s->rx_discard = ARRAY_FIELD_EX32(s->regs, CMND, RX_DISCARD); 239ec7e429bSPhilippe Mathieu-Daudé DB_PRINT_L(1, "%sselecting peripheral %d\n", 240ec7e429bSPhilippe Mathieu-Daudé new_state ? "" : "de", i); 241ef06ca39SFrancisco Iglesias } 242c95997a3SFrancisco Iglesias qemu_set_irq(s->cs_lines[i], !new_state); 24331e17060SPaolo Bonzini } 2440c4a94b8SFrancisco Iglesias if (!(field & ((1 << (s->num_cs * s->num_busses)) - 1))) { 24531e17060SPaolo Bonzini s->snoop_state = SNOOP_CHECKING; 246ef06ca39SFrancisco Iglesias s->cmd_dummies = 0; 247ef06ca39SFrancisco Iglesias s->link_state = 1; 248ef06ca39SFrancisco Iglesias s->link_state_next = 1; 249ef06ca39SFrancisco Iglesias s->link_state_next_when = 0; 2504a5b6fa8SPeter Crosthwaite DB_PRINT_L(1, "moving to snoop check state\n"); 25131e17060SPaolo Bonzini } 25231e17060SPaolo Bonzini } 25331e17060SPaolo Bonzini 254c95997a3SFrancisco Iglesias static void xlnx_zynqmp_qspips_update_cs_lines(XlnxZynqMPQSPIPS *s) 255c95997a3SFrancisco Iglesias { 256c95997a3SFrancisco Iglesias if (s->regs[R_GQSPI_GF_SNAPSHOT]) { 257c95997a3SFrancisco Iglesias int field = ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, CHIP_SELECT); 2580c4a94b8SFrancisco Iglesias bool upper_cs_sel = field & (1 << 1); 2590c4a94b8SFrancisco Iglesias bool lower_cs_sel = field & 1; 2600c4a94b8SFrancisco Iglesias bool bus0_enabled; 2610c4a94b8SFrancisco Iglesias bool bus1_enabled; 2620c4a94b8SFrancisco Iglesias uint8_t buses; 2630c4a94b8SFrancisco Iglesias int cs = 0; 2640c4a94b8SFrancisco Iglesias 2650c4a94b8SFrancisco Iglesias buses = ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, DATA_BUS_SELECT); 2660c4a94b8SFrancisco Iglesias bus0_enabled = buses & 1; 2670c4a94b8SFrancisco Iglesias bus1_enabled = buses & (1 << 1); 2680c4a94b8SFrancisco Iglesias 2690c4a94b8SFrancisco Iglesias if (bus0_enabled && bus1_enabled) { 2700c4a94b8SFrancisco Iglesias if (lower_cs_sel) { 2710c4a94b8SFrancisco Iglesias cs |= 1; 2720c4a94b8SFrancisco Iglesias } 2730c4a94b8SFrancisco Iglesias if (upper_cs_sel) { 2740c4a94b8SFrancisco Iglesias cs |= 1 << 3; 2750c4a94b8SFrancisco Iglesias } 2760c4a94b8SFrancisco Iglesias } else if (bus0_enabled) { 2770c4a94b8SFrancisco Iglesias if (lower_cs_sel) { 2780c4a94b8SFrancisco Iglesias cs |= 1; 2790c4a94b8SFrancisco Iglesias } 2800c4a94b8SFrancisco Iglesias if (upper_cs_sel) { 2810c4a94b8SFrancisco Iglesias cs |= 1 << 1; 2820c4a94b8SFrancisco Iglesias } 2830c4a94b8SFrancisco Iglesias } else if (bus1_enabled) { 2840c4a94b8SFrancisco Iglesias if (lower_cs_sel) { 2850c4a94b8SFrancisco Iglesias cs |= 1 << 2; 2860c4a94b8SFrancisco Iglesias } 2870c4a94b8SFrancisco Iglesias if (upper_cs_sel) { 2880c4a94b8SFrancisco Iglesias cs |= 1 << 3; 2890c4a94b8SFrancisco Iglesias } 2900c4a94b8SFrancisco Iglesias } 2910c4a94b8SFrancisco Iglesias xilinx_spips_update_cs(XILINX_SPIPS(s), cs); 292c95997a3SFrancisco Iglesias } 293c95997a3SFrancisco Iglesias } 294c95997a3SFrancisco Iglesias 295c95997a3SFrancisco Iglesias static void xilinx_spips_update_cs_lines(XilinxSPIPS *s) 296c95997a3SFrancisco Iglesias { 297c95997a3SFrancisco Iglesias int field = ~((s->regs[R_CONFIG] & CS) >> CS_SHIFT); 298c95997a3SFrancisco Iglesias 299c95997a3SFrancisco Iglesias /* In dual parallel, mirror low CS to both */ 300c95997a3SFrancisco Iglesias if (num_effective_busses(s) == 2) { 301c95997a3SFrancisco Iglesias /* Single bit chip-select for qspi */ 302c95997a3SFrancisco Iglesias field &= 0x1; 3030c4a94b8SFrancisco Iglesias field |= field << 3; 304c95997a3SFrancisco Iglesias /* Dual stack U-Page */ 305c95997a3SFrancisco Iglesias } else if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_TWO_MEM && 306c95997a3SFrancisco Iglesias s->regs[R_LQSPI_STS] & LQSPI_CFG_U_PAGE) { 307c95997a3SFrancisco Iglesias /* Single bit chip-select for qspi */ 308c95997a3SFrancisco Iglesias field &= 0x1; 309c95997a3SFrancisco Iglesias /* change from CS0 to CS1 */ 310c95997a3SFrancisco Iglesias field <<= 1; 311c95997a3SFrancisco Iglesias } 312c95997a3SFrancisco Iglesias /* Auto CS */ 313c95997a3SFrancisco Iglesias if (!(s->regs[R_CONFIG] & MANUAL_CS) && 314c95997a3SFrancisco Iglesias fifo8_is_empty(&s->tx_fifo)) { 315c95997a3SFrancisco Iglesias field = 0; 316c95997a3SFrancisco Iglesias } 317c95997a3SFrancisco Iglesias xilinx_spips_update_cs(s, field); 318c95997a3SFrancisco Iglesias } 319c95997a3SFrancisco Iglesias 32031e17060SPaolo Bonzini static void xilinx_spips_update_ixr(XilinxSPIPS *s) 32131e17060SPaolo Bonzini { 322c95997a3SFrancisco Iglesias if (!(s->regs[R_LQSPI_CFG] & LQSPI_CFG_LQ_MODE)) { 323c95997a3SFrancisco Iglesias s->regs[R_INTR_STATUS] &= ~IXR_SELF_CLEAR; 32431e17060SPaolo Bonzini s->regs[R_INTR_STATUS] |= 32531e17060SPaolo Bonzini (fifo8_is_full(&s->rx_fifo) ? IXR_RX_FIFO_FULL : 0) | 326c95997a3SFrancisco Iglesias (s->rx_fifo.num >= s->regs[R_RX_THRES] ? 327c95997a3SFrancisco Iglesias IXR_RX_FIFO_NOT_EMPTY : 0) | 32831e17060SPaolo Bonzini (fifo8_is_full(&s->tx_fifo) ? IXR_TX_FIFO_FULL : 0) | 329c95997a3SFrancisco Iglesias (fifo8_is_empty(&s->tx_fifo) ? IXR_TX_FIFO_EMPTY : 0) | 33031e17060SPaolo Bonzini (s->tx_fifo.num < s->regs[R_TX_THRES] ? IXR_TX_FIFO_NOT_FULL : 0); 331c95997a3SFrancisco Iglesias } 33231e17060SPaolo Bonzini int new_irqline = !!(s->regs[R_INTR_MASK] & s->regs[R_INTR_STATUS] & 33331e17060SPaolo Bonzini IXR_ALL); 33431e17060SPaolo Bonzini if (new_irqline != s->irqline) { 33531e17060SPaolo Bonzini s->irqline = new_irqline; 33631e17060SPaolo Bonzini qemu_set_irq(s->irq, s->irqline); 33731e17060SPaolo Bonzini } 33831e17060SPaolo Bonzini } 33931e17060SPaolo Bonzini 340c95997a3SFrancisco Iglesias static void xlnx_zynqmp_qspips_update_ixr(XlnxZynqMPQSPIPS *s) 341c95997a3SFrancisco Iglesias { 342c95997a3SFrancisco Iglesias uint32_t gqspi_int; 343c95997a3SFrancisco Iglesias int new_irqline; 344c95997a3SFrancisco Iglesias 345c95997a3SFrancisco Iglesias s->regs[R_GQSPI_ISR] &= ~IXR_SELF_CLEAR; 346c95997a3SFrancisco Iglesias s->regs[R_GQSPI_ISR] |= 347c95997a3SFrancisco Iglesias (fifo32_is_empty(&s->fifo_g) ? IXR_GENERIC_FIFO_EMPTY : 0) | 348c95997a3SFrancisco Iglesias (fifo32_is_full(&s->fifo_g) ? IXR_GENERIC_FIFO_FULL : 0) | 349c95997a3SFrancisco Iglesias (s->fifo_g.fifo.num < s->regs[R_GQSPI_GFIFO_THRESH] ? 350c95997a3SFrancisco Iglesias IXR_GENERIC_FIFO_NOT_FULL : 0) | 351c95997a3SFrancisco Iglesias (fifo8_is_empty(&s->rx_fifo_g) ? IXR_RX_FIFO_EMPTY : 0) | 352c95997a3SFrancisco Iglesias (fifo8_is_full(&s->rx_fifo_g) ? IXR_RX_FIFO_FULL : 0) | 353c95997a3SFrancisco Iglesias (s->rx_fifo_g.num >= s->regs[R_GQSPI_RX_THRESH] ? 354c95997a3SFrancisco Iglesias IXR_RX_FIFO_NOT_EMPTY : 0) | 355c95997a3SFrancisco Iglesias (fifo8_is_empty(&s->tx_fifo_g) ? IXR_TX_FIFO_EMPTY : 0) | 356c95997a3SFrancisco Iglesias (fifo8_is_full(&s->tx_fifo_g) ? IXR_TX_FIFO_FULL : 0) | 357c95997a3SFrancisco Iglesias (s->tx_fifo_g.num < s->regs[R_GQSPI_TX_THRESH] ? 358c95997a3SFrancisco Iglesias IXR_TX_FIFO_NOT_FULL : 0); 359c95997a3SFrancisco Iglesias 360c95997a3SFrancisco Iglesias /* GQSPI Interrupt Trigger Status */ 361c95997a3SFrancisco Iglesias gqspi_int = (~s->regs[R_GQSPI_IMR]) & s->regs[R_GQSPI_ISR] & GQSPI_IXR_MASK; 362c95997a3SFrancisco Iglesias new_irqline = !!(gqspi_int & IXR_ALL); 363c95997a3SFrancisco Iglesias 364c95997a3SFrancisco Iglesias /* drive external interrupt pin */ 365c95997a3SFrancisco Iglesias if (new_irqline != s->gqspi_irqline) { 366c95997a3SFrancisco Iglesias s->gqspi_irqline = new_irqline; 367c95997a3SFrancisco Iglesias qemu_set_irq(XILINX_SPIPS(s)->irq, s->gqspi_irqline); 368c95997a3SFrancisco Iglesias } 369c95997a3SFrancisco Iglesias } 370c95997a3SFrancisco Iglesias 37131e17060SPaolo Bonzini static void xilinx_spips_reset(DeviceState *d) 37231e17060SPaolo Bonzini { 37331e17060SPaolo Bonzini XilinxSPIPS *s = XILINX_SPIPS(d); 37431e17060SPaolo Bonzini 375d3c348b6SAlistair Francis memset(s->regs, 0, sizeof(s->regs)); 37631e17060SPaolo Bonzini 37731e17060SPaolo Bonzini fifo8_reset(&s->rx_fifo); 37831e17060SPaolo Bonzini fifo8_reset(&s->rx_fifo); 37931e17060SPaolo Bonzini /* non zero resets */ 38031e17060SPaolo Bonzini s->regs[R_CONFIG] |= MODEFAIL_GEN_EN; 38131e17060SPaolo Bonzini s->regs[R_SLAVE_IDLE_COUNT] = 0xFF; 38231e17060SPaolo Bonzini s->regs[R_TX_THRES] = 1; 38331e17060SPaolo Bonzini s->regs[R_RX_THRES] = 1; 38431e17060SPaolo Bonzini /* FIXME: move magic number definition somewhere sensible */ 38531e17060SPaolo Bonzini s->regs[R_MOD_ID] = 0x01090106; 38631e17060SPaolo Bonzini s->regs[R_LQSPI_CFG] = R_LQSPI_CFG_RESET; 387ef06ca39SFrancisco Iglesias s->link_state = 1; 388ef06ca39SFrancisco Iglesias s->link_state_next = 1; 389ef06ca39SFrancisco Iglesias s->link_state_next_when = 0; 39031e17060SPaolo Bonzini s->snoop_state = SNOOP_CHECKING; 391ef06ca39SFrancisco Iglesias s->cmd_dummies = 0; 392275e28ccSFrancisco Iglesias s->man_start_com = false; 39331e17060SPaolo Bonzini xilinx_spips_update_ixr(s); 39431e17060SPaolo Bonzini xilinx_spips_update_cs_lines(s); 39531e17060SPaolo Bonzini } 39631e17060SPaolo Bonzini 397c95997a3SFrancisco Iglesias static void xlnx_zynqmp_qspips_reset(DeviceState *d) 398c95997a3SFrancisco Iglesias { 399c95997a3SFrancisco Iglesias XlnxZynqMPQSPIPS *s = XLNX_ZYNQMP_QSPIPS(d); 400c95997a3SFrancisco Iglesias 401c95997a3SFrancisco Iglesias xilinx_spips_reset(d); 402c95997a3SFrancisco Iglesias 403d3c348b6SAlistair Francis memset(s->regs, 0, sizeof(s->regs)); 404d3c348b6SAlistair Francis 405c95997a3SFrancisco Iglesias fifo8_reset(&s->rx_fifo_g); 406c95997a3SFrancisco Iglesias fifo8_reset(&s->rx_fifo_g); 407c95997a3SFrancisco Iglesias fifo32_reset(&s->fifo_g); 4084f0da466SAlistair Francis s->regs[R_INTR_STATUS] = R_INTR_STATUS_RESET; 4094f0da466SAlistair Francis s->regs[R_GPIO] = 1; 4104f0da466SAlistair Francis s->regs[R_LPBK_DLY_ADJ] = R_LPBK_DLY_ADJ_RESET; 4114f0da466SAlistair Francis s->regs[R_GQSPI_GFIFO_THRESH] = 0x10; 4124f0da466SAlistair Francis s->regs[R_MOD_ID] = 0x01090101; 4134f0da466SAlistair Francis s->regs[R_GQSPI_IMR] = R_GQSPI_IMR_RESET; 414c95997a3SFrancisco Iglesias s->regs[R_GQSPI_TX_THRESH] = 1; 415c95997a3SFrancisco Iglesias s->regs[R_GQSPI_RX_THRESH] = 1; 4164f0da466SAlistair Francis s->regs[R_GQSPI_GPIO] = 1; 4174f0da466SAlistair Francis s->regs[R_GQSPI_LPBK_DLY_ADJ] = R_GQSPI_LPBK_DLY_ADJ_RESET; 4184f0da466SAlistair Francis s->regs[R_GQSPI_MOD_ID] = R_GQSPI_MOD_ID_RESET; 4194f0da466SAlistair Francis s->regs[R_QSPIDMA_DST_CTRL] = R_QSPIDMA_DST_CTRL_RESET; 4204f0da466SAlistair Francis s->regs[R_QSPIDMA_DST_I_MASK] = R_QSPIDMA_DST_I_MASK_RESET; 4214f0da466SAlistair Francis s->regs[R_QSPIDMA_DST_CTRL2] = R_QSPIDMA_DST_CTRL2_RESET; 422c95997a3SFrancisco Iglesias s->man_start_com_g = false; 423c95997a3SFrancisco Iglesias s->gqspi_irqline = 0; 424c95997a3SFrancisco Iglesias xlnx_zynqmp_qspips_update_ixr(s); 425c95997a3SFrancisco Iglesias } 426c95997a3SFrancisco Iglesias 427c3725b85SFrancisco Iglesias /* N way (num) in place bit striper. Lay out row wise bits (MSB to LSB) 4289151da25SPeter Crosthwaite * column wise (from element 0 to N-1). num is the length of x, and dir 4299151da25SPeter Crosthwaite * reverses the direction of the transform. Best illustrated by example: 4309151da25SPeter Crosthwaite * Each digit in the below array is a single bit (num == 3): 4319151da25SPeter Crosthwaite * 432c3725b85SFrancisco Iglesias * {{ 76543210, } ----- stripe (dir == false) -----> {{ 741gdaFC, } 433c3725b85SFrancisco Iglesias * { hgfedcba, } { 630fcHEB, } 434c3725b85SFrancisco Iglesias * { HGFEDCBA, }} <---- upstripe (dir == true) ----- { 52hebGDA, }} 4359151da25SPeter Crosthwaite */ 4369151da25SPeter Crosthwaite 4379151da25SPeter Crosthwaite static inline void stripe8(uint8_t *x, int num, bool dir) 4389151da25SPeter Crosthwaite { 439aa64cfaeSPeter Maydell uint8_t r[MAX_NUM_BUSSES]; 4409151da25SPeter Crosthwaite int idx[2] = {0, 0}; 441c3725b85SFrancisco Iglesias int bit[2] = {0, 7}; 4429151da25SPeter Crosthwaite int d = dir; 4439151da25SPeter Crosthwaite 444aa64cfaeSPeter Maydell assert(num <= MAX_NUM_BUSSES); 445aa64cfaeSPeter Maydell memset(r, 0, sizeof(uint8_t) * num); 446aa64cfaeSPeter Maydell 4479151da25SPeter Crosthwaite for (idx[0] = 0; idx[0] < num; ++idx[0]) { 448c3725b85SFrancisco Iglesias for (bit[0] = 7; bit[0] >= 0; bit[0]--) { 449c3725b85SFrancisco Iglesias r[idx[!d]] |= x[idx[d]] & 1 << bit[d] ? 1 << bit[!d] : 0; 4509151da25SPeter Crosthwaite idx[1] = (idx[1] + 1) % num; 4519151da25SPeter Crosthwaite if (!idx[1]) { 452c3725b85SFrancisco Iglesias bit[1]--; 4539151da25SPeter Crosthwaite } 4549151da25SPeter Crosthwaite } 4559151da25SPeter Crosthwaite } 4569151da25SPeter Crosthwaite memcpy(x, r, sizeof(uint8_t) * num); 4579151da25SPeter Crosthwaite } 4589151da25SPeter Crosthwaite 459c95997a3SFrancisco Iglesias static void xlnx_zynqmp_qspips_flush_fifo_g(XlnxZynqMPQSPIPS *s) 460c95997a3SFrancisco Iglesias { 461c95997a3SFrancisco Iglesias while (s->regs[R_GQSPI_DATA_STS] || !fifo32_is_empty(&s->fifo_g)) { 462c95997a3SFrancisco Iglesias uint8_t tx_rx[2] = { 0 }; 463c95997a3SFrancisco Iglesias int num_stripes = 1; 464c95997a3SFrancisco Iglesias uint8_t busses; 465c95997a3SFrancisco Iglesias int i; 466c95997a3SFrancisco Iglesias 467c95997a3SFrancisco Iglesias if (!s->regs[R_GQSPI_DATA_STS]) { 468c95997a3SFrancisco Iglesias uint8_t imm; 469c95997a3SFrancisco Iglesias 470c95997a3SFrancisco Iglesias s->regs[R_GQSPI_GF_SNAPSHOT] = fifo32_pop(&s->fifo_g); 471c95997a3SFrancisco Iglesias DB_PRINT_L(0, "GQSPI command: %x\n", s->regs[R_GQSPI_GF_SNAPSHOT]); 472c95997a3SFrancisco Iglesias if (!s->regs[R_GQSPI_GF_SNAPSHOT]) { 473c95997a3SFrancisco Iglesias DB_PRINT_L(0, "Dummy GQSPI Delay Command Entry, Do nothing"); 474c95997a3SFrancisco Iglesias continue; 475c95997a3SFrancisco Iglesias } 476c95997a3SFrancisco Iglesias xlnx_zynqmp_qspips_update_cs_lines(s); 477c95997a3SFrancisco Iglesias 478c95997a3SFrancisco Iglesias imm = ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, IMMEDIATE_DATA); 479c95997a3SFrancisco Iglesias if (!ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, DATA_XFER)) { 480c95997a3SFrancisco Iglesias /* immedate transfer */ 481c95997a3SFrancisco Iglesias if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, TRANSMIT) || 482c95997a3SFrancisco Iglesias ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, RECIEVE)) { 483c95997a3SFrancisco Iglesias s->regs[R_GQSPI_DATA_STS] = 1; 484c95997a3SFrancisco Iglesias /* CS setup/hold - do nothing */ 485c95997a3SFrancisco Iglesias } else { 486c95997a3SFrancisco Iglesias s->regs[R_GQSPI_DATA_STS] = 0; 487c95997a3SFrancisco Iglesias } 488c95997a3SFrancisco Iglesias } else if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, EXPONENT)) { 489c95997a3SFrancisco Iglesias if (imm > 31) { 490c95997a3SFrancisco Iglesias qemu_log_mask(LOG_UNIMP, "QSPI exponential transfer too" 491c95997a3SFrancisco Iglesias " long - 2 ^ %" PRId8 " requested\n", imm); 492c95997a3SFrancisco Iglesias } 493c95997a3SFrancisco Iglesias s->regs[R_GQSPI_DATA_STS] = 1ul << imm; 494c95997a3SFrancisco Iglesias } else { 495c95997a3SFrancisco Iglesias s->regs[R_GQSPI_DATA_STS] = imm; 496c95997a3SFrancisco Iglesias } 497c95997a3SFrancisco Iglesias } 498c95997a3SFrancisco Iglesias /* Zero length transfer check */ 499c95997a3SFrancisco Iglesias if (!s->regs[R_GQSPI_DATA_STS]) { 500c95997a3SFrancisco Iglesias continue; 501c95997a3SFrancisco Iglesias } 502c95997a3SFrancisco Iglesias if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, RECIEVE) && 503c95997a3SFrancisco Iglesias fifo8_is_full(&s->rx_fifo_g)) { 504c95997a3SFrancisco Iglesias /* No space in RX fifo for transfer - try again later */ 505c95997a3SFrancisco Iglesias return; 506c95997a3SFrancisco Iglesias } 507c95997a3SFrancisco Iglesias if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, STRIPE) && 508c95997a3SFrancisco Iglesias (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, TRANSMIT) || 509c95997a3SFrancisco Iglesias ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, RECIEVE))) { 510c95997a3SFrancisco Iglesias num_stripes = 2; 511c95997a3SFrancisco Iglesias } 512c95997a3SFrancisco Iglesias if (!ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, DATA_XFER)) { 513c95997a3SFrancisco Iglesias tx_rx[0] = ARRAY_FIELD_EX32(s->regs, 514c95997a3SFrancisco Iglesias GQSPI_GF_SNAPSHOT, IMMEDIATE_DATA); 515c95997a3SFrancisco Iglesias } else if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, TRANSMIT)) { 516c95997a3SFrancisco Iglesias for (i = 0; i < num_stripes; ++i) { 517c95997a3SFrancisco Iglesias if (!fifo8_is_empty(&s->tx_fifo_g)) { 518c95997a3SFrancisco Iglesias tx_rx[i] = fifo8_pop(&s->tx_fifo_g); 519c95997a3SFrancisco Iglesias s->tx_fifo_g_align++; 520c95997a3SFrancisco Iglesias } else { 521c95997a3SFrancisco Iglesias return; 522c95997a3SFrancisco Iglesias } 523c95997a3SFrancisco Iglesias } 524c95997a3SFrancisco Iglesias } 525c95997a3SFrancisco Iglesias if (num_stripes == 1) { 526c95997a3SFrancisco Iglesias /* mirror */ 527c95997a3SFrancisco Iglesias tx_rx[1] = tx_rx[0]; 528c95997a3SFrancisco Iglesias } 529c95997a3SFrancisco Iglesias busses = ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, DATA_BUS_SELECT); 530c95997a3SFrancisco Iglesias for (i = 0; i < 2; ++i) { 531c95997a3SFrancisco Iglesias DB_PRINT_L(1, "bus %d tx = %02x\n", i, tx_rx[i]); 532c95997a3SFrancisco Iglesias tx_rx[i] = ssi_transfer(XILINX_SPIPS(s)->spi[i], tx_rx[i]); 533c95997a3SFrancisco Iglesias DB_PRINT_L(1, "bus %d rx = %02x\n", i, tx_rx[i]); 534c95997a3SFrancisco Iglesias } 535c95997a3SFrancisco Iglesias if (s->regs[R_GQSPI_DATA_STS] > 1 && 536c95997a3SFrancisco Iglesias busses == 0x3 && num_stripes == 2) { 537c95997a3SFrancisco Iglesias s->regs[R_GQSPI_DATA_STS] -= 2; 538c95997a3SFrancisco Iglesias } else if (s->regs[R_GQSPI_DATA_STS] > 0) { 539c95997a3SFrancisco Iglesias s->regs[R_GQSPI_DATA_STS]--; 540c95997a3SFrancisco Iglesias } 541c95997a3SFrancisco Iglesias if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, RECIEVE)) { 542c95997a3SFrancisco Iglesias for (i = 0; i < 2; ++i) { 543c95997a3SFrancisco Iglesias if (busses & (1 << i)) { 544c95997a3SFrancisco Iglesias DB_PRINT_L(1, "bus %d push_byte = %02x\n", i, tx_rx[i]); 545c95997a3SFrancisco Iglesias fifo8_push(&s->rx_fifo_g, tx_rx[i]); 546c95997a3SFrancisco Iglesias s->rx_fifo_g_align++; 547c95997a3SFrancisco Iglesias } 548c95997a3SFrancisco Iglesias } 549c95997a3SFrancisco Iglesias } 550c95997a3SFrancisco Iglesias if (!s->regs[R_GQSPI_DATA_STS]) { 551c95997a3SFrancisco Iglesias for (; s->tx_fifo_g_align % 4; s->tx_fifo_g_align++) { 552c95997a3SFrancisco Iglesias fifo8_pop(&s->tx_fifo_g); 553c95997a3SFrancisco Iglesias } 554c95997a3SFrancisco Iglesias for (; s->rx_fifo_g_align % 4; s->rx_fifo_g_align++) { 555c95997a3SFrancisco Iglesias fifo8_push(&s->rx_fifo_g, 0); 556c95997a3SFrancisco Iglesias } 557c95997a3SFrancisco Iglesias } 558c95997a3SFrancisco Iglesias } 559c95997a3SFrancisco Iglesias } 560c95997a3SFrancisco Iglesias 561ef06ca39SFrancisco Iglesias static int xilinx_spips_num_dummies(XilinxQSPIPS *qs, uint8_t command) 562ef06ca39SFrancisco Iglesias { 563ef06ca39SFrancisco Iglesias if (!qs) { 564ef06ca39SFrancisco Iglesias /* The SPI device is not a QSPI device */ 565ef06ca39SFrancisco Iglesias return -1; 566ef06ca39SFrancisco Iglesias } 567ef06ca39SFrancisco Iglesias 568ef06ca39SFrancisco Iglesias switch (command) { /* check for dummies */ 569ef06ca39SFrancisco Iglesias case READ: /* no dummy bytes/cycles */ 570ef06ca39SFrancisco Iglesias case PP: 571ef06ca39SFrancisco Iglesias case DPP: 572ef06ca39SFrancisco Iglesias case QPP: 573ef06ca39SFrancisco Iglesias case READ_4: 574ef06ca39SFrancisco Iglesias case PP_4: 575ef06ca39SFrancisco Iglesias case QPP_4: 576ef06ca39SFrancisco Iglesias return 0; 577ef06ca39SFrancisco Iglesias case FAST_READ: 578ef06ca39SFrancisco Iglesias case DOR: 579ef06ca39SFrancisco Iglesias case QOR: 58033e2c4d8SFrancisco Iglesias case FAST_READ_4: 581ef06ca39SFrancisco Iglesias case DOR_4: 582ef06ca39SFrancisco Iglesias case QOR_4: 583ef06ca39SFrancisco Iglesias return 1; 584ef06ca39SFrancisco Iglesias case DIOR: 585ef06ca39SFrancisco Iglesias case DIOR_4: 586ef06ca39SFrancisco Iglesias return 2; 587ef06ca39SFrancisco Iglesias case QIOR: 588ef06ca39SFrancisco Iglesias case QIOR_4: 589b8cc8503SFrancisco Iglesias return 4; 590ef06ca39SFrancisco Iglesias default: 591ef06ca39SFrancisco Iglesias return -1; 592ef06ca39SFrancisco Iglesias } 593ef06ca39SFrancisco Iglesias } 594ef06ca39SFrancisco Iglesias 595ef06ca39SFrancisco Iglesias static inline uint8_t get_addr_length(XilinxSPIPS *s, uint8_t cmd) 596ef06ca39SFrancisco Iglesias { 597ef06ca39SFrancisco Iglesias switch (cmd) { 598ef06ca39SFrancisco Iglesias case PP_4: 599ef06ca39SFrancisco Iglesias case QPP_4: 600ef06ca39SFrancisco Iglesias case READ_4: 601ef06ca39SFrancisco Iglesias case QIOR_4: 602ef06ca39SFrancisco Iglesias case FAST_READ_4: 603ef06ca39SFrancisco Iglesias case DOR_4: 604ef06ca39SFrancisco Iglesias case QOR_4: 605ef06ca39SFrancisco Iglesias case DIOR_4: 606ef06ca39SFrancisco Iglesias return 4; 607ef06ca39SFrancisco Iglesias default: 608ef06ca39SFrancisco Iglesias return (s->regs[R_CMND] & R_CMND_EXT_ADD) ? 4 : 3; 609ef06ca39SFrancisco Iglesias } 610ef06ca39SFrancisco Iglesias } 611ef06ca39SFrancisco Iglesias 61231e17060SPaolo Bonzini static void xilinx_spips_flush_txfifo(XilinxSPIPS *s) 61331e17060SPaolo Bonzini { 6144a5b6fa8SPeter Crosthwaite int debug_level = 0; 615ef06ca39SFrancisco Iglesias XilinxQSPIPS *q = (XilinxQSPIPS *) object_dynamic_cast(OBJECT(s), 616ef06ca39SFrancisco Iglesias TYPE_XILINX_QSPIPS); 6174a5b6fa8SPeter Crosthwaite 61831e17060SPaolo Bonzini for (;;) { 61931e17060SPaolo Bonzini int i; 62031e17060SPaolo Bonzini uint8_t tx = 0; 621fbe5dac7SFrancisco Iglesias uint8_t tx_rx[MAX_NUM_BUSSES] = { 0 }; 622ef06ca39SFrancisco Iglesias uint8_t dummy_cycles = 0; 623ef06ca39SFrancisco Iglesias uint8_t addr_length; 62431e17060SPaolo Bonzini 62531e17060SPaolo Bonzini if (fifo8_is_empty(&s->tx_fifo)) { 62631e17060SPaolo Bonzini xilinx_spips_update_ixr(s); 62731e17060SPaolo Bonzini return; 628fbf32752SSai Pavan Boddu } else if (s->snoop_state == SNOOP_STRIPING || 629fbf32752SSai Pavan Boddu s->snoop_state == SNOOP_NONE) { 6309151da25SPeter Crosthwaite for (i = 0; i < num_effective_busses(s); ++i) { 6319151da25SPeter Crosthwaite tx_rx[i] = fifo8_pop(&s->tx_fifo); 6329151da25SPeter Crosthwaite } 6339151da25SPeter Crosthwaite stripe8(tx_rx, num_effective_busses(s), false); 634ef06ca39SFrancisco Iglesias } else if (s->snoop_state >= SNOOP_ADDR) { 63531e17060SPaolo Bonzini tx = fifo8_pop(&s->tx_fifo); 6369151da25SPeter Crosthwaite for (i = 0; i < num_effective_busses(s); ++i) { 6379151da25SPeter Crosthwaite tx_rx[i] = tx; 63831e17060SPaolo Bonzini } 639ef06ca39SFrancisco Iglesias } else { 640ef06ca39SFrancisco Iglesias /* Extract a dummy byte and generate dummy cycles according to the 641ef06ca39SFrancisco Iglesias * link state */ 642ef06ca39SFrancisco Iglesias tx = fifo8_pop(&s->tx_fifo); 643ef06ca39SFrancisco Iglesias dummy_cycles = 8 / s->link_state; 64431e17060SPaolo Bonzini } 6459151da25SPeter Crosthwaite 6469151da25SPeter Crosthwaite for (i = 0; i < num_effective_busses(s); ++i) { 647c3725b85SFrancisco Iglesias int bus = num_effective_busses(s) - 1 - i; 648ef06ca39SFrancisco Iglesias if (dummy_cycles) { 649ef06ca39SFrancisco Iglesias int d; 650ef06ca39SFrancisco Iglesias for (d = 0; d < dummy_cycles; ++d) { 651ef06ca39SFrancisco Iglesias tx_rx[0] = ssi_transfer(s->spi[bus], (uint32_t)tx_rx[0]); 652ef06ca39SFrancisco Iglesias } 653ef06ca39SFrancisco Iglesias } else { 6544a5b6fa8SPeter Crosthwaite DB_PRINT_L(debug_level, "tx = %02x\n", tx_rx[i]); 655c3725b85SFrancisco Iglesias tx_rx[i] = ssi_transfer(s->spi[bus], (uint32_t)tx_rx[i]); 6564a5b6fa8SPeter Crosthwaite DB_PRINT_L(debug_level, "rx = %02x\n", tx_rx[i]); 6579151da25SPeter Crosthwaite } 658ef06ca39SFrancisco Iglesias } 6599151da25SPeter Crosthwaite 660ef06ca39SFrancisco Iglesias if (s->regs[R_CMND] & R_CMND_RXFIFO_DRAIN) { 661ef06ca39SFrancisco Iglesias DB_PRINT_L(debug_level, "dircarding drained rx byte\n"); 662ef06ca39SFrancisco Iglesias /* Do nothing */ 663ef06ca39SFrancisco Iglesias } else if (s->rx_discard) { 664ef06ca39SFrancisco Iglesias DB_PRINT_L(debug_level, "dircarding discarded rx byte\n"); 665ef06ca39SFrancisco Iglesias s->rx_discard -= 8 / s->link_state; 666ef06ca39SFrancisco Iglesias } else if (fifo8_is_full(&s->rx_fifo)) { 66731e17060SPaolo Bonzini s->regs[R_INTR_STATUS] |= IXR_RX_FIFO_OVERFLOW; 6684a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "rx FIFO overflow"); 6699151da25SPeter Crosthwaite } else if (s->snoop_state == SNOOP_STRIPING) { 6709151da25SPeter Crosthwaite stripe8(tx_rx, num_effective_busses(s), true); 6719151da25SPeter Crosthwaite for (i = 0; i < num_effective_busses(s); ++i) { 6729151da25SPeter Crosthwaite fifo8_push(&s->rx_fifo, (uint8_t)tx_rx[i]); 673ef06ca39SFrancisco Iglesias DB_PRINT_L(debug_level, "pushing striped rx byte\n"); 6749151da25SPeter Crosthwaite } 67531e17060SPaolo Bonzini } else { 676ef06ca39SFrancisco Iglesias DB_PRINT_L(debug_level, "pushing unstriped rx byte\n"); 6779151da25SPeter Crosthwaite fifo8_push(&s->rx_fifo, (uint8_t)tx_rx[0]); 67831e17060SPaolo Bonzini } 67931e17060SPaolo Bonzini 680ef06ca39SFrancisco Iglesias if (s->link_state_next_when) { 681ef06ca39SFrancisco Iglesias s->link_state_next_when--; 682ef06ca39SFrancisco Iglesias if (!s->link_state_next_when) { 683ef06ca39SFrancisco Iglesias s->link_state = s->link_state_next; 684ef06ca39SFrancisco Iglesias } 685ef06ca39SFrancisco Iglesias } 686ef06ca39SFrancisco Iglesias 6874a5b6fa8SPeter Crosthwaite DB_PRINT_L(debug_level, "initial snoop state: %x\n", 6884a5b6fa8SPeter Crosthwaite (unsigned)s->snoop_state); 68931e17060SPaolo Bonzini switch (s->snoop_state) { 69031e17060SPaolo Bonzini case (SNOOP_CHECKING): 691ef06ca39SFrancisco Iglesias /* Store the count of dummy bytes in the txfifo */ 692ef06ca39SFrancisco Iglesias s->cmd_dummies = xilinx_spips_num_dummies(q, tx); 693ef06ca39SFrancisco Iglesias addr_length = get_addr_length(s, tx); 694ef06ca39SFrancisco Iglesias if (s->cmd_dummies < 0) { 69531e17060SPaolo Bonzini s->snoop_state = SNOOP_NONE; 696ef06ca39SFrancisco Iglesias } else { 697ef06ca39SFrancisco Iglesias s->snoop_state = SNOOP_ADDR + addr_length - 1; 698ef06ca39SFrancisco Iglesias } 699ef06ca39SFrancisco Iglesias switch (tx) { 700ef06ca39SFrancisco Iglesias case DPP: 701ef06ca39SFrancisco Iglesias case DOR: 702ef06ca39SFrancisco Iglesias case DOR_4: 703ef06ca39SFrancisco Iglesias s->link_state_next = 2; 704ef06ca39SFrancisco Iglesias s->link_state_next_when = addr_length + s->cmd_dummies; 705ef06ca39SFrancisco Iglesias break; 706ef06ca39SFrancisco Iglesias case QPP: 707ef06ca39SFrancisco Iglesias case QPP_4: 708ef06ca39SFrancisco Iglesias case QOR: 709ef06ca39SFrancisco Iglesias case QOR_4: 710ef06ca39SFrancisco Iglesias s->link_state_next = 4; 711ef06ca39SFrancisco Iglesias s->link_state_next_when = addr_length + s->cmd_dummies; 712ef06ca39SFrancisco Iglesias break; 713ef06ca39SFrancisco Iglesias case DIOR: 714ef06ca39SFrancisco Iglesias case DIOR_4: 715ef06ca39SFrancisco Iglesias s->link_state = 2; 716ef06ca39SFrancisco Iglesias break; 717ef06ca39SFrancisco Iglesias case QIOR: 718ef06ca39SFrancisco Iglesias case QIOR_4: 719ef06ca39SFrancisco Iglesias s->link_state = 4; 720ef06ca39SFrancisco Iglesias break; 721ef06ca39SFrancisco Iglesias } 722ef06ca39SFrancisco Iglesias break; 723ef06ca39SFrancisco Iglesias case (SNOOP_ADDR): 724ef06ca39SFrancisco Iglesias /* Address has been transmitted, transmit dummy cycles now if 725ef06ca39SFrancisco Iglesias * needed */ 726ef06ca39SFrancisco Iglesias if (s->cmd_dummies < 0) { 727ef06ca39SFrancisco Iglesias s->snoop_state = SNOOP_NONE; 728ef06ca39SFrancisco Iglesias } else { 729ef06ca39SFrancisco Iglesias s->snoop_state = s->cmd_dummies; 73031e17060SPaolo Bonzini } 73131e17060SPaolo Bonzini break; 73231e17060SPaolo Bonzini case (SNOOP_STRIPING): 73331e17060SPaolo Bonzini case (SNOOP_NONE): 7344a5b6fa8SPeter Crosthwaite /* Once we hit the boring stuff - squelch debug noise */ 7354a5b6fa8SPeter Crosthwaite if (!debug_level) { 7364a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "squelching debug info ....\n"); 7374a5b6fa8SPeter Crosthwaite debug_level = 1; 7384a5b6fa8SPeter Crosthwaite } 73931e17060SPaolo Bonzini break; 74031e17060SPaolo Bonzini default: 74131e17060SPaolo Bonzini s->snoop_state--; 74231e17060SPaolo Bonzini } 7434a5b6fa8SPeter Crosthwaite DB_PRINT_L(debug_level, "final snoop state: %x\n", 7444a5b6fa8SPeter Crosthwaite (unsigned)s->snoop_state); 74531e17060SPaolo Bonzini } 74631e17060SPaolo Bonzini } 74731e17060SPaolo Bonzini 7482fdd171eSFrancisco Iglesias static inline void tx_data_bytes(Fifo8 *fifo, uint32_t value, int num, bool be) 7492fdd171eSFrancisco Iglesias { 7502fdd171eSFrancisco Iglesias int i; 7512fdd171eSFrancisco Iglesias for (i = 0; i < num && !fifo8_is_full(fifo); ++i) { 7522fdd171eSFrancisco Iglesias if (be) { 7532fdd171eSFrancisco Iglesias fifo8_push(fifo, (uint8_t)(value >> 24)); 7542fdd171eSFrancisco Iglesias value <<= 8; 7552fdd171eSFrancisco Iglesias } else { 7562fdd171eSFrancisco Iglesias fifo8_push(fifo, (uint8_t)value); 7572fdd171eSFrancisco Iglesias value >>= 8; 7582fdd171eSFrancisco Iglesias } 7592fdd171eSFrancisco Iglesias } 7602fdd171eSFrancisco Iglesias } 7612fdd171eSFrancisco Iglesias 762275e28ccSFrancisco Iglesias static void xilinx_spips_check_zero_pump(XilinxSPIPS *s) 763275e28ccSFrancisco Iglesias { 764275e28ccSFrancisco Iglesias if (!s->regs[R_TRANSFER_SIZE]) { 765275e28ccSFrancisco Iglesias return; 766275e28ccSFrancisco Iglesias } 767275e28ccSFrancisco Iglesias if (!fifo8_is_empty(&s->tx_fifo) && s->regs[R_CMND] & R_CMND_PUSH_WAIT) { 768275e28ccSFrancisco Iglesias return; 769275e28ccSFrancisco Iglesias } 770275e28ccSFrancisco Iglesias /* 771275e28ccSFrancisco Iglesias * The zero pump must never fill tx fifo such that rx overflow is 772275e28ccSFrancisco Iglesias * possible 773275e28ccSFrancisco Iglesias */ 774275e28ccSFrancisco Iglesias while (s->regs[R_TRANSFER_SIZE] && 775275e28ccSFrancisco Iglesias s->rx_fifo.num + s->tx_fifo.num < RXFF_A_Q - 3) { 776275e28ccSFrancisco Iglesias /* endianess just doesn't matter when zero pumping */ 777275e28ccSFrancisco Iglesias tx_data_bytes(&s->tx_fifo, 0, 4, false); 778275e28ccSFrancisco Iglesias s->regs[R_TRANSFER_SIZE] &= ~0x03ull; 779275e28ccSFrancisco Iglesias s->regs[R_TRANSFER_SIZE] -= 4; 780275e28ccSFrancisco Iglesias } 781275e28ccSFrancisco Iglesias } 782275e28ccSFrancisco Iglesias 783275e28ccSFrancisco Iglesias static void xilinx_spips_check_flush(XilinxSPIPS *s) 784275e28ccSFrancisco Iglesias { 785275e28ccSFrancisco Iglesias if (s->man_start_com || 786275e28ccSFrancisco Iglesias (!fifo8_is_empty(&s->tx_fifo) && 787275e28ccSFrancisco Iglesias !(s->regs[R_CONFIG] & MAN_START_EN))) { 788275e28ccSFrancisco Iglesias xilinx_spips_check_zero_pump(s); 789275e28ccSFrancisco Iglesias xilinx_spips_flush_txfifo(s); 790275e28ccSFrancisco Iglesias } 791275e28ccSFrancisco Iglesias if (fifo8_is_empty(&s->tx_fifo) && !s->regs[R_TRANSFER_SIZE]) { 792275e28ccSFrancisco Iglesias s->man_start_com = false; 793275e28ccSFrancisco Iglesias } 794275e28ccSFrancisco Iglesias xilinx_spips_update_ixr(s); 795275e28ccSFrancisco Iglesias } 796275e28ccSFrancisco Iglesias 797c95997a3SFrancisco Iglesias static void xlnx_zynqmp_qspips_check_flush(XlnxZynqMPQSPIPS *s) 798c95997a3SFrancisco Iglesias { 799c95997a3SFrancisco Iglesias bool gqspi_has_work = s->regs[R_GQSPI_DATA_STS] || 800c95997a3SFrancisco Iglesias !fifo32_is_empty(&s->fifo_g); 801c95997a3SFrancisco Iglesias 802c95997a3SFrancisco Iglesias if (ARRAY_FIELD_EX32(s->regs, GQSPI_SELECT, GENERIC_QSPI_EN)) { 803c95997a3SFrancisco Iglesias if (s->man_start_com_g || (gqspi_has_work && 804c95997a3SFrancisco Iglesias !ARRAY_FIELD_EX32(s->regs, GQSPI_CNFG, GEN_FIFO_START_MODE))) { 805c95997a3SFrancisco Iglesias xlnx_zynqmp_qspips_flush_fifo_g(s); 806c95997a3SFrancisco Iglesias } 807c95997a3SFrancisco Iglesias } else { 808c95997a3SFrancisco Iglesias xilinx_spips_check_flush(XILINX_SPIPS(s)); 809c95997a3SFrancisco Iglesias } 810c95997a3SFrancisco Iglesias if (!gqspi_has_work) { 811c95997a3SFrancisco Iglesias s->man_start_com_g = false; 812c95997a3SFrancisco Iglesias } 813c95997a3SFrancisco Iglesias xlnx_zynqmp_qspips_update_ixr(s); 814c95997a3SFrancisco Iglesias } 815c95997a3SFrancisco Iglesias 8162fdd171eSFrancisco Iglesias static inline int rx_data_bytes(Fifo8 *fifo, uint8_t *value, int max) 81731e17060SPaolo Bonzini { 81831e17060SPaolo Bonzini int i; 81931e17060SPaolo Bonzini 8202fdd171eSFrancisco Iglesias for (i = 0; i < max && !fifo8_is_empty(fifo); ++i) { 8212fdd171eSFrancisco Iglesias value[i] = fifo8_pop(fifo); 82231e17060SPaolo Bonzini } 8232fdd171eSFrancisco Iglesias return max - i; 82431e17060SPaolo Bonzini } 82531e17060SPaolo Bonzini 826c95997a3SFrancisco Iglesias static const void *pop_buf(Fifo8 *fifo, uint32_t max, uint32_t *num) 827c95997a3SFrancisco Iglesias { 828c95997a3SFrancisco Iglesias void *ret; 829c95997a3SFrancisco Iglesias 830c95997a3SFrancisco Iglesias if (max == 0 || max > fifo->num) { 831c95997a3SFrancisco Iglesias abort(); 832c95997a3SFrancisco Iglesias } 833c95997a3SFrancisco Iglesias *num = MIN(fifo->capacity - fifo->head, max); 834c95997a3SFrancisco Iglesias ret = &fifo->data[fifo->head]; 835c95997a3SFrancisco Iglesias fifo->head += *num; 836c95997a3SFrancisco Iglesias fifo->head %= fifo->capacity; 837c95997a3SFrancisco Iglesias fifo->num -= *num; 838c95997a3SFrancisco Iglesias return ret; 839c95997a3SFrancisco Iglesias } 840c95997a3SFrancisco Iglesias 841c95997a3SFrancisco Iglesias static void xlnx_zynqmp_qspips_notify(void *opaque) 842c95997a3SFrancisco Iglesias { 843c95997a3SFrancisco Iglesias XlnxZynqMPQSPIPS *rq = XLNX_ZYNQMP_QSPIPS(opaque); 844c95997a3SFrancisco Iglesias XilinxSPIPS *s = XILINX_SPIPS(rq); 845c95997a3SFrancisco Iglesias Fifo8 *recv_fifo; 846c95997a3SFrancisco Iglesias 847c95997a3SFrancisco Iglesias if (ARRAY_FIELD_EX32(rq->regs, GQSPI_SELECT, GENERIC_QSPI_EN)) { 848c95997a3SFrancisco Iglesias if (!(ARRAY_FIELD_EX32(rq->regs, GQSPI_CNFG, MODE_EN) == 2)) { 849c95997a3SFrancisco Iglesias return; 850c95997a3SFrancisco Iglesias } 851c95997a3SFrancisco Iglesias recv_fifo = &rq->rx_fifo_g; 852c95997a3SFrancisco Iglesias } else { 853c95997a3SFrancisco Iglesias if (!(s->regs[R_CMND] & R_CMND_DMA_EN)) { 854c95997a3SFrancisco Iglesias return; 855c95997a3SFrancisco Iglesias } 856c95997a3SFrancisco Iglesias recv_fifo = &s->rx_fifo; 857c95997a3SFrancisco Iglesias } 858c95997a3SFrancisco Iglesias while (recv_fifo->num >= 4 859c95997a3SFrancisco Iglesias && stream_can_push(rq->dma, xlnx_zynqmp_qspips_notify, rq)) 860c95997a3SFrancisco Iglesias { 861c95997a3SFrancisco Iglesias size_t ret; 862c95997a3SFrancisco Iglesias uint32_t num; 86321d887cdSSai Pavan Boddu const void *rxd; 86421d887cdSSai Pavan Boddu int len; 86521d887cdSSai Pavan Boddu 86621d887cdSSai Pavan Boddu len = recv_fifo->num >= rq->dma_burst_size ? rq->dma_burst_size : 86721d887cdSSai Pavan Boddu recv_fifo->num; 86821d887cdSSai Pavan Boddu rxd = pop_buf(recv_fifo, len, &num); 869c95997a3SFrancisco Iglesias 870c95997a3SFrancisco Iglesias memcpy(rq->dma_buf, rxd, num); 871c95997a3SFrancisco Iglesias 87251b19950SEdgar E. Iglesias ret = stream_push(rq->dma, rq->dma_buf, num, false); 87321d887cdSSai Pavan Boddu assert(ret == num); 874c95997a3SFrancisco Iglesias xlnx_zynqmp_qspips_check_flush(rq); 875c95997a3SFrancisco Iglesias } 876c95997a3SFrancisco Iglesias } 877c95997a3SFrancisco Iglesias 87831e17060SPaolo Bonzini static uint64_t xilinx_spips_read(void *opaque, hwaddr addr, 87931e17060SPaolo Bonzini unsigned size) 88031e17060SPaolo Bonzini { 88131e17060SPaolo Bonzini XilinxSPIPS *s = opaque; 88231e17060SPaolo Bonzini uint32_t mask = ~0; 88331e17060SPaolo Bonzini uint32_t ret; 884b0b7ae62SPeter Crosthwaite uint8_t rx_buf[4]; 8852fdd171eSFrancisco Iglesias int shortfall; 88631e17060SPaolo Bonzini 88731e17060SPaolo Bonzini addr >>= 2; 88831e17060SPaolo Bonzini switch (addr) { 88931e17060SPaolo Bonzini case R_CONFIG: 8902133a5f6SPeter Crosthwaite mask = ~(R_CONFIG_RSVD | MAN_START_COM); 89131e17060SPaolo Bonzini break; 89231e17060SPaolo Bonzini case R_INTR_STATUS: 89387920b44SPeter Crosthwaite ret = s->regs[addr] & IXR_ALL; 89487920b44SPeter Crosthwaite s->regs[addr] = 0; 8954a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret); 8962e1cf2c9SFrancisco Iglesias xilinx_spips_update_ixr(s); 89787920b44SPeter Crosthwaite return ret; 89831e17060SPaolo Bonzini case R_INTR_MASK: 89931e17060SPaolo Bonzini mask = IXR_ALL; 90031e17060SPaolo Bonzini break; 90131e17060SPaolo Bonzini case R_EN: 90231e17060SPaolo Bonzini mask = 0x1; 90331e17060SPaolo Bonzini break; 90431e17060SPaolo Bonzini case R_SLAVE_IDLE_COUNT: 90531e17060SPaolo Bonzini mask = 0xFF; 90631e17060SPaolo Bonzini break; 90731e17060SPaolo Bonzini case R_MOD_ID: 90831e17060SPaolo Bonzini mask = 0x01FFFFFF; 90931e17060SPaolo Bonzini break; 91031e17060SPaolo Bonzini case R_INTR_EN: 91131e17060SPaolo Bonzini case R_INTR_DIS: 91231e17060SPaolo Bonzini case R_TX_DATA: 91331e17060SPaolo Bonzini mask = 0; 91431e17060SPaolo Bonzini break; 91531e17060SPaolo Bonzini case R_RX_DATA: 916b0b7ae62SPeter Crosthwaite memset(rx_buf, 0, sizeof(rx_buf)); 9172fdd171eSFrancisco Iglesias shortfall = rx_data_bytes(&s->rx_fifo, rx_buf, s->num_txrx_bytes); 9182fdd171eSFrancisco Iglesias ret = s->regs[R_CONFIG] & R_CONFIG_ENDIAN ? 9192fdd171eSFrancisco Iglesias cpu_to_be32(*(uint32_t *)rx_buf) : 9202fdd171eSFrancisco Iglesias cpu_to_le32(*(uint32_t *)rx_buf); 9212fdd171eSFrancisco Iglesias if (!(s->regs[R_CONFIG] & R_CONFIG_ENDIAN)) { 9222fdd171eSFrancisco Iglesias ret <<= 8 * shortfall; 9232fdd171eSFrancisco Iglesias } 9244a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret); 925c95997a3SFrancisco Iglesias xilinx_spips_check_flush(s); 92631e17060SPaolo Bonzini xilinx_spips_update_ixr(s); 92731e17060SPaolo Bonzini return ret; 92831e17060SPaolo Bonzini } 9294a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4, 9304a5b6fa8SPeter Crosthwaite s->regs[addr] & mask); 93131e17060SPaolo Bonzini return s->regs[addr] & mask; 93231e17060SPaolo Bonzini 93331e17060SPaolo Bonzini } 93431e17060SPaolo Bonzini 935c95997a3SFrancisco Iglesias static uint64_t xlnx_zynqmp_qspips_read(void *opaque, 936c95997a3SFrancisco Iglesias hwaddr addr, unsigned size) 937c95997a3SFrancisco Iglesias { 938c95997a3SFrancisco Iglesias XlnxZynqMPQSPIPS *s = XLNX_ZYNQMP_QSPIPS(opaque); 939c95997a3SFrancisco Iglesias uint32_t reg = addr / 4; 940c95997a3SFrancisco Iglesias uint32_t ret; 941c95997a3SFrancisco Iglesias uint8_t rx_buf[4]; 942c95997a3SFrancisco Iglesias int shortfall; 943c95997a3SFrancisco Iglesias 944c95997a3SFrancisco Iglesias if (reg <= R_MOD_ID) { 945c95997a3SFrancisco Iglesias return xilinx_spips_read(opaque, addr, size); 946c95997a3SFrancisco Iglesias } else { 947c95997a3SFrancisco Iglesias switch (reg) { 948c95997a3SFrancisco Iglesias case R_GQSPI_RXD: 949c95997a3SFrancisco Iglesias if (fifo8_is_empty(&s->rx_fifo_g)) { 950c95997a3SFrancisco Iglesias qemu_log_mask(LOG_GUEST_ERROR, 951c95997a3SFrancisco Iglesias "Read from empty GQSPI RX FIFO\n"); 952c95997a3SFrancisco Iglesias return 0; 953c95997a3SFrancisco Iglesias } 954c95997a3SFrancisco Iglesias memset(rx_buf, 0, sizeof(rx_buf)); 955c95997a3SFrancisco Iglesias shortfall = rx_data_bytes(&s->rx_fifo_g, rx_buf, 956c95997a3SFrancisco Iglesias XILINX_SPIPS(s)->num_txrx_bytes); 957c95997a3SFrancisco Iglesias ret = ARRAY_FIELD_EX32(s->regs, GQSPI_CNFG, ENDIAN) ? 958c95997a3SFrancisco Iglesias cpu_to_be32(*(uint32_t *)rx_buf) : 959c95997a3SFrancisco Iglesias cpu_to_le32(*(uint32_t *)rx_buf); 960c95997a3SFrancisco Iglesias if (!ARRAY_FIELD_EX32(s->regs, GQSPI_CNFG, ENDIAN)) { 961c95997a3SFrancisco Iglesias ret <<= 8 * shortfall; 962c95997a3SFrancisco Iglesias } 963c95997a3SFrancisco Iglesias xlnx_zynqmp_qspips_check_flush(s); 964c95997a3SFrancisco Iglesias xlnx_zynqmp_qspips_update_ixr(s); 965c95997a3SFrancisco Iglesias return ret; 966c95997a3SFrancisco Iglesias default: 967c95997a3SFrancisco Iglesias return s->regs[reg]; 968c95997a3SFrancisco Iglesias } 969c95997a3SFrancisco Iglesias } 970c95997a3SFrancisco Iglesias } 971c95997a3SFrancisco Iglesias 97231e17060SPaolo Bonzini static void xilinx_spips_write(void *opaque, hwaddr addr, 97331e17060SPaolo Bonzini uint64_t value, unsigned size) 97431e17060SPaolo Bonzini { 97531e17060SPaolo Bonzini int mask = ~0; 97631e17060SPaolo Bonzini XilinxSPIPS *s = opaque; 9773a6606c7SSai Pavan Boddu bool try_flush = true; 97831e17060SPaolo Bonzini 9794a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr, (unsigned)value); 98031e17060SPaolo Bonzini addr >>= 2; 98131e17060SPaolo Bonzini switch (addr) { 98231e17060SPaolo Bonzini case R_CONFIG: 9832133a5f6SPeter Crosthwaite mask = ~(R_CONFIG_RSVD | MAN_START_COM); 984275e28ccSFrancisco Iglesias if ((value & MAN_START_COM) && (s->regs[R_CONFIG] & MAN_START_EN)) { 985275e28ccSFrancisco Iglesias s->man_start_com = true; 98631e17060SPaolo Bonzini } 98731e17060SPaolo Bonzini break; 98831e17060SPaolo Bonzini case R_INTR_STATUS: 98931e17060SPaolo Bonzini mask = IXR_ALL; 99031e17060SPaolo Bonzini s->regs[R_INTR_STATUS] &= ~(mask & value); 99131e17060SPaolo Bonzini goto no_reg_update; 99231e17060SPaolo Bonzini case R_INTR_DIS: 99331e17060SPaolo Bonzini mask = IXR_ALL; 99431e17060SPaolo Bonzini s->regs[R_INTR_MASK] &= ~(mask & value); 99531e17060SPaolo Bonzini goto no_reg_update; 99631e17060SPaolo Bonzini case R_INTR_EN: 99731e17060SPaolo Bonzini mask = IXR_ALL; 99831e17060SPaolo Bonzini s->regs[R_INTR_MASK] |= mask & value; 99931e17060SPaolo Bonzini goto no_reg_update; 100031e17060SPaolo Bonzini case R_EN: 100131e17060SPaolo Bonzini mask = 0x1; 100231e17060SPaolo Bonzini break; 100331e17060SPaolo Bonzini case R_SLAVE_IDLE_COUNT: 100431e17060SPaolo Bonzini mask = 0xFF; 100531e17060SPaolo Bonzini break; 100631e17060SPaolo Bonzini case R_RX_DATA: 100731e17060SPaolo Bonzini case R_INTR_MASK: 100831e17060SPaolo Bonzini case R_MOD_ID: 100931e17060SPaolo Bonzini mask = 0; 101031e17060SPaolo Bonzini break; 101131e17060SPaolo Bonzini case R_TX_DATA: 10122fdd171eSFrancisco Iglesias tx_data_bytes(&s->tx_fifo, (uint32_t)value, s->num_txrx_bytes, 10132fdd171eSFrancisco Iglesias s->regs[R_CONFIG] & R_CONFIG_ENDIAN); 101431e17060SPaolo Bonzini goto no_reg_update; 101531e17060SPaolo Bonzini case R_TXD1: 10162fdd171eSFrancisco Iglesias tx_data_bytes(&s->tx_fifo, (uint32_t)value, 1, 10172fdd171eSFrancisco Iglesias s->regs[R_CONFIG] & R_CONFIG_ENDIAN); 101831e17060SPaolo Bonzini goto no_reg_update; 101931e17060SPaolo Bonzini case R_TXD2: 10202fdd171eSFrancisco Iglesias tx_data_bytes(&s->tx_fifo, (uint32_t)value, 2, 10212fdd171eSFrancisco Iglesias s->regs[R_CONFIG] & R_CONFIG_ENDIAN); 102231e17060SPaolo Bonzini goto no_reg_update; 102331e17060SPaolo Bonzini case R_TXD3: 10242fdd171eSFrancisco Iglesias tx_data_bytes(&s->tx_fifo, (uint32_t)value, 3, 10252fdd171eSFrancisco Iglesias s->regs[R_CONFIG] & R_CONFIG_ENDIAN); 102631e17060SPaolo Bonzini goto no_reg_update; 10273a6606c7SSai Pavan Boddu /* Skip SPI bus update for below registers writes */ 10283a6606c7SSai Pavan Boddu case R_GPIO: 10293a6606c7SSai Pavan Boddu case R_LPBK_DLY_ADJ: 10303a6606c7SSai Pavan Boddu case R_IOU_TAPDLY_BYPASS: 10313a6606c7SSai Pavan Boddu case R_DUMMY_CYCLE_EN: 10323a6606c7SSai Pavan Boddu case R_ECO: 10333a6606c7SSai Pavan Boddu try_flush = false; 10343a6606c7SSai Pavan Boddu break; 103531e17060SPaolo Bonzini } 103631e17060SPaolo Bonzini s->regs[addr] = (s->regs[addr] & ~mask) | (value & mask); 103731e17060SPaolo Bonzini no_reg_update: 10383a6606c7SSai Pavan Boddu if (try_flush) { 1039c4f08ffeSPeter Crosthwaite xilinx_spips_update_cs_lines(s); 1040275e28ccSFrancisco Iglesias xilinx_spips_check_flush(s); 104131e17060SPaolo Bonzini xilinx_spips_update_cs_lines(s); 1042c4f08ffeSPeter Crosthwaite xilinx_spips_update_ixr(s); 104331e17060SPaolo Bonzini } 10443a6606c7SSai Pavan Boddu } 104531e17060SPaolo Bonzini 104631e17060SPaolo Bonzini static const MemoryRegionOps spips_ops = { 104731e17060SPaolo Bonzini .read = xilinx_spips_read, 104831e17060SPaolo Bonzini .write = xilinx_spips_write, 104931e17060SPaolo Bonzini .endianness = DEVICE_LITTLE_ENDIAN, 105031e17060SPaolo Bonzini }; 105131e17060SPaolo Bonzini 1052252b99baSKONRAD Frederic static void xilinx_qspips_invalidate_mmio_ptr(XilinxQSPIPS *q) 1053252b99baSKONRAD Frederic { 105483c3a1f6SKONRAD Frederic q->lqspi_cached_addr = ~0ULL; 1055252b99baSKONRAD Frederic } 1056252b99baSKONRAD Frederic 1057b5cd9143SPeter Crosthwaite static void xilinx_qspips_write(void *opaque, hwaddr addr, 1058b5cd9143SPeter Crosthwaite uint64_t value, unsigned size) 1059b5cd9143SPeter Crosthwaite { 1060b5cd9143SPeter Crosthwaite XilinxQSPIPS *q = XILINX_QSPIPS(opaque); 1061ef06ca39SFrancisco Iglesias XilinxSPIPS *s = XILINX_SPIPS(opaque); 1062b5cd9143SPeter Crosthwaite 1063b5cd9143SPeter Crosthwaite xilinx_spips_write(opaque, addr, value, size); 1064b5cd9143SPeter Crosthwaite addr >>= 2; 1065b5cd9143SPeter Crosthwaite 1066b5cd9143SPeter Crosthwaite if (addr == R_LQSPI_CFG) { 1067252b99baSKONRAD Frederic xilinx_qspips_invalidate_mmio_ptr(q); 1068b5cd9143SPeter Crosthwaite } 1069ef06ca39SFrancisco Iglesias if (s->regs[R_CMND] & R_CMND_RXFIFO_DRAIN) { 1070ef06ca39SFrancisco Iglesias fifo8_reset(&s->rx_fifo); 1071ef06ca39SFrancisco Iglesias } 1072b5cd9143SPeter Crosthwaite } 1073b5cd9143SPeter Crosthwaite 1074c95997a3SFrancisco Iglesias static void xlnx_zynqmp_qspips_write(void *opaque, hwaddr addr, 1075c95997a3SFrancisco Iglesias uint64_t value, unsigned size) 1076c95997a3SFrancisco Iglesias { 1077c95997a3SFrancisco Iglesias XlnxZynqMPQSPIPS *s = XLNX_ZYNQMP_QSPIPS(opaque); 1078c95997a3SFrancisco Iglesias uint32_t reg = addr / 4; 1079c95997a3SFrancisco Iglesias 1080c95997a3SFrancisco Iglesias if (reg <= R_MOD_ID) { 1081c95997a3SFrancisco Iglesias xilinx_qspips_write(opaque, addr, value, size); 1082c95997a3SFrancisco Iglesias } else { 1083c95997a3SFrancisco Iglesias switch (reg) { 1084c95997a3SFrancisco Iglesias case R_GQSPI_CNFG: 1085c95997a3SFrancisco Iglesias if (FIELD_EX32(value, GQSPI_CNFG, GEN_FIFO_START) && 1086c95997a3SFrancisco Iglesias ARRAY_FIELD_EX32(s->regs, GQSPI_CNFG, GEN_FIFO_START_MODE)) { 1087c95997a3SFrancisco Iglesias s->man_start_com_g = true; 1088c95997a3SFrancisco Iglesias } 1089c95997a3SFrancisco Iglesias s->regs[reg] = value & ~(R_GQSPI_CNFG_GEN_FIFO_START_MASK); 1090c95997a3SFrancisco Iglesias break; 1091c95997a3SFrancisco Iglesias case R_GQSPI_GEN_FIFO: 1092c95997a3SFrancisco Iglesias if (!fifo32_is_full(&s->fifo_g)) { 1093c95997a3SFrancisco Iglesias fifo32_push(&s->fifo_g, value); 1094c95997a3SFrancisco Iglesias } 1095c95997a3SFrancisco Iglesias break; 1096c95997a3SFrancisco Iglesias case R_GQSPI_TXD: 1097c95997a3SFrancisco Iglesias tx_data_bytes(&s->tx_fifo_g, (uint32_t)value, 4, 1098c95997a3SFrancisco Iglesias ARRAY_FIELD_EX32(s->regs, GQSPI_CNFG, ENDIAN)); 1099c95997a3SFrancisco Iglesias break; 1100c95997a3SFrancisco Iglesias case R_GQSPI_FIFO_CTRL: 1101c95997a3SFrancisco Iglesias if (FIELD_EX32(value, GQSPI_FIFO_CTRL, GENERIC_FIFO_RESET)) { 1102c95997a3SFrancisco Iglesias fifo32_reset(&s->fifo_g); 1103c95997a3SFrancisco Iglesias } 1104c95997a3SFrancisco Iglesias if (FIELD_EX32(value, GQSPI_FIFO_CTRL, TX_FIFO_RESET)) { 1105c95997a3SFrancisco Iglesias fifo8_reset(&s->tx_fifo_g); 1106c95997a3SFrancisco Iglesias } 1107c95997a3SFrancisco Iglesias if (FIELD_EX32(value, GQSPI_FIFO_CTRL, RX_FIFO_RESET)) { 1108c95997a3SFrancisco Iglesias fifo8_reset(&s->rx_fifo_g); 1109c95997a3SFrancisco Iglesias } 1110c95997a3SFrancisco Iglesias break; 1111c95997a3SFrancisco Iglesias case R_GQSPI_IDR: 1112c95997a3SFrancisco Iglesias s->regs[R_GQSPI_IMR] |= value; 1113c95997a3SFrancisco Iglesias break; 1114c95997a3SFrancisco Iglesias case R_GQSPI_IER: 1115c95997a3SFrancisco Iglesias s->regs[R_GQSPI_IMR] &= ~value; 1116c95997a3SFrancisco Iglesias break; 1117c95997a3SFrancisco Iglesias case R_GQSPI_ISR: 1118c95997a3SFrancisco Iglesias s->regs[R_GQSPI_ISR] &= ~value; 1119c95997a3SFrancisco Iglesias break; 1120c95997a3SFrancisco Iglesias case R_GQSPI_IMR: 1121c95997a3SFrancisco Iglesias case R_GQSPI_RXD: 1122c95997a3SFrancisco Iglesias case R_GQSPI_GF_SNAPSHOT: 1123c95997a3SFrancisco Iglesias case R_GQSPI_MOD_ID: 1124c95997a3SFrancisco Iglesias break; 1125c95997a3SFrancisco Iglesias default: 1126c95997a3SFrancisco Iglesias s->regs[reg] = value; 1127c95997a3SFrancisco Iglesias break; 1128c95997a3SFrancisco Iglesias } 1129c95997a3SFrancisco Iglesias xlnx_zynqmp_qspips_update_cs_lines(s); 1130c95997a3SFrancisco Iglesias xlnx_zynqmp_qspips_check_flush(s); 1131c95997a3SFrancisco Iglesias xlnx_zynqmp_qspips_update_cs_lines(s); 1132c95997a3SFrancisco Iglesias xlnx_zynqmp_qspips_update_ixr(s); 1133c95997a3SFrancisco Iglesias } 1134c95997a3SFrancisco Iglesias xlnx_zynqmp_qspips_notify(s); 1135c95997a3SFrancisco Iglesias } 1136c95997a3SFrancisco Iglesias 1137b5cd9143SPeter Crosthwaite static const MemoryRegionOps qspips_ops = { 1138b5cd9143SPeter Crosthwaite .read = xilinx_spips_read, 1139b5cd9143SPeter Crosthwaite .write = xilinx_qspips_write, 1140b5cd9143SPeter Crosthwaite .endianness = DEVICE_LITTLE_ENDIAN, 1141b5cd9143SPeter Crosthwaite }; 1142b5cd9143SPeter Crosthwaite 1143c95997a3SFrancisco Iglesias static const MemoryRegionOps xlnx_zynqmp_qspips_ops = { 1144c95997a3SFrancisco Iglesias .read = xlnx_zynqmp_qspips_read, 1145c95997a3SFrancisco Iglesias .write = xlnx_zynqmp_qspips_write, 1146c95997a3SFrancisco Iglesias .endianness = DEVICE_LITTLE_ENDIAN, 1147c95997a3SFrancisco Iglesias }; 1148c95997a3SFrancisco Iglesias 114931e17060SPaolo Bonzini #define LQSPI_CACHE_SIZE 1024 115031e17060SPaolo Bonzini 1151252b99baSKONRAD Frederic static void lqspi_load_cache(void *opaque, hwaddr addr) 115231e17060SPaolo Bonzini { 11536b91f015SPeter Crosthwaite XilinxQSPIPS *q = opaque; 115431e17060SPaolo Bonzini XilinxSPIPS *s = opaque; 1155252b99baSKONRAD Frederic int i; 1156252b99baSKONRAD Frederic int flash_addr = ((addr & ~(LQSPI_CACHE_SIZE - 1)) 1157252b99baSKONRAD Frederic / num_effective_busses(s)); 1158ec7e429bSPhilippe Mathieu-Daudé int peripheral = flash_addr >> LQSPI_ADDRESS_BITS; 115931e17060SPaolo Bonzini int cache_entry = 0; 116015408b42SPeter Crosthwaite uint32_t u_page_save = s->regs[R_LQSPI_STS] & ~LQSPI_CFG_U_PAGE; 116115408b42SPeter Crosthwaite 1162252b99baSKONRAD Frederic if (addr < q->lqspi_cached_addr || 1163252b99baSKONRAD Frederic addr > q->lqspi_cached_addr + LQSPI_CACHE_SIZE - 4) { 1164252b99baSKONRAD Frederic xilinx_qspips_invalidate_mmio_ptr(q); 116515408b42SPeter Crosthwaite s->regs[R_LQSPI_STS] &= ~LQSPI_CFG_U_PAGE; 1166ec7e429bSPhilippe Mathieu-Daudé s->regs[R_LQSPI_STS] |= peripheral ? LQSPI_CFG_U_PAGE : 0; 116731e17060SPaolo Bonzini 11684a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "config reg status: %08x\n", s->regs[R_LQSPI_CFG]); 116931e17060SPaolo Bonzini 117031e17060SPaolo Bonzini fifo8_reset(&s->tx_fifo); 117131e17060SPaolo Bonzini fifo8_reset(&s->rx_fifo); 117231e17060SPaolo Bonzini 117331e17060SPaolo Bonzini /* instruction */ 11744a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "pushing read instruction: %02x\n", 11754a5b6fa8SPeter Crosthwaite (unsigned)(uint8_t)(s->regs[R_LQSPI_CFG] & 11764a5b6fa8SPeter Crosthwaite LQSPI_CFG_INST_CODE)); 117731e17060SPaolo Bonzini fifo8_push(&s->tx_fifo, s->regs[R_LQSPI_CFG] & LQSPI_CFG_INST_CODE); 117831e17060SPaolo Bonzini /* read address */ 11794a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "pushing read address %06x\n", flash_addr); 1180fbfaa507SFrancisco Iglesias if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_ADDR4) { 1181fbfaa507SFrancisco Iglesias fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 24)); 1182fbfaa507SFrancisco Iglesias } 118331e17060SPaolo Bonzini fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 16)); 118431e17060SPaolo Bonzini fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 8)); 118531e17060SPaolo Bonzini fifo8_push(&s->tx_fifo, (uint8_t)flash_addr); 118631e17060SPaolo Bonzini /* mode bits */ 118731e17060SPaolo Bonzini if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_MODE_EN) { 118831e17060SPaolo Bonzini fifo8_push(&s->tx_fifo, extract32(s->regs[R_LQSPI_CFG], 118931e17060SPaolo Bonzini LQSPI_CFG_MODE_SHIFT, 119031e17060SPaolo Bonzini LQSPI_CFG_MODE_WIDTH)); 119131e17060SPaolo Bonzini } 119231e17060SPaolo Bonzini /* dummy bytes */ 119331e17060SPaolo Bonzini for (i = 0; i < (extract32(s->regs[R_LQSPI_CFG], LQSPI_CFG_DUMMY_SHIFT, 119431e17060SPaolo Bonzini LQSPI_CFG_DUMMY_WIDTH)); ++i) { 11954a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "pushing dummy byte\n"); 119631e17060SPaolo Bonzini fifo8_push(&s->tx_fifo, 0); 119731e17060SPaolo Bonzini } 1198c4f08ffeSPeter Crosthwaite xilinx_spips_update_cs_lines(s); 119931e17060SPaolo Bonzini xilinx_spips_flush_txfifo(s); 120031e17060SPaolo Bonzini fifo8_reset(&s->rx_fifo); 120131e17060SPaolo Bonzini 12024a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "starting QSPI data read\n"); 120331e17060SPaolo Bonzini 1204b0b7ae62SPeter Crosthwaite while (cache_entry < LQSPI_CACHE_SIZE) { 1205b0b7ae62SPeter Crosthwaite for (i = 0; i < 64; ++i) { 12062fdd171eSFrancisco Iglesias tx_data_bytes(&s->tx_fifo, 0, 1, false); 1207a66418f6SPeter Crosthwaite } 120831e17060SPaolo Bonzini xilinx_spips_flush_txfifo(s); 1209b0b7ae62SPeter Crosthwaite for (i = 0; i < 64; ++i) { 12102fdd171eSFrancisco Iglesias rx_data_bytes(&s->rx_fifo, &q->lqspi_buf[cache_entry++], 1); 1211a66418f6SPeter Crosthwaite } 121231e17060SPaolo Bonzini } 121331e17060SPaolo Bonzini 121415408b42SPeter Crosthwaite s->regs[R_LQSPI_STS] &= ~LQSPI_CFG_U_PAGE; 121515408b42SPeter Crosthwaite s->regs[R_LQSPI_STS] |= u_page_save; 121631e17060SPaolo Bonzini xilinx_spips_update_cs_lines(s); 121731e17060SPaolo Bonzini 1218b0b7ae62SPeter Crosthwaite q->lqspi_cached_addr = flash_addr * num_effective_busses(s); 1219252b99baSKONRAD Frederic } 1220252b99baSKONRAD Frederic } 1221252b99baSKONRAD Frederic 12225937bd50SPhilippe Mathieu-Daudé static MemTxResult lqspi_read(void *opaque, hwaddr addr, uint64_t *value, 12235937bd50SPhilippe Mathieu-Daudé unsigned size, MemTxAttrs attrs) 1224252b99baSKONRAD Frederic { 12255937bd50SPhilippe Mathieu-Daudé XilinxQSPIPS *q = XILINX_QSPIPS(opaque); 1226252b99baSKONRAD Frederic 1227252b99baSKONRAD Frederic if (addr >= q->lqspi_cached_addr && 1228252b99baSKONRAD Frederic addr <= q->lqspi_cached_addr + LQSPI_CACHE_SIZE - 4) { 1229252b99baSKONRAD Frederic uint8_t *retp = &q->lqspi_buf[addr - q->lqspi_cached_addr]; 12305937bd50SPhilippe Mathieu-Daudé *value = cpu_to_le32(*(uint32_t *)retp); 12315937bd50SPhilippe Mathieu-Daudé DB_PRINT_L(1, "addr: %08" HWADDR_PRIx ", data: %08" PRIx64 "\n", 12325937bd50SPhilippe Mathieu-Daudé addr, *value); 12335937bd50SPhilippe Mathieu-Daudé return MEMTX_OK; 123431e17060SPaolo Bonzini } 12355937bd50SPhilippe Mathieu-Daudé 12365937bd50SPhilippe Mathieu-Daudé lqspi_load_cache(opaque, addr); 12375937bd50SPhilippe Mathieu-Daudé return lqspi_read(opaque, addr, value, size, attrs); 123831e17060SPaolo Bonzini } 123931e17060SPaolo Bonzini 1240936a236cSPhilippe Mathieu-Daudé static MemTxResult lqspi_write(void *opaque, hwaddr offset, uint64_t value, 1241936a236cSPhilippe Mathieu-Daudé unsigned size, MemTxAttrs attrs) 1242936a236cSPhilippe Mathieu-Daudé { 1243936a236cSPhilippe Mathieu-Daudé /* 1244936a236cSPhilippe Mathieu-Daudé * From UG1085, Chapter 24 (Quad-SPI controllers): 1245936a236cSPhilippe Mathieu-Daudé * - Writes are ignored 1246936a236cSPhilippe Mathieu-Daudé * - AXI writes generate an external AXI slave error (SLVERR) 1247936a236cSPhilippe Mathieu-Daudé */ 1248936a236cSPhilippe Mathieu-Daudé qemu_log_mask(LOG_GUEST_ERROR, "%s Unexpected %u-bit access to 0x%" PRIx64 1249936a236cSPhilippe Mathieu-Daudé " (value: 0x%" PRIx64 "\n", 1250936a236cSPhilippe Mathieu-Daudé __func__, size << 3, offset, value); 1251936a236cSPhilippe Mathieu-Daudé 1252936a236cSPhilippe Mathieu-Daudé return MEMTX_ERROR; 1253936a236cSPhilippe Mathieu-Daudé } 1254936a236cSPhilippe Mathieu-Daudé 125531e17060SPaolo Bonzini static const MemoryRegionOps lqspi_ops = { 12565937bd50SPhilippe Mathieu-Daudé .read_with_attrs = lqspi_read, 1257936a236cSPhilippe Mathieu-Daudé .write_with_attrs = lqspi_write, 125831e17060SPaolo Bonzini .endianness = DEVICE_NATIVE_ENDIAN, 1259526668c7SPhilippe Mathieu-Daudé .impl = { 1260526668c7SPhilippe Mathieu-Daudé .min_access_size = 4, 1261526668c7SPhilippe Mathieu-Daudé .max_access_size = 4, 1262526668c7SPhilippe Mathieu-Daudé }, 126331e17060SPaolo Bonzini .valid = { 1264b0b7ae62SPeter Crosthwaite .min_access_size = 1, 126531e17060SPaolo Bonzini .max_access_size = 4 126631e17060SPaolo Bonzini } 126731e17060SPaolo Bonzini }; 126831e17060SPaolo Bonzini 126931e17060SPaolo Bonzini static void xilinx_spips_realize(DeviceState *dev, Error **errp) 127031e17060SPaolo Bonzini { 127131e17060SPaolo Bonzini XilinxSPIPS *s = XILINX_SPIPS(dev); 127231e17060SPaolo Bonzini SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 127310e60b35SPeter Crosthwaite XilinxSPIPSClass *xsc = XILINX_SPIPS_GET_CLASS(s); 127431e17060SPaolo Bonzini int i; 127531e17060SPaolo Bonzini 12764a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "realized spips\n"); 127731e17060SPaolo Bonzini 1278fbe5dac7SFrancisco Iglesias if (s->num_busses > MAX_NUM_BUSSES) { 1279fbe5dac7SFrancisco Iglesias error_setg(errp, 1280fbe5dac7SFrancisco Iglesias "requested number of SPI busses %u exceeds maximum %d", 1281fbe5dac7SFrancisco Iglesias s->num_busses, MAX_NUM_BUSSES); 1282fbe5dac7SFrancisco Iglesias return; 1283fbe5dac7SFrancisco Iglesias } 1284fbe5dac7SFrancisco Iglesias if (s->num_busses < MIN_NUM_BUSSES) { 1285fbe5dac7SFrancisco Iglesias error_setg(errp, 1286fbe5dac7SFrancisco Iglesias "requested number of SPI busses %u is below minimum %d", 1287fbe5dac7SFrancisco Iglesias s->num_busses, MIN_NUM_BUSSES); 1288fbe5dac7SFrancisco Iglesias return; 1289fbe5dac7SFrancisco Iglesias } 1290fbe5dac7SFrancisco Iglesias 129131e17060SPaolo Bonzini s->spi = g_new(SSIBus *, s->num_busses); 129231e17060SPaolo Bonzini for (i = 0; i < s->num_busses; ++i) { 129331e17060SPaolo Bonzini char bus_name[16]; 129431e17060SPaolo Bonzini snprintf(bus_name, 16, "spi%d", i); 129531e17060SPaolo Bonzini s->spi[i] = ssi_create_bus(dev, bus_name); 129631e17060SPaolo Bonzini } 129731e17060SPaolo Bonzini 129831e17060SPaolo Bonzini s->cs_lines = g_new0(qemu_irq, s->num_cs * s->num_busses); 1299ef06ca39SFrancisco Iglesias s->cs_lines_state = g_new0(bool, s->num_cs * s->num_busses); 1300c8cccba3SPaolo Bonzini 130131e17060SPaolo Bonzini sysbus_init_irq(sbd, &s->irq); 130231e17060SPaolo Bonzini for (i = 0; i < s->num_cs * s->num_busses; ++i) { 130331e17060SPaolo Bonzini sysbus_init_irq(sbd, &s->cs_lines[i]); 130431e17060SPaolo Bonzini } 130531e17060SPaolo Bonzini 130629776739SPaolo Bonzini memory_region_init_io(&s->iomem, OBJECT(s), xsc->reg_ops, s, 1307c95997a3SFrancisco Iglesias "spi", XLNX_ZYNQMP_SPIPS_R_MAX * 4); 130831e17060SPaolo Bonzini sysbus_init_mmio(sbd, &s->iomem); 130931e17060SPaolo Bonzini 13106b91f015SPeter Crosthwaite s->irqline = -1; 13116b91f015SPeter Crosthwaite 131210e60b35SPeter Crosthwaite fifo8_create(&s->rx_fifo, xsc->rx_fifo_size); 131310e60b35SPeter Crosthwaite fifo8_create(&s->tx_fifo, xsc->tx_fifo_size); 13146b91f015SPeter Crosthwaite } 13156b91f015SPeter Crosthwaite 13166b91f015SPeter Crosthwaite static void xilinx_qspips_realize(DeviceState *dev, Error **errp) 13176b91f015SPeter Crosthwaite { 13186b91f015SPeter Crosthwaite XilinxSPIPS *s = XILINX_SPIPS(dev); 13196b91f015SPeter Crosthwaite XilinxQSPIPS *q = XILINX_QSPIPS(dev); 13206b91f015SPeter Crosthwaite SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 13216b91f015SPeter Crosthwaite 13224a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "realized qspips\n"); 13236b91f015SPeter Crosthwaite 13246b91f015SPeter Crosthwaite s->num_busses = 2; 13256b91f015SPeter Crosthwaite s->num_cs = 2; 13266b91f015SPeter Crosthwaite s->num_txrx_bytes = 4; 13276b91f015SPeter Crosthwaite 13286b91f015SPeter Crosthwaite xilinx_spips_realize(dev, errp); 132929776739SPaolo Bonzini memory_region_init_io(&s->mmlqspi, OBJECT(s), &lqspi_ops, s, "lqspi", 133031e17060SPaolo Bonzini (1 << LQSPI_ADDRESS_BITS) * 2); 133131e17060SPaolo Bonzini sysbus_init_mmio(sbd, &s->mmlqspi); 133231e17060SPaolo Bonzini 13336b91f015SPeter Crosthwaite q->lqspi_cached_addr = ~0ULL; 133431e17060SPaolo Bonzini } 133531e17060SPaolo Bonzini 1336c95997a3SFrancisco Iglesias static void xlnx_zynqmp_qspips_realize(DeviceState *dev, Error **errp) 1337c95997a3SFrancisco Iglesias { 1338c95997a3SFrancisco Iglesias XlnxZynqMPQSPIPS *s = XLNX_ZYNQMP_QSPIPS(dev); 1339c95997a3SFrancisco Iglesias XilinxSPIPSClass *xsc = XILINX_SPIPS_GET_CLASS(s); 1340c95997a3SFrancisco Iglesias 134121d887cdSSai Pavan Boddu if (s->dma_burst_size > QSPI_DMA_MAX_BURST_SIZE) { 134221d887cdSSai Pavan Boddu error_setg(errp, 134321d887cdSSai Pavan Boddu "qspi dma burst size %u exceeds maximum limit %d", 134421d887cdSSai Pavan Boddu s->dma_burst_size, QSPI_DMA_MAX_BURST_SIZE); 134521d887cdSSai Pavan Boddu return; 134621d887cdSSai Pavan Boddu } 1347c95997a3SFrancisco Iglesias xilinx_qspips_realize(dev, errp); 1348c95997a3SFrancisco Iglesias fifo8_create(&s->rx_fifo_g, xsc->rx_fifo_size); 1349c95997a3SFrancisco Iglesias fifo8_create(&s->tx_fifo_g, xsc->tx_fifo_size); 1350c95997a3SFrancisco Iglesias fifo32_create(&s->fifo_g, 32); 1351c95997a3SFrancisco Iglesias } 1352c95997a3SFrancisco Iglesias 1353c95997a3SFrancisco Iglesias static void xlnx_zynqmp_qspips_init(Object *obj) 1354c95997a3SFrancisco Iglesias { 1355c95997a3SFrancisco Iglesias XlnxZynqMPQSPIPS *rq = XLNX_ZYNQMP_QSPIPS(obj); 1356c95997a3SFrancisco Iglesias 1357*cfbef3f4SPhilippe Mathieu-Daudé object_property_add_link(obj, "stream-connected-dma", TYPE_STREAM_SINK, 1358c95997a3SFrancisco Iglesias (Object **)&rq->dma, 1359c95997a3SFrancisco Iglesias object_property_allow_set_link, 1360d2623129SMarkus Armbruster OBJ_PROP_LINK_STRONG); 1361c95997a3SFrancisco Iglesias } 1362c95997a3SFrancisco Iglesias 136331e17060SPaolo Bonzini static int xilinx_spips_post_load(void *opaque, int version_id) 136431e17060SPaolo Bonzini { 136531e17060SPaolo Bonzini xilinx_spips_update_ixr((XilinxSPIPS *)opaque); 136631e17060SPaolo Bonzini xilinx_spips_update_cs_lines((XilinxSPIPS *)opaque); 136731e17060SPaolo Bonzini return 0; 136831e17060SPaolo Bonzini } 136931e17060SPaolo Bonzini 137031e17060SPaolo Bonzini static const VMStateDescription vmstate_xilinx_spips = { 137131e17060SPaolo Bonzini .name = "xilinx_spips", 137231e17060SPaolo Bonzini .version_id = 2, 137331e17060SPaolo Bonzini .minimum_version_id = 2, 137431e17060SPaolo Bonzini .post_load = xilinx_spips_post_load, 137531e17060SPaolo Bonzini .fields = (VMStateField[]) { 137631e17060SPaolo Bonzini VMSTATE_FIFO8(tx_fifo, XilinxSPIPS), 137731e17060SPaolo Bonzini VMSTATE_FIFO8(rx_fifo, XilinxSPIPS), 13786363235bSAlistair Francis VMSTATE_UINT32_ARRAY(regs, XilinxSPIPS, XLNX_SPIPS_R_MAX), 137931e17060SPaolo Bonzini VMSTATE_UINT8(snoop_state, XilinxSPIPS), 138031e17060SPaolo Bonzini VMSTATE_END_OF_LIST() 138131e17060SPaolo Bonzini } 138231e17060SPaolo Bonzini }; 138331e17060SPaolo Bonzini 1384c95997a3SFrancisco Iglesias static int xlnx_zynqmp_qspips_post_load(void *opaque, int version_id) 1385c95997a3SFrancisco Iglesias { 1386c95997a3SFrancisco Iglesias XlnxZynqMPQSPIPS *s = (XlnxZynqMPQSPIPS *)opaque; 1387c95997a3SFrancisco Iglesias XilinxSPIPS *qs = XILINX_SPIPS(s); 1388c95997a3SFrancisco Iglesias 1389c95997a3SFrancisco Iglesias if (ARRAY_FIELD_EX32(s->regs, GQSPI_SELECT, GENERIC_QSPI_EN) && 1390c95997a3SFrancisco Iglesias fifo8_is_empty(&qs->rx_fifo) && fifo8_is_empty(&qs->tx_fifo)) { 1391c95997a3SFrancisco Iglesias xlnx_zynqmp_qspips_update_ixr(s); 1392c95997a3SFrancisco Iglesias xlnx_zynqmp_qspips_update_cs_lines(s); 1393c95997a3SFrancisco Iglesias } 1394c95997a3SFrancisco Iglesias return 0; 1395c95997a3SFrancisco Iglesias } 1396c95997a3SFrancisco Iglesias 1397c95997a3SFrancisco Iglesias static const VMStateDescription vmstate_xilinx_qspips = { 1398c95997a3SFrancisco Iglesias .name = "xilinx_qspips", 1399c95997a3SFrancisco Iglesias .version_id = 1, 1400c95997a3SFrancisco Iglesias .minimum_version_id = 1, 1401c95997a3SFrancisco Iglesias .fields = (VMStateField[]) { 1402c95997a3SFrancisco Iglesias VMSTATE_STRUCT(parent_obj, XilinxQSPIPS, 0, 1403c95997a3SFrancisco Iglesias vmstate_xilinx_spips, XilinxSPIPS), 1404c95997a3SFrancisco Iglesias VMSTATE_END_OF_LIST() 1405c95997a3SFrancisco Iglesias } 1406c95997a3SFrancisco Iglesias }; 1407c95997a3SFrancisco Iglesias 1408c95997a3SFrancisco Iglesias static const VMStateDescription vmstate_xlnx_zynqmp_qspips = { 1409c95997a3SFrancisco Iglesias .name = "xlnx_zynqmp_qspips", 1410c95997a3SFrancisco Iglesias .version_id = 1, 1411c95997a3SFrancisco Iglesias .minimum_version_id = 1, 1412c95997a3SFrancisco Iglesias .post_load = xlnx_zynqmp_qspips_post_load, 1413c95997a3SFrancisco Iglesias .fields = (VMStateField[]) { 1414c95997a3SFrancisco Iglesias VMSTATE_STRUCT(parent_obj, XlnxZynqMPQSPIPS, 0, 1415c95997a3SFrancisco Iglesias vmstate_xilinx_qspips, XilinxQSPIPS), 1416c95997a3SFrancisco Iglesias VMSTATE_FIFO8(tx_fifo_g, XlnxZynqMPQSPIPS), 1417c95997a3SFrancisco Iglesias VMSTATE_FIFO8(rx_fifo_g, XlnxZynqMPQSPIPS), 1418c95997a3SFrancisco Iglesias VMSTATE_FIFO32(fifo_g, XlnxZynqMPQSPIPS), 1419c95997a3SFrancisco Iglesias VMSTATE_UINT32_ARRAY(regs, XlnxZynqMPQSPIPS, XLNX_ZYNQMP_SPIPS_R_MAX), 1420c95997a3SFrancisco Iglesias VMSTATE_END_OF_LIST() 1421c95997a3SFrancisco Iglesias } 1422c95997a3SFrancisco Iglesias }; 1423c95997a3SFrancisco Iglesias 142421d887cdSSai Pavan Boddu static Property xilinx_zynqmp_qspips_properties[] = { 142521d887cdSSai Pavan Boddu DEFINE_PROP_UINT32("dma-burst-size", XlnxZynqMPQSPIPS, dma_burst_size, 64), 142621d887cdSSai Pavan Boddu DEFINE_PROP_END_OF_LIST(), 142721d887cdSSai Pavan Boddu }; 142821d887cdSSai Pavan Boddu 142931e17060SPaolo Bonzini static Property xilinx_spips_properties[] = { 143031e17060SPaolo Bonzini DEFINE_PROP_UINT8("num-busses", XilinxSPIPS, num_busses, 1), 143131e17060SPaolo Bonzini DEFINE_PROP_UINT8("num-ss-bits", XilinxSPIPS, num_cs, 4), 143231e17060SPaolo Bonzini DEFINE_PROP_UINT8("num-txrx-bytes", XilinxSPIPS, num_txrx_bytes, 1), 143331e17060SPaolo Bonzini DEFINE_PROP_END_OF_LIST(), 143431e17060SPaolo Bonzini }; 14356b91f015SPeter Crosthwaite 14366b91f015SPeter Crosthwaite static void xilinx_qspips_class_init(ObjectClass *klass, void * data) 14376b91f015SPeter Crosthwaite { 14386b91f015SPeter Crosthwaite DeviceClass *dc = DEVICE_CLASS(klass); 143910e60b35SPeter Crosthwaite XilinxSPIPSClass *xsc = XILINX_SPIPS_CLASS(klass); 14406b91f015SPeter Crosthwaite 14416b91f015SPeter Crosthwaite dc->realize = xilinx_qspips_realize; 1442b5cd9143SPeter Crosthwaite xsc->reg_ops = &qspips_ops; 144310e60b35SPeter Crosthwaite xsc->rx_fifo_size = RXFF_A_Q; 144410e60b35SPeter Crosthwaite xsc->tx_fifo_size = TXFF_A_Q; 14456b91f015SPeter Crosthwaite } 14466b91f015SPeter Crosthwaite 144731e17060SPaolo Bonzini static void xilinx_spips_class_init(ObjectClass *klass, void *data) 144831e17060SPaolo Bonzini { 144931e17060SPaolo Bonzini DeviceClass *dc = DEVICE_CLASS(klass); 145010e60b35SPeter Crosthwaite XilinxSPIPSClass *xsc = XILINX_SPIPS_CLASS(klass); 145131e17060SPaolo Bonzini 145231e17060SPaolo Bonzini dc->realize = xilinx_spips_realize; 145331e17060SPaolo Bonzini dc->reset = xilinx_spips_reset; 14544f67d30bSMarc-André Lureau device_class_set_props(dc, xilinx_spips_properties); 145531e17060SPaolo Bonzini dc->vmsd = &vmstate_xilinx_spips; 145610e60b35SPeter Crosthwaite 1457b5cd9143SPeter Crosthwaite xsc->reg_ops = &spips_ops; 145810e60b35SPeter Crosthwaite xsc->rx_fifo_size = RXFF_A; 145910e60b35SPeter Crosthwaite xsc->tx_fifo_size = TXFF_A; 146031e17060SPaolo Bonzini } 146131e17060SPaolo Bonzini 1462c95997a3SFrancisco Iglesias static void xlnx_zynqmp_qspips_class_init(ObjectClass *klass, void * data) 1463c95997a3SFrancisco Iglesias { 1464c95997a3SFrancisco Iglesias DeviceClass *dc = DEVICE_CLASS(klass); 1465c95997a3SFrancisco Iglesias XilinxSPIPSClass *xsc = XILINX_SPIPS_CLASS(klass); 1466c95997a3SFrancisco Iglesias 1467c95997a3SFrancisco Iglesias dc->realize = xlnx_zynqmp_qspips_realize; 1468c95997a3SFrancisco Iglesias dc->reset = xlnx_zynqmp_qspips_reset; 1469c95997a3SFrancisco Iglesias dc->vmsd = &vmstate_xlnx_zynqmp_qspips; 14704f67d30bSMarc-André Lureau device_class_set_props(dc, xilinx_zynqmp_qspips_properties); 1471c95997a3SFrancisco Iglesias xsc->reg_ops = &xlnx_zynqmp_qspips_ops; 1472c95997a3SFrancisco Iglesias xsc->rx_fifo_size = RXFF_A_Q; 1473c95997a3SFrancisco Iglesias xsc->tx_fifo_size = TXFF_A_Q; 1474c95997a3SFrancisco Iglesias } 1475c95997a3SFrancisco Iglesias 147631e17060SPaolo Bonzini static const TypeInfo xilinx_spips_info = { 147731e17060SPaolo Bonzini .name = TYPE_XILINX_SPIPS, 147831e17060SPaolo Bonzini .parent = TYPE_SYS_BUS_DEVICE, 147931e17060SPaolo Bonzini .instance_size = sizeof(XilinxSPIPS), 148031e17060SPaolo Bonzini .class_init = xilinx_spips_class_init, 148110e60b35SPeter Crosthwaite .class_size = sizeof(XilinxSPIPSClass), 148231e17060SPaolo Bonzini }; 148331e17060SPaolo Bonzini 14846b91f015SPeter Crosthwaite static const TypeInfo xilinx_qspips_info = { 14856b91f015SPeter Crosthwaite .name = TYPE_XILINX_QSPIPS, 14866b91f015SPeter Crosthwaite .parent = TYPE_XILINX_SPIPS, 14876b91f015SPeter Crosthwaite .instance_size = sizeof(XilinxQSPIPS), 14886b91f015SPeter Crosthwaite .class_init = xilinx_qspips_class_init, 14896b91f015SPeter Crosthwaite }; 14906b91f015SPeter Crosthwaite 1491c95997a3SFrancisco Iglesias static const TypeInfo xlnx_zynqmp_qspips_info = { 1492c95997a3SFrancisco Iglesias .name = TYPE_XLNX_ZYNQMP_QSPIPS, 1493c95997a3SFrancisco Iglesias .parent = TYPE_XILINX_QSPIPS, 1494c95997a3SFrancisco Iglesias .instance_size = sizeof(XlnxZynqMPQSPIPS), 1495c95997a3SFrancisco Iglesias .instance_init = xlnx_zynqmp_qspips_init, 1496c95997a3SFrancisco Iglesias .class_init = xlnx_zynqmp_qspips_class_init, 1497c95997a3SFrancisco Iglesias }; 1498c95997a3SFrancisco Iglesias 149931e17060SPaolo Bonzini static void xilinx_spips_register_types(void) 150031e17060SPaolo Bonzini { 150131e17060SPaolo Bonzini type_register_static(&xilinx_spips_info); 15026b91f015SPeter Crosthwaite type_register_static(&xilinx_qspips_info); 1503c95997a3SFrancisco Iglesias type_register_static(&xlnx_zynqmp_qspips_info); 150431e17060SPaolo Bonzini } 150531e17060SPaolo Bonzini 150631e17060SPaolo Bonzini type_init(xilinx_spips_register_types) 1507