xref: /openbmc/qemu/hw/ssi/xilinx_spips.c (revision c4f08ffe)
131e17060SPaolo Bonzini /*
231e17060SPaolo Bonzini  * QEMU model of the Xilinx Zynq SPI controller
331e17060SPaolo Bonzini  *
431e17060SPaolo Bonzini  * Copyright (c) 2012 Peter A. G. Crosthwaite
531e17060SPaolo Bonzini  *
631e17060SPaolo Bonzini  * Permission is hereby granted, free of charge, to any person obtaining a copy
731e17060SPaolo Bonzini  * of this software and associated documentation files (the "Software"), to deal
831e17060SPaolo Bonzini  * in the Software without restriction, including without limitation the rights
931e17060SPaolo Bonzini  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
1031e17060SPaolo Bonzini  * copies of the Software, and to permit persons to whom the Software is
1131e17060SPaolo Bonzini  * furnished to do so, subject to the following conditions:
1231e17060SPaolo Bonzini  *
1331e17060SPaolo Bonzini  * The above copyright notice and this permission notice shall be included in
1431e17060SPaolo Bonzini  * all copies or substantial portions of the Software.
1531e17060SPaolo Bonzini  *
1631e17060SPaolo Bonzini  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
1731e17060SPaolo Bonzini  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
1831e17060SPaolo Bonzini  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
1931e17060SPaolo Bonzini  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
2031e17060SPaolo Bonzini  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
2131e17060SPaolo Bonzini  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
2231e17060SPaolo Bonzini  * THE SOFTWARE.
2331e17060SPaolo Bonzini  */
2431e17060SPaolo Bonzini 
2531e17060SPaolo Bonzini #include "hw/sysbus.h"
2631e17060SPaolo Bonzini #include "sysemu/sysemu.h"
2731e17060SPaolo Bonzini #include "hw/ptimer.h"
2831e17060SPaolo Bonzini #include "qemu/log.h"
2931e17060SPaolo Bonzini #include "qemu/fifo8.h"
3031e17060SPaolo Bonzini #include "hw/ssi.h"
3131e17060SPaolo Bonzini #include "qemu/bitops.h"
3231e17060SPaolo Bonzini 
3331e17060SPaolo Bonzini #ifdef XILINX_SPIPS_ERR_DEBUG
3431e17060SPaolo Bonzini #define DB_PRINT(...) do { \
3531e17060SPaolo Bonzini     fprintf(stderr,  ": %s: ", __func__); \
3631e17060SPaolo Bonzini     fprintf(stderr, ## __VA_ARGS__); \
3731e17060SPaolo Bonzini     } while (0);
3831e17060SPaolo Bonzini #else
3931e17060SPaolo Bonzini     #define DB_PRINT(...)
4031e17060SPaolo Bonzini #endif
4131e17060SPaolo Bonzini 
4231e17060SPaolo Bonzini /* config register */
4331e17060SPaolo Bonzini #define R_CONFIG            (0x00 / 4)
4431e17060SPaolo Bonzini #define IFMODE              (1 << 31)
4531e17060SPaolo Bonzini #define ENDIAN              (1 << 26)
4631e17060SPaolo Bonzini #define MODEFAIL_GEN_EN     (1 << 17)
4731e17060SPaolo Bonzini #define MAN_START_COM       (1 << 16)
4831e17060SPaolo Bonzini #define MAN_START_EN        (1 << 15)
4931e17060SPaolo Bonzini #define MANUAL_CS           (1 << 14)
5031e17060SPaolo Bonzini #define CS                  (0xF << 10)
5131e17060SPaolo Bonzini #define CS_SHIFT            (10)
5231e17060SPaolo Bonzini #define PERI_SEL            (1 << 9)
5331e17060SPaolo Bonzini #define REF_CLK             (1 << 8)
5431e17060SPaolo Bonzini #define FIFO_WIDTH          (3 << 6)
5531e17060SPaolo Bonzini #define BAUD_RATE_DIV       (7 << 3)
5631e17060SPaolo Bonzini #define CLK_PH              (1 << 2)
5731e17060SPaolo Bonzini #define CLK_POL             (1 << 1)
5831e17060SPaolo Bonzini #define MODE_SEL            (1 << 0)
5931e17060SPaolo Bonzini 
6031e17060SPaolo Bonzini /* interrupt mechanism */
6131e17060SPaolo Bonzini #define R_INTR_STATUS       (0x04 / 4)
6231e17060SPaolo Bonzini #define R_INTR_EN           (0x08 / 4)
6331e17060SPaolo Bonzini #define R_INTR_DIS          (0x0C / 4)
6431e17060SPaolo Bonzini #define R_INTR_MASK         (0x10 / 4)
6531e17060SPaolo Bonzini #define IXR_TX_FIFO_UNDERFLOW   (1 << 6)
6631e17060SPaolo Bonzini #define IXR_RX_FIFO_FULL        (1 << 5)
6731e17060SPaolo Bonzini #define IXR_RX_FIFO_NOT_EMPTY   (1 << 4)
6831e17060SPaolo Bonzini #define IXR_TX_FIFO_FULL        (1 << 3)
6931e17060SPaolo Bonzini #define IXR_TX_FIFO_NOT_FULL    (1 << 2)
7031e17060SPaolo Bonzini #define IXR_TX_FIFO_MODE_FAIL   (1 << 1)
7131e17060SPaolo Bonzini #define IXR_RX_FIFO_OVERFLOW    (1 << 0)
7231e17060SPaolo Bonzini #define IXR_ALL                 ((IXR_TX_FIFO_UNDERFLOW<<1)-1)
7331e17060SPaolo Bonzini 
7431e17060SPaolo Bonzini #define R_EN                (0x14 / 4)
7531e17060SPaolo Bonzini #define R_DELAY             (0x18 / 4)
7631e17060SPaolo Bonzini #define R_TX_DATA           (0x1C / 4)
7731e17060SPaolo Bonzini #define R_RX_DATA           (0x20 / 4)
7831e17060SPaolo Bonzini #define R_SLAVE_IDLE_COUNT  (0x24 / 4)
7931e17060SPaolo Bonzini #define R_TX_THRES          (0x28 / 4)
8031e17060SPaolo Bonzini #define R_RX_THRES          (0x2C / 4)
8131e17060SPaolo Bonzini #define R_TXD1              (0x80 / 4)
8231e17060SPaolo Bonzini #define R_TXD2              (0x84 / 4)
8331e17060SPaolo Bonzini #define R_TXD3              (0x88 / 4)
8431e17060SPaolo Bonzini 
8531e17060SPaolo Bonzini #define R_LQSPI_CFG         (0xa0 / 4)
8631e17060SPaolo Bonzini #define R_LQSPI_CFG_RESET       0x03A002EB
8731e17060SPaolo Bonzini #define LQSPI_CFG_LQ_MODE       (1 << 31)
8831e17060SPaolo Bonzini #define LQSPI_CFG_TWO_MEM       (1 << 30)
8931e17060SPaolo Bonzini #define LQSPI_CFG_SEP_BUS       (1 << 30)
9031e17060SPaolo Bonzini #define LQSPI_CFG_U_PAGE        (1 << 28)
9131e17060SPaolo Bonzini #define LQSPI_CFG_MODE_EN       (1 << 25)
9231e17060SPaolo Bonzini #define LQSPI_CFG_MODE_WIDTH    8
9331e17060SPaolo Bonzini #define LQSPI_CFG_MODE_SHIFT    16
9431e17060SPaolo Bonzini #define LQSPI_CFG_DUMMY_WIDTH   3
9531e17060SPaolo Bonzini #define LQSPI_CFG_DUMMY_SHIFT   8
9631e17060SPaolo Bonzini #define LQSPI_CFG_INST_CODE     0xFF
9731e17060SPaolo Bonzini 
9831e17060SPaolo Bonzini #define R_LQSPI_STS         (0xA4 / 4)
9931e17060SPaolo Bonzini #define LQSPI_STS_WR_RECVD      (1 << 1)
10031e17060SPaolo Bonzini 
10131e17060SPaolo Bonzini #define R_MOD_ID            (0xFC / 4)
10231e17060SPaolo Bonzini 
10331e17060SPaolo Bonzini #define R_MAX (R_MOD_ID+1)
10431e17060SPaolo Bonzini 
10531e17060SPaolo Bonzini /* size of TXRX FIFOs */
10631e17060SPaolo Bonzini #define RXFF_A          32
10731e17060SPaolo Bonzini #define TXFF_A          32
10831e17060SPaolo Bonzini 
10910e60b35SPeter Crosthwaite #define RXFF_A_Q          (64 * 4)
11010e60b35SPeter Crosthwaite #define TXFF_A_Q          (64 * 4)
11110e60b35SPeter Crosthwaite 
11231e17060SPaolo Bonzini /* 16MB per linear region */
11331e17060SPaolo Bonzini #define LQSPI_ADDRESS_BITS 24
11431e17060SPaolo Bonzini /* Bite off 4k chunks at a time */
11531e17060SPaolo Bonzini #define LQSPI_CACHE_SIZE 1024
11631e17060SPaolo Bonzini 
11731e17060SPaolo Bonzini #define SNOOP_CHECKING 0xFF
11831e17060SPaolo Bonzini #define SNOOP_NONE 0xFE
11931e17060SPaolo Bonzini #define SNOOP_STRIPING 0
12031e17060SPaolo Bonzini 
12131e17060SPaolo Bonzini typedef enum {
12231e17060SPaolo Bonzini     READ = 0x3,
12331e17060SPaolo Bonzini     FAST_READ = 0xb,
12431e17060SPaolo Bonzini     DOR = 0x3b,
12531e17060SPaolo Bonzini     QOR = 0x6b,
12631e17060SPaolo Bonzini     DIOR = 0xbb,
12731e17060SPaolo Bonzini     QIOR = 0xeb,
12831e17060SPaolo Bonzini 
12931e17060SPaolo Bonzini     PP = 0x2,
13031e17060SPaolo Bonzini     DPP = 0xa2,
13131e17060SPaolo Bonzini     QPP = 0x32,
13231e17060SPaolo Bonzini } FlashCMD;
13331e17060SPaolo Bonzini 
13431e17060SPaolo Bonzini typedef struct {
1356b91f015SPeter Crosthwaite     SysBusDevice parent_obj;
1366b91f015SPeter Crosthwaite 
13731e17060SPaolo Bonzini     MemoryRegion iomem;
13831e17060SPaolo Bonzini     MemoryRegion mmlqspi;
13931e17060SPaolo Bonzini 
14031e17060SPaolo Bonzini     qemu_irq irq;
14131e17060SPaolo Bonzini     int irqline;
14231e17060SPaolo Bonzini 
14331e17060SPaolo Bonzini     uint8_t num_cs;
14431e17060SPaolo Bonzini     uint8_t num_busses;
14531e17060SPaolo Bonzini 
14631e17060SPaolo Bonzini     uint8_t snoop_state;
14731e17060SPaolo Bonzini     qemu_irq *cs_lines;
14831e17060SPaolo Bonzini     SSIBus **spi;
14931e17060SPaolo Bonzini 
15031e17060SPaolo Bonzini     Fifo8 rx_fifo;
15131e17060SPaolo Bonzini     Fifo8 tx_fifo;
15231e17060SPaolo Bonzini 
15331e17060SPaolo Bonzini     uint8_t num_txrx_bytes;
15431e17060SPaolo Bonzini 
15531e17060SPaolo Bonzini     uint32_t regs[R_MAX];
1566b91f015SPeter Crosthwaite } XilinxSPIPS;
1576b91f015SPeter Crosthwaite 
1586b91f015SPeter Crosthwaite typedef struct {
1596b91f015SPeter Crosthwaite     XilinxSPIPS parent_obj;
16031e17060SPaolo Bonzini 
16131e17060SPaolo Bonzini     uint32_t lqspi_buf[LQSPI_CACHE_SIZE];
16231e17060SPaolo Bonzini     hwaddr lqspi_cached_addr;
1636b91f015SPeter Crosthwaite } XilinxQSPIPS;
16431e17060SPaolo Bonzini 
16510e60b35SPeter Crosthwaite typedef struct XilinxSPIPSClass {
16610e60b35SPeter Crosthwaite     SysBusDeviceClass parent_class;
16710e60b35SPeter Crosthwaite 
168b5cd9143SPeter Crosthwaite     const MemoryRegionOps *reg_ops;
169b5cd9143SPeter Crosthwaite 
17010e60b35SPeter Crosthwaite     uint32_t rx_fifo_size;
17110e60b35SPeter Crosthwaite     uint32_t tx_fifo_size;
17210e60b35SPeter Crosthwaite } XilinxSPIPSClass;
1736b91f015SPeter Crosthwaite 
1746b91f015SPeter Crosthwaite #define TYPE_XILINX_SPIPS "xlnx.ps7-spi"
1756b91f015SPeter Crosthwaite #define TYPE_XILINX_QSPIPS "xlnx.ps7-qspi"
17631e17060SPaolo Bonzini 
17731e17060SPaolo Bonzini #define XILINX_SPIPS(obj) \
17831e17060SPaolo Bonzini      OBJECT_CHECK(XilinxSPIPS, (obj), TYPE_XILINX_SPIPS)
17910e60b35SPeter Crosthwaite #define XILINX_SPIPS_CLASS(klass) \
18010e60b35SPeter Crosthwaite      OBJECT_CLASS_CHECK(XilinxSPIPSClass, (klass), TYPE_XILINX_SPIPS)
18110e60b35SPeter Crosthwaite #define XILINX_SPIPS_GET_CLASS(obj) \
18210e60b35SPeter Crosthwaite      OBJECT_GET_CLASS(XilinxSPIPSClass, (obj), TYPE_XILINX_SPIPS)
18310e60b35SPeter Crosthwaite 
1846b91f015SPeter Crosthwaite #define XILINX_QSPIPS(obj) \
1856b91f015SPeter Crosthwaite      OBJECT_CHECK(XilinxQSPIPS, (obj), TYPE_XILINX_QSPIPS)
18631e17060SPaolo Bonzini 
18731e17060SPaolo Bonzini static inline int num_effective_busses(XilinxSPIPS *s)
18831e17060SPaolo Bonzini {
18931e17060SPaolo Bonzini     return (s->regs[R_LQSPI_CFG] & LQSPI_CFG_SEP_BUS &&
19031e17060SPaolo Bonzini             s->regs[R_LQSPI_CFG] & LQSPI_CFG_TWO_MEM) ? s->num_busses : 1;
19131e17060SPaolo Bonzini }
19231e17060SPaolo Bonzini 
193*c4f08ffeSPeter Crosthwaite static inline bool xilinx_spips_cs_is_set(XilinxSPIPS *s, int i, int field)
194*c4f08ffeSPeter Crosthwaite {
195*c4f08ffeSPeter Crosthwaite     return ~field & (1 << i) && (s->regs[R_CONFIG] & MANUAL_CS
196*c4f08ffeSPeter Crosthwaite                     || !fifo8_is_empty(&s->tx_fifo));
197*c4f08ffeSPeter Crosthwaite }
198*c4f08ffeSPeter Crosthwaite 
19931e17060SPaolo Bonzini static void xilinx_spips_update_cs_lines(XilinxSPIPS *s)
20031e17060SPaolo Bonzini {
20131e17060SPaolo Bonzini     int i, j;
20231e17060SPaolo Bonzini     bool found = false;
20331e17060SPaolo Bonzini     int field = s->regs[R_CONFIG] >> CS_SHIFT;
20431e17060SPaolo Bonzini 
20531e17060SPaolo Bonzini     for (i = 0; i < s->num_cs; i++) {
20631e17060SPaolo Bonzini         for (j = 0; j < num_effective_busses(s); j++) {
20731e17060SPaolo Bonzini             int upage = !!(s->regs[R_LQSPI_STS] & LQSPI_CFG_U_PAGE);
20831e17060SPaolo Bonzini             int cs_to_set = (j * s->num_cs + i + upage) %
20931e17060SPaolo Bonzini                                 (s->num_cs * s->num_busses);
21031e17060SPaolo Bonzini 
211*c4f08ffeSPeter Crosthwaite             if (xilinx_spips_cs_is_set(s, i, field) && !found) {
21231e17060SPaolo Bonzini                 DB_PRINT("selecting slave %d\n", i);
21331e17060SPaolo Bonzini                 qemu_set_irq(s->cs_lines[cs_to_set], 0);
21431e17060SPaolo Bonzini             } else {
215*c4f08ffeSPeter Crosthwaite                 DB_PRINT("deselecting slave %d\n", i);
21631e17060SPaolo Bonzini                 qemu_set_irq(s->cs_lines[cs_to_set], 1);
21731e17060SPaolo Bonzini             }
21831e17060SPaolo Bonzini         }
219*c4f08ffeSPeter Crosthwaite         if (xilinx_spips_cs_is_set(s, i, field)) {
22031e17060SPaolo Bonzini             found = true;
22131e17060SPaolo Bonzini         }
22231e17060SPaolo Bonzini     }
22331e17060SPaolo Bonzini     if (!found) {
22431e17060SPaolo Bonzini         s->snoop_state = SNOOP_CHECKING;
22531e17060SPaolo Bonzini     }
22631e17060SPaolo Bonzini }
22731e17060SPaolo Bonzini 
22831e17060SPaolo Bonzini static void xilinx_spips_update_ixr(XilinxSPIPS *s)
22931e17060SPaolo Bonzini {
2303ea728d0SPeter Crosthwaite     if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_LQ_MODE) {
2313ea728d0SPeter Crosthwaite         return;
2323ea728d0SPeter Crosthwaite     }
23331e17060SPaolo Bonzini     /* These are set/cleared as they occur */
23431e17060SPaolo Bonzini     s->regs[R_INTR_STATUS] &= (IXR_TX_FIFO_UNDERFLOW | IXR_RX_FIFO_OVERFLOW |
23531e17060SPaolo Bonzini                                 IXR_TX_FIFO_MODE_FAIL);
23631e17060SPaolo Bonzini     /* these are pure functions of fifo state, set them here */
23731e17060SPaolo Bonzini     s->regs[R_INTR_STATUS] |=
23831e17060SPaolo Bonzini         (fifo8_is_full(&s->rx_fifo) ? IXR_RX_FIFO_FULL : 0) |
23931e17060SPaolo Bonzini         (s->rx_fifo.num >= s->regs[R_RX_THRES] ? IXR_RX_FIFO_NOT_EMPTY : 0) |
24031e17060SPaolo Bonzini         (fifo8_is_full(&s->tx_fifo) ? IXR_TX_FIFO_FULL : 0) |
24131e17060SPaolo Bonzini         (s->tx_fifo.num < s->regs[R_TX_THRES] ? IXR_TX_FIFO_NOT_FULL : 0);
24231e17060SPaolo Bonzini     /* drive external interrupt pin */
24331e17060SPaolo Bonzini     int new_irqline = !!(s->regs[R_INTR_MASK] & s->regs[R_INTR_STATUS] &
24431e17060SPaolo Bonzini                                                                 IXR_ALL);
24531e17060SPaolo Bonzini     if (new_irqline != s->irqline) {
24631e17060SPaolo Bonzini         s->irqline = new_irqline;
24731e17060SPaolo Bonzini         qemu_set_irq(s->irq, s->irqline);
24831e17060SPaolo Bonzini     }
24931e17060SPaolo Bonzini }
25031e17060SPaolo Bonzini 
25131e17060SPaolo Bonzini static void xilinx_spips_reset(DeviceState *d)
25231e17060SPaolo Bonzini {
25331e17060SPaolo Bonzini     XilinxSPIPS *s = XILINX_SPIPS(d);
25431e17060SPaolo Bonzini 
25531e17060SPaolo Bonzini     int i;
25631e17060SPaolo Bonzini     for (i = 0; i < R_MAX; i++) {
25731e17060SPaolo Bonzini         s->regs[i] = 0;
25831e17060SPaolo Bonzini     }
25931e17060SPaolo Bonzini 
26031e17060SPaolo Bonzini     fifo8_reset(&s->rx_fifo);
26131e17060SPaolo Bonzini     fifo8_reset(&s->rx_fifo);
26231e17060SPaolo Bonzini     /* non zero resets */
26331e17060SPaolo Bonzini     s->regs[R_CONFIG] |= MODEFAIL_GEN_EN;
26431e17060SPaolo Bonzini     s->regs[R_SLAVE_IDLE_COUNT] = 0xFF;
26531e17060SPaolo Bonzini     s->regs[R_TX_THRES] = 1;
26631e17060SPaolo Bonzini     s->regs[R_RX_THRES] = 1;
26731e17060SPaolo Bonzini     /* FIXME: move magic number definition somewhere sensible */
26831e17060SPaolo Bonzini     s->regs[R_MOD_ID] = 0x01090106;
26931e17060SPaolo Bonzini     s->regs[R_LQSPI_CFG] = R_LQSPI_CFG_RESET;
27031e17060SPaolo Bonzini     s->snoop_state = SNOOP_CHECKING;
27131e17060SPaolo Bonzini     xilinx_spips_update_ixr(s);
27231e17060SPaolo Bonzini     xilinx_spips_update_cs_lines(s);
27331e17060SPaolo Bonzini }
27431e17060SPaolo Bonzini 
27531e17060SPaolo Bonzini static void xilinx_spips_flush_txfifo(XilinxSPIPS *s)
27631e17060SPaolo Bonzini {
27731e17060SPaolo Bonzini     for (;;) {
27831e17060SPaolo Bonzini         int i;
27931e17060SPaolo Bonzini         uint8_t rx;
28031e17060SPaolo Bonzini         uint8_t tx = 0;
28131e17060SPaolo Bonzini 
28231e17060SPaolo Bonzini         for (i = 0; i < num_effective_busses(s); ++i) {
28331e17060SPaolo Bonzini             if (!i || s->snoop_state == SNOOP_STRIPING) {
28431e17060SPaolo Bonzini                 if (fifo8_is_empty(&s->tx_fifo)) {
2853ea728d0SPeter Crosthwaite                     if (!(s->regs[R_LQSPI_CFG] & LQSPI_CFG_LQ_MODE)) {
28631e17060SPaolo Bonzini                         s->regs[R_INTR_STATUS] |= IXR_TX_FIFO_UNDERFLOW;
2873ea728d0SPeter Crosthwaite                     }
28831e17060SPaolo Bonzini                     xilinx_spips_update_ixr(s);
28931e17060SPaolo Bonzini                     return;
29031e17060SPaolo Bonzini                 } else {
29131e17060SPaolo Bonzini                     tx = fifo8_pop(&s->tx_fifo);
29231e17060SPaolo Bonzini                 }
29331e17060SPaolo Bonzini             }
29431e17060SPaolo Bonzini             rx = ssi_transfer(s->spi[i], (uint32_t)tx);
29531e17060SPaolo Bonzini             DB_PRINT("tx = %02x rx = %02x\n", tx, rx);
29631e17060SPaolo Bonzini             if (!i || s->snoop_state == SNOOP_STRIPING) {
29731e17060SPaolo Bonzini                 if (fifo8_is_full(&s->rx_fifo)) {
29831e17060SPaolo Bonzini                     s->regs[R_INTR_STATUS] |= IXR_RX_FIFO_OVERFLOW;
29931e17060SPaolo Bonzini                     DB_PRINT("rx FIFO overflow");
30031e17060SPaolo Bonzini                 } else {
30131e17060SPaolo Bonzini                     fifo8_push(&s->rx_fifo, (uint8_t)rx);
30231e17060SPaolo Bonzini                 }
30331e17060SPaolo Bonzini             }
30431e17060SPaolo Bonzini         }
30531e17060SPaolo Bonzini 
30631e17060SPaolo Bonzini         switch (s->snoop_state) {
30731e17060SPaolo Bonzini         case (SNOOP_CHECKING):
30831e17060SPaolo Bonzini             switch (tx) { /* new instruction code */
30931e17060SPaolo Bonzini             case READ: /* 3 address bytes, no dummy bytes/cycles */
31031e17060SPaolo Bonzini             case PP:
31131e17060SPaolo Bonzini             case DPP:
31231e17060SPaolo Bonzini             case QPP:
31331e17060SPaolo Bonzini                 s->snoop_state = 3;
31431e17060SPaolo Bonzini                 break;
31531e17060SPaolo Bonzini             case FAST_READ: /* 3 address bytes, 1 dummy byte */
31631e17060SPaolo Bonzini             case DOR:
31731e17060SPaolo Bonzini             case QOR:
31831e17060SPaolo Bonzini             case DIOR: /* FIXME: these vary between vendor - set to spansion */
31931e17060SPaolo Bonzini                 s->snoop_state = 4;
32031e17060SPaolo Bonzini                 break;
32131e17060SPaolo Bonzini             case QIOR: /* 3 address bytes, 2 dummy bytes */
32231e17060SPaolo Bonzini                 s->snoop_state = 6;
32331e17060SPaolo Bonzini                 break;
32431e17060SPaolo Bonzini             default:
32531e17060SPaolo Bonzini                 s->snoop_state = SNOOP_NONE;
32631e17060SPaolo Bonzini             }
32731e17060SPaolo Bonzini             break;
32831e17060SPaolo Bonzini         case (SNOOP_STRIPING):
32931e17060SPaolo Bonzini         case (SNOOP_NONE):
33031e17060SPaolo Bonzini             break;
33131e17060SPaolo Bonzini         default:
33231e17060SPaolo Bonzini             s->snoop_state--;
33331e17060SPaolo Bonzini         }
33431e17060SPaolo Bonzini     }
33531e17060SPaolo Bonzini }
33631e17060SPaolo Bonzini 
33731e17060SPaolo Bonzini static inline void rx_data_bytes(XilinxSPIPS *s, uint32_t *value, int max)
33831e17060SPaolo Bonzini {
33931e17060SPaolo Bonzini     int i;
34031e17060SPaolo Bonzini 
34131e17060SPaolo Bonzini     *value = 0;
34231e17060SPaolo Bonzini     for (i = 0; i < max && !fifo8_is_empty(&s->rx_fifo); ++i) {
34331e17060SPaolo Bonzini         uint32_t next = fifo8_pop(&s->rx_fifo) & 0xFF;
34431e17060SPaolo Bonzini         *value |= next << 8 * (s->regs[R_CONFIG] & ENDIAN ? 3-i : i);
34531e17060SPaolo Bonzini     }
34631e17060SPaolo Bonzini }
34731e17060SPaolo Bonzini 
34831e17060SPaolo Bonzini static uint64_t xilinx_spips_read(void *opaque, hwaddr addr,
34931e17060SPaolo Bonzini                                                         unsigned size)
35031e17060SPaolo Bonzini {
35131e17060SPaolo Bonzini     XilinxSPIPS *s = opaque;
35231e17060SPaolo Bonzini     uint32_t mask = ~0;
35331e17060SPaolo Bonzini     uint32_t ret;
35431e17060SPaolo Bonzini 
35531e17060SPaolo Bonzini     addr >>= 2;
35631e17060SPaolo Bonzini     switch (addr) {
35731e17060SPaolo Bonzini     case R_CONFIG:
35831e17060SPaolo Bonzini         mask = 0x0002FFFF;
35931e17060SPaolo Bonzini         break;
36031e17060SPaolo Bonzini     case R_INTR_STATUS:
36187920b44SPeter Crosthwaite         ret = s->regs[addr] & IXR_ALL;
36287920b44SPeter Crosthwaite         s->regs[addr] = 0;
36387920b44SPeter Crosthwaite         DB_PRINT("addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret);
36487920b44SPeter Crosthwaite         return ret;
36531e17060SPaolo Bonzini     case R_INTR_MASK:
36631e17060SPaolo Bonzini         mask = IXR_ALL;
36731e17060SPaolo Bonzini         break;
36831e17060SPaolo Bonzini     case  R_EN:
36931e17060SPaolo Bonzini         mask = 0x1;
37031e17060SPaolo Bonzini         break;
37131e17060SPaolo Bonzini     case R_SLAVE_IDLE_COUNT:
37231e17060SPaolo Bonzini         mask = 0xFF;
37331e17060SPaolo Bonzini         break;
37431e17060SPaolo Bonzini     case R_MOD_ID:
37531e17060SPaolo Bonzini         mask = 0x01FFFFFF;
37631e17060SPaolo Bonzini         break;
37731e17060SPaolo Bonzini     case R_INTR_EN:
37831e17060SPaolo Bonzini     case R_INTR_DIS:
37931e17060SPaolo Bonzini     case R_TX_DATA:
38031e17060SPaolo Bonzini         mask = 0;
38131e17060SPaolo Bonzini         break;
38231e17060SPaolo Bonzini     case R_RX_DATA:
38331e17060SPaolo Bonzini         rx_data_bytes(s, &ret, s->num_txrx_bytes);
38431e17060SPaolo Bonzini         DB_PRINT("addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret);
38531e17060SPaolo Bonzini         xilinx_spips_update_ixr(s);
38631e17060SPaolo Bonzini         return ret;
38731e17060SPaolo Bonzini     }
38831e17060SPaolo Bonzini     DB_PRINT("addr=" TARGET_FMT_plx " = %x\n", addr * 4, s->regs[addr] & mask);
38931e17060SPaolo Bonzini     return s->regs[addr] & mask;
39031e17060SPaolo Bonzini 
39131e17060SPaolo Bonzini }
39231e17060SPaolo Bonzini 
39331e17060SPaolo Bonzini static inline void tx_data_bytes(XilinxSPIPS *s, uint32_t value, int num)
39431e17060SPaolo Bonzini {
39531e17060SPaolo Bonzini     int i;
39631e17060SPaolo Bonzini     for (i = 0; i < num && !fifo8_is_full(&s->tx_fifo); ++i) {
39731e17060SPaolo Bonzini         if (s->regs[R_CONFIG] & ENDIAN) {
39831e17060SPaolo Bonzini             fifo8_push(&s->tx_fifo, (uint8_t)(value >> 24));
39931e17060SPaolo Bonzini             value <<= 8;
40031e17060SPaolo Bonzini         } else {
40131e17060SPaolo Bonzini             fifo8_push(&s->tx_fifo, (uint8_t)value);
40231e17060SPaolo Bonzini             value >>= 8;
40331e17060SPaolo Bonzini         }
40431e17060SPaolo Bonzini     }
40531e17060SPaolo Bonzini }
40631e17060SPaolo Bonzini 
40731e17060SPaolo Bonzini static void xilinx_spips_write(void *opaque, hwaddr addr,
40831e17060SPaolo Bonzini                                         uint64_t value, unsigned size)
40931e17060SPaolo Bonzini {
41031e17060SPaolo Bonzini     int mask = ~0;
41131e17060SPaolo Bonzini     int man_start_com = 0;
41231e17060SPaolo Bonzini     XilinxSPIPS *s = opaque;
41331e17060SPaolo Bonzini 
41431e17060SPaolo Bonzini     DB_PRINT("addr=" TARGET_FMT_plx " = %x\n", addr, (unsigned)value);
41531e17060SPaolo Bonzini     addr >>= 2;
41631e17060SPaolo Bonzini     switch (addr) {
41731e17060SPaolo Bonzini     case R_CONFIG:
41831e17060SPaolo Bonzini         mask = 0x0002FFFF;
41931e17060SPaolo Bonzini         if (value & MAN_START_COM) {
42031e17060SPaolo Bonzini             man_start_com = 1;
42131e17060SPaolo Bonzini         }
42231e17060SPaolo Bonzini         break;
42331e17060SPaolo Bonzini     case R_INTR_STATUS:
42431e17060SPaolo Bonzini         mask = IXR_ALL;
42531e17060SPaolo Bonzini         s->regs[R_INTR_STATUS] &= ~(mask & value);
42631e17060SPaolo Bonzini         goto no_reg_update;
42731e17060SPaolo Bonzini     case R_INTR_DIS:
42831e17060SPaolo Bonzini         mask = IXR_ALL;
42931e17060SPaolo Bonzini         s->regs[R_INTR_MASK] &= ~(mask & value);
43031e17060SPaolo Bonzini         goto no_reg_update;
43131e17060SPaolo Bonzini     case R_INTR_EN:
43231e17060SPaolo Bonzini         mask = IXR_ALL;
43331e17060SPaolo Bonzini         s->regs[R_INTR_MASK] |= mask & value;
43431e17060SPaolo Bonzini         goto no_reg_update;
43531e17060SPaolo Bonzini     case R_EN:
43631e17060SPaolo Bonzini         mask = 0x1;
43731e17060SPaolo Bonzini         break;
43831e17060SPaolo Bonzini     case R_SLAVE_IDLE_COUNT:
43931e17060SPaolo Bonzini         mask = 0xFF;
44031e17060SPaolo Bonzini         break;
44131e17060SPaolo Bonzini     case R_RX_DATA:
44231e17060SPaolo Bonzini     case R_INTR_MASK:
44331e17060SPaolo Bonzini     case R_MOD_ID:
44431e17060SPaolo Bonzini         mask = 0;
44531e17060SPaolo Bonzini         break;
44631e17060SPaolo Bonzini     case R_TX_DATA:
44731e17060SPaolo Bonzini         tx_data_bytes(s, (uint32_t)value, s->num_txrx_bytes);
44831e17060SPaolo Bonzini         goto no_reg_update;
44931e17060SPaolo Bonzini     case R_TXD1:
45031e17060SPaolo Bonzini         tx_data_bytes(s, (uint32_t)value, 1);
45131e17060SPaolo Bonzini         goto no_reg_update;
45231e17060SPaolo Bonzini     case R_TXD2:
45331e17060SPaolo Bonzini         tx_data_bytes(s, (uint32_t)value, 2);
45431e17060SPaolo Bonzini         goto no_reg_update;
45531e17060SPaolo Bonzini     case R_TXD3:
45631e17060SPaolo Bonzini         tx_data_bytes(s, (uint32_t)value, 3);
45731e17060SPaolo Bonzini         goto no_reg_update;
45831e17060SPaolo Bonzini     }
45931e17060SPaolo Bonzini     s->regs[addr] = (s->regs[addr] & ~mask) | (value & mask);
46031e17060SPaolo Bonzini no_reg_update:
461*c4f08ffeSPeter Crosthwaite     xilinx_spips_update_cs_lines(s);
462e100f3beSPeter Crosthwaite     if ((man_start_com && s->regs[R_CONFIG] & MAN_START_EN) ||
463e100f3beSPeter Crosthwaite             (fifo8_is_empty(&s->tx_fifo) && s->regs[R_CONFIG] & MAN_START_EN)) {
46431e17060SPaolo Bonzini         xilinx_spips_flush_txfifo(s);
46531e17060SPaolo Bonzini     }
46631e17060SPaolo Bonzini     xilinx_spips_update_cs_lines(s);
467*c4f08ffeSPeter Crosthwaite     xilinx_spips_update_ixr(s);
46831e17060SPaolo Bonzini }
46931e17060SPaolo Bonzini 
47031e17060SPaolo Bonzini static const MemoryRegionOps spips_ops = {
47131e17060SPaolo Bonzini     .read = xilinx_spips_read,
47231e17060SPaolo Bonzini     .write = xilinx_spips_write,
47331e17060SPaolo Bonzini     .endianness = DEVICE_LITTLE_ENDIAN,
47431e17060SPaolo Bonzini };
47531e17060SPaolo Bonzini 
476b5cd9143SPeter Crosthwaite static void xilinx_qspips_write(void *opaque, hwaddr addr,
477b5cd9143SPeter Crosthwaite                                 uint64_t value, unsigned size)
478b5cd9143SPeter Crosthwaite {
479b5cd9143SPeter Crosthwaite     XilinxQSPIPS *q = XILINX_QSPIPS(opaque);
480b5cd9143SPeter Crosthwaite 
481b5cd9143SPeter Crosthwaite     xilinx_spips_write(opaque, addr, value, size);
482b5cd9143SPeter Crosthwaite     addr >>= 2;
483b5cd9143SPeter Crosthwaite 
484b5cd9143SPeter Crosthwaite     if (addr == R_LQSPI_CFG) {
485b5cd9143SPeter Crosthwaite         q->lqspi_cached_addr = ~0ULL;
486b5cd9143SPeter Crosthwaite     }
487b5cd9143SPeter Crosthwaite }
488b5cd9143SPeter Crosthwaite 
489b5cd9143SPeter Crosthwaite static const MemoryRegionOps qspips_ops = {
490b5cd9143SPeter Crosthwaite     .read = xilinx_spips_read,
491b5cd9143SPeter Crosthwaite     .write = xilinx_qspips_write,
492b5cd9143SPeter Crosthwaite     .endianness = DEVICE_LITTLE_ENDIAN,
493b5cd9143SPeter Crosthwaite };
494b5cd9143SPeter Crosthwaite 
49531e17060SPaolo Bonzini #define LQSPI_CACHE_SIZE 1024
49631e17060SPaolo Bonzini 
49731e17060SPaolo Bonzini static uint64_t
49831e17060SPaolo Bonzini lqspi_read(void *opaque, hwaddr addr, unsigned int size)
49931e17060SPaolo Bonzini {
50031e17060SPaolo Bonzini     int i;
5016b91f015SPeter Crosthwaite     XilinxQSPIPS *q = opaque;
50231e17060SPaolo Bonzini     XilinxSPIPS *s = opaque;
503abef5fa6SPeter Crosthwaite     uint32_t ret;
50431e17060SPaolo Bonzini 
5056b91f015SPeter Crosthwaite     if (addr >= q->lqspi_cached_addr &&
5066b91f015SPeter Crosthwaite             addr <= q->lqspi_cached_addr + LQSPI_CACHE_SIZE - 4) {
507abef5fa6SPeter Crosthwaite         ret = q->lqspi_buf[(addr - q->lqspi_cached_addr) >> 2];
508abef5fa6SPeter Crosthwaite         DB_PRINT("addr: %08x, data: %08x\n", (unsigned)addr, (unsigned)ret);
509abef5fa6SPeter Crosthwaite         return ret;
51031e17060SPaolo Bonzini     } else {
51131e17060SPaolo Bonzini         int flash_addr = (addr / num_effective_busses(s));
51231e17060SPaolo Bonzini         int slave = flash_addr >> LQSPI_ADDRESS_BITS;
51331e17060SPaolo Bonzini         int cache_entry = 0;
51431e17060SPaolo Bonzini 
51531e17060SPaolo Bonzini         DB_PRINT("config reg status: %08x\n", s->regs[R_LQSPI_CFG]);
51631e17060SPaolo Bonzini 
51731e17060SPaolo Bonzini         fifo8_reset(&s->tx_fifo);
51831e17060SPaolo Bonzini         fifo8_reset(&s->rx_fifo);
51931e17060SPaolo Bonzini 
52031e17060SPaolo Bonzini         s->regs[R_CONFIG] &= ~CS;
521*c4f08ffeSPeter Crosthwaite         s->regs[R_CONFIG] |= ((~(1 << slave) << CS_SHIFT) & CS) | MANUAL_CS;
52231e17060SPaolo Bonzini         xilinx_spips_update_cs_lines(s);
52331e17060SPaolo Bonzini 
52431e17060SPaolo Bonzini         /* instruction */
52531e17060SPaolo Bonzini         DB_PRINT("pushing read instruction: %02x\n",
52631e17060SPaolo Bonzini                  (uint8_t)(s->regs[R_LQSPI_CFG] & LQSPI_CFG_INST_CODE));
52731e17060SPaolo Bonzini         fifo8_push(&s->tx_fifo, s->regs[R_LQSPI_CFG] & LQSPI_CFG_INST_CODE);
52831e17060SPaolo Bonzini         /* read address */
52931e17060SPaolo Bonzini         DB_PRINT("pushing read address %06x\n", flash_addr);
53031e17060SPaolo Bonzini         fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 16));
53131e17060SPaolo Bonzini         fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 8));
53231e17060SPaolo Bonzini         fifo8_push(&s->tx_fifo, (uint8_t)flash_addr);
53331e17060SPaolo Bonzini         /* mode bits */
53431e17060SPaolo Bonzini         if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_MODE_EN) {
53531e17060SPaolo Bonzini             fifo8_push(&s->tx_fifo, extract32(s->regs[R_LQSPI_CFG],
53631e17060SPaolo Bonzini                                               LQSPI_CFG_MODE_SHIFT,
53731e17060SPaolo Bonzini                                               LQSPI_CFG_MODE_WIDTH));
53831e17060SPaolo Bonzini         }
53931e17060SPaolo Bonzini         /* dummy bytes */
54031e17060SPaolo Bonzini         for (i = 0; i < (extract32(s->regs[R_LQSPI_CFG], LQSPI_CFG_DUMMY_SHIFT,
54131e17060SPaolo Bonzini                                    LQSPI_CFG_DUMMY_WIDTH)); ++i) {
54231e17060SPaolo Bonzini             DB_PRINT("pushing dummy byte\n");
54331e17060SPaolo Bonzini             fifo8_push(&s->tx_fifo, 0);
54431e17060SPaolo Bonzini         }
545*c4f08ffeSPeter Crosthwaite         xilinx_spips_update_cs_lines(s);
54631e17060SPaolo Bonzini         xilinx_spips_flush_txfifo(s);
54731e17060SPaolo Bonzini         fifo8_reset(&s->rx_fifo);
54831e17060SPaolo Bonzini 
54931e17060SPaolo Bonzini         DB_PRINT("starting QSPI data read\n");
55031e17060SPaolo Bonzini 
55131e17060SPaolo Bonzini         for (i = 0; i < LQSPI_CACHE_SIZE / 4; ++i) {
55231e17060SPaolo Bonzini             tx_data_bytes(s, 0, 4);
55331e17060SPaolo Bonzini             xilinx_spips_flush_txfifo(s);
5546b91f015SPeter Crosthwaite             rx_data_bytes(s, &q->lqspi_buf[cache_entry], 4);
55531e17060SPaolo Bonzini             cache_entry++;
55631e17060SPaolo Bonzini         }
557*c4f08ffeSPeter Crosthwaite         xilinx_spips_update_cs_lines(s);
55831e17060SPaolo Bonzini 
55931e17060SPaolo Bonzini         s->regs[R_CONFIG] |= CS;
56031e17060SPaolo Bonzini         xilinx_spips_update_cs_lines(s);
56131e17060SPaolo Bonzini 
5626b91f015SPeter Crosthwaite         q->lqspi_cached_addr = addr;
56331e17060SPaolo Bonzini         return lqspi_read(opaque, addr, size);
56431e17060SPaolo Bonzini     }
56531e17060SPaolo Bonzini }
56631e17060SPaolo Bonzini 
56731e17060SPaolo Bonzini static const MemoryRegionOps lqspi_ops = {
56831e17060SPaolo Bonzini     .read = lqspi_read,
56931e17060SPaolo Bonzini     .endianness = DEVICE_NATIVE_ENDIAN,
57031e17060SPaolo Bonzini     .valid = {
57131e17060SPaolo Bonzini         .min_access_size = 4,
57231e17060SPaolo Bonzini         .max_access_size = 4
57331e17060SPaolo Bonzini     }
57431e17060SPaolo Bonzini };
57531e17060SPaolo Bonzini 
57631e17060SPaolo Bonzini static void xilinx_spips_realize(DeviceState *dev, Error **errp)
57731e17060SPaolo Bonzini {
57831e17060SPaolo Bonzini     XilinxSPIPS *s = XILINX_SPIPS(dev);
57931e17060SPaolo Bonzini     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
58010e60b35SPeter Crosthwaite     XilinxSPIPSClass *xsc = XILINX_SPIPS_GET_CLASS(s);
58131e17060SPaolo Bonzini     int i;
58231e17060SPaolo Bonzini 
5836b91f015SPeter Crosthwaite     DB_PRINT("realized spips\n");
58431e17060SPaolo Bonzini 
58531e17060SPaolo Bonzini     s->spi = g_new(SSIBus *, s->num_busses);
58631e17060SPaolo Bonzini     for (i = 0; i < s->num_busses; ++i) {
58731e17060SPaolo Bonzini         char bus_name[16];
58831e17060SPaolo Bonzini         snprintf(bus_name, 16, "spi%d", i);
58931e17060SPaolo Bonzini         s->spi[i] = ssi_create_bus(dev, bus_name);
59031e17060SPaolo Bonzini     }
59131e17060SPaolo Bonzini 
59231e17060SPaolo Bonzini     s->cs_lines = g_new0(qemu_irq, s->num_cs * s->num_busses);
59331e17060SPaolo Bonzini     ssi_auto_connect_slaves(DEVICE(s), s->cs_lines, s->spi[0]);
59431e17060SPaolo Bonzini     ssi_auto_connect_slaves(DEVICE(s), s->cs_lines, s->spi[1]);
59531e17060SPaolo Bonzini     sysbus_init_irq(sbd, &s->irq);
59631e17060SPaolo Bonzini     for (i = 0; i < s->num_cs * s->num_busses; ++i) {
59731e17060SPaolo Bonzini         sysbus_init_irq(sbd, &s->cs_lines[i]);
59831e17060SPaolo Bonzini     }
59931e17060SPaolo Bonzini 
600b5cd9143SPeter Crosthwaite     memory_region_init_io(&s->iomem, xsc->reg_ops, s, "spi", R_MAX*4);
60131e17060SPaolo Bonzini     sysbus_init_mmio(sbd, &s->iomem);
60231e17060SPaolo Bonzini 
6036b91f015SPeter Crosthwaite     s->irqline = -1;
6046b91f015SPeter Crosthwaite 
60510e60b35SPeter Crosthwaite     fifo8_create(&s->rx_fifo, xsc->rx_fifo_size);
60610e60b35SPeter Crosthwaite     fifo8_create(&s->tx_fifo, xsc->tx_fifo_size);
6076b91f015SPeter Crosthwaite }
6086b91f015SPeter Crosthwaite 
6096b91f015SPeter Crosthwaite static void xilinx_qspips_realize(DeviceState *dev, Error **errp)
6106b91f015SPeter Crosthwaite {
6116b91f015SPeter Crosthwaite     XilinxSPIPS *s = XILINX_SPIPS(dev);
6126b91f015SPeter Crosthwaite     XilinxQSPIPS *q = XILINX_QSPIPS(dev);
6136b91f015SPeter Crosthwaite     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
6146b91f015SPeter Crosthwaite 
6156b91f015SPeter Crosthwaite     DB_PRINT("realized qspips\n");
6166b91f015SPeter Crosthwaite 
6176b91f015SPeter Crosthwaite     s->num_busses = 2;
6186b91f015SPeter Crosthwaite     s->num_cs = 2;
6196b91f015SPeter Crosthwaite     s->num_txrx_bytes = 4;
6206b91f015SPeter Crosthwaite 
6216b91f015SPeter Crosthwaite     xilinx_spips_realize(dev, errp);
62231e17060SPaolo Bonzini     memory_region_init_io(&s->mmlqspi, &lqspi_ops, s, "lqspi",
62331e17060SPaolo Bonzini                           (1 << LQSPI_ADDRESS_BITS) * 2);
62431e17060SPaolo Bonzini     sysbus_init_mmio(sbd, &s->mmlqspi);
62531e17060SPaolo Bonzini 
6266b91f015SPeter Crosthwaite     q->lqspi_cached_addr = ~0ULL;
62731e17060SPaolo Bonzini }
62831e17060SPaolo Bonzini 
62931e17060SPaolo Bonzini static int xilinx_spips_post_load(void *opaque, int version_id)
63031e17060SPaolo Bonzini {
63131e17060SPaolo Bonzini     xilinx_spips_update_ixr((XilinxSPIPS *)opaque);
63231e17060SPaolo Bonzini     xilinx_spips_update_cs_lines((XilinxSPIPS *)opaque);
63331e17060SPaolo Bonzini     return 0;
63431e17060SPaolo Bonzini }
63531e17060SPaolo Bonzini 
63631e17060SPaolo Bonzini static const VMStateDescription vmstate_xilinx_spips = {
63731e17060SPaolo Bonzini     .name = "xilinx_spips",
63831e17060SPaolo Bonzini     .version_id = 2,
63931e17060SPaolo Bonzini     .minimum_version_id = 2,
64031e17060SPaolo Bonzini     .minimum_version_id_old = 2,
64131e17060SPaolo Bonzini     .post_load = xilinx_spips_post_load,
64231e17060SPaolo Bonzini     .fields = (VMStateField[]) {
64331e17060SPaolo Bonzini         VMSTATE_FIFO8(tx_fifo, XilinxSPIPS),
64431e17060SPaolo Bonzini         VMSTATE_FIFO8(rx_fifo, XilinxSPIPS),
64531e17060SPaolo Bonzini         VMSTATE_UINT32_ARRAY(regs, XilinxSPIPS, R_MAX),
64631e17060SPaolo Bonzini         VMSTATE_UINT8(snoop_state, XilinxSPIPS),
64731e17060SPaolo Bonzini         VMSTATE_END_OF_LIST()
64831e17060SPaolo Bonzini     }
64931e17060SPaolo Bonzini };
65031e17060SPaolo Bonzini 
65131e17060SPaolo Bonzini static Property xilinx_spips_properties[] = {
65231e17060SPaolo Bonzini     DEFINE_PROP_UINT8("num-busses", XilinxSPIPS, num_busses, 1),
65331e17060SPaolo Bonzini     DEFINE_PROP_UINT8("num-ss-bits", XilinxSPIPS, num_cs, 4),
65431e17060SPaolo Bonzini     DEFINE_PROP_UINT8("num-txrx-bytes", XilinxSPIPS, num_txrx_bytes, 1),
65531e17060SPaolo Bonzini     DEFINE_PROP_END_OF_LIST(),
65631e17060SPaolo Bonzini };
6576b91f015SPeter Crosthwaite 
6586b91f015SPeter Crosthwaite static void xilinx_qspips_class_init(ObjectClass *klass, void * data)
6596b91f015SPeter Crosthwaite {
6606b91f015SPeter Crosthwaite     DeviceClass *dc = DEVICE_CLASS(klass);
66110e60b35SPeter Crosthwaite     XilinxSPIPSClass *xsc = XILINX_SPIPS_CLASS(klass);
6626b91f015SPeter Crosthwaite 
6636b91f015SPeter Crosthwaite     dc->realize = xilinx_qspips_realize;
664b5cd9143SPeter Crosthwaite     xsc->reg_ops = &qspips_ops;
66510e60b35SPeter Crosthwaite     xsc->rx_fifo_size = RXFF_A_Q;
66610e60b35SPeter Crosthwaite     xsc->tx_fifo_size = TXFF_A_Q;
6676b91f015SPeter Crosthwaite }
6686b91f015SPeter Crosthwaite 
66931e17060SPaolo Bonzini static void xilinx_spips_class_init(ObjectClass *klass, void *data)
67031e17060SPaolo Bonzini {
67131e17060SPaolo Bonzini     DeviceClass *dc = DEVICE_CLASS(klass);
67210e60b35SPeter Crosthwaite     XilinxSPIPSClass *xsc = XILINX_SPIPS_CLASS(klass);
67331e17060SPaolo Bonzini 
67431e17060SPaolo Bonzini     dc->realize = xilinx_spips_realize;
67531e17060SPaolo Bonzini     dc->reset = xilinx_spips_reset;
67631e17060SPaolo Bonzini     dc->props = xilinx_spips_properties;
67731e17060SPaolo Bonzini     dc->vmsd = &vmstate_xilinx_spips;
67810e60b35SPeter Crosthwaite 
679b5cd9143SPeter Crosthwaite     xsc->reg_ops = &spips_ops;
68010e60b35SPeter Crosthwaite     xsc->rx_fifo_size = RXFF_A;
68110e60b35SPeter Crosthwaite     xsc->tx_fifo_size = TXFF_A;
68231e17060SPaolo Bonzini }
68331e17060SPaolo Bonzini 
68431e17060SPaolo Bonzini static const TypeInfo xilinx_spips_info = {
68531e17060SPaolo Bonzini     .name  = TYPE_XILINX_SPIPS,
68631e17060SPaolo Bonzini     .parent = TYPE_SYS_BUS_DEVICE,
68731e17060SPaolo Bonzini     .instance_size  = sizeof(XilinxSPIPS),
68831e17060SPaolo Bonzini     .class_init = xilinx_spips_class_init,
68910e60b35SPeter Crosthwaite     .class_size = sizeof(XilinxSPIPSClass),
69031e17060SPaolo Bonzini };
69131e17060SPaolo Bonzini 
6926b91f015SPeter Crosthwaite static const TypeInfo xilinx_qspips_info = {
6936b91f015SPeter Crosthwaite     .name  = TYPE_XILINX_QSPIPS,
6946b91f015SPeter Crosthwaite     .parent = TYPE_XILINX_SPIPS,
6956b91f015SPeter Crosthwaite     .instance_size  = sizeof(XilinxQSPIPS),
6966b91f015SPeter Crosthwaite     .class_init = xilinx_qspips_class_init,
6976b91f015SPeter Crosthwaite };
6986b91f015SPeter Crosthwaite 
69931e17060SPaolo Bonzini static void xilinx_spips_register_types(void)
70031e17060SPaolo Bonzini {
70131e17060SPaolo Bonzini     type_register_static(&xilinx_spips_info);
7026b91f015SPeter Crosthwaite     type_register_static(&xilinx_qspips_info);
70331e17060SPaolo Bonzini }
70431e17060SPaolo Bonzini 
70531e17060SPaolo Bonzini type_init(xilinx_spips_register_types)
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