131e17060SPaolo Bonzini /* 231e17060SPaolo Bonzini * QEMU model of the Xilinx Zynq SPI controller 331e17060SPaolo Bonzini * 431e17060SPaolo Bonzini * Copyright (c) 2012 Peter A. G. Crosthwaite 531e17060SPaolo Bonzini * 631e17060SPaolo Bonzini * Permission is hereby granted, free of charge, to any person obtaining a copy 731e17060SPaolo Bonzini * of this software and associated documentation files (the "Software"), to deal 831e17060SPaolo Bonzini * in the Software without restriction, including without limitation the rights 931e17060SPaolo Bonzini * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 1031e17060SPaolo Bonzini * copies of the Software, and to permit persons to whom the Software is 1131e17060SPaolo Bonzini * furnished to do so, subject to the following conditions: 1231e17060SPaolo Bonzini * 1331e17060SPaolo Bonzini * The above copyright notice and this permission notice shall be included in 1431e17060SPaolo Bonzini * all copies or substantial portions of the Software. 1531e17060SPaolo Bonzini * 1631e17060SPaolo Bonzini * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1731e17060SPaolo Bonzini * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1831e17060SPaolo Bonzini * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 1931e17060SPaolo Bonzini * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 2031e17060SPaolo Bonzini * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 2131e17060SPaolo Bonzini * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 2231e17060SPaolo Bonzini * THE SOFTWARE. 2331e17060SPaolo Bonzini */ 2431e17060SPaolo Bonzini 2531e17060SPaolo Bonzini #include "hw/sysbus.h" 2631e17060SPaolo Bonzini #include "sysemu/sysemu.h" 2731e17060SPaolo Bonzini #include "hw/ptimer.h" 2831e17060SPaolo Bonzini #include "qemu/log.h" 2931e17060SPaolo Bonzini #include "qemu/fifo8.h" 3031e17060SPaolo Bonzini #include "hw/ssi.h" 3131e17060SPaolo Bonzini #include "qemu/bitops.h" 3231e17060SPaolo Bonzini 334a5b6fa8SPeter Crosthwaite #ifndef XILINX_SPIPS_ERR_DEBUG 344a5b6fa8SPeter Crosthwaite #define XILINX_SPIPS_ERR_DEBUG 0 354a5b6fa8SPeter Crosthwaite #endif 364a5b6fa8SPeter Crosthwaite 374a5b6fa8SPeter Crosthwaite #define DB_PRINT_L(level, ...) do { \ 384a5b6fa8SPeter Crosthwaite if (XILINX_SPIPS_ERR_DEBUG > (level)) { \ 3931e17060SPaolo Bonzini fprintf(stderr, ": %s: ", __func__); \ 4031e17060SPaolo Bonzini fprintf(stderr, ## __VA_ARGS__); \ 414a5b6fa8SPeter Crosthwaite } \ 4231e17060SPaolo Bonzini } while (0); 4331e17060SPaolo Bonzini 4431e17060SPaolo Bonzini /* config register */ 4531e17060SPaolo Bonzini #define R_CONFIG (0x00 / 4) 4631e17060SPaolo Bonzini #define IFMODE (1 << 31) 4731e17060SPaolo Bonzini #define ENDIAN (1 << 26) 4831e17060SPaolo Bonzini #define MODEFAIL_GEN_EN (1 << 17) 4931e17060SPaolo Bonzini #define MAN_START_COM (1 << 16) 5031e17060SPaolo Bonzini #define MAN_START_EN (1 << 15) 5131e17060SPaolo Bonzini #define MANUAL_CS (1 << 14) 5231e17060SPaolo Bonzini #define CS (0xF << 10) 5331e17060SPaolo Bonzini #define CS_SHIFT (10) 5431e17060SPaolo Bonzini #define PERI_SEL (1 << 9) 5531e17060SPaolo Bonzini #define REF_CLK (1 << 8) 5631e17060SPaolo Bonzini #define FIFO_WIDTH (3 << 6) 5731e17060SPaolo Bonzini #define BAUD_RATE_DIV (7 << 3) 5831e17060SPaolo Bonzini #define CLK_PH (1 << 2) 5931e17060SPaolo Bonzini #define CLK_POL (1 << 1) 6031e17060SPaolo Bonzini #define MODE_SEL (1 << 0) 612133a5f6SPeter Crosthwaite #define R_CONFIG_RSVD (0x7bf40000) 6231e17060SPaolo Bonzini 6331e17060SPaolo Bonzini /* interrupt mechanism */ 6431e17060SPaolo Bonzini #define R_INTR_STATUS (0x04 / 4) 6531e17060SPaolo Bonzini #define R_INTR_EN (0x08 / 4) 6631e17060SPaolo Bonzini #define R_INTR_DIS (0x0C / 4) 6731e17060SPaolo Bonzini #define R_INTR_MASK (0x10 / 4) 6831e17060SPaolo Bonzini #define IXR_TX_FIFO_UNDERFLOW (1 << 6) 6931e17060SPaolo Bonzini #define IXR_RX_FIFO_FULL (1 << 5) 7031e17060SPaolo Bonzini #define IXR_RX_FIFO_NOT_EMPTY (1 << 4) 7131e17060SPaolo Bonzini #define IXR_TX_FIFO_FULL (1 << 3) 7231e17060SPaolo Bonzini #define IXR_TX_FIFO_NOT_FULL (1 << 2) 7331e17060SPaolo Bonzini #define IXR_TX_FIFO_MODE_FAIL (1 << 1) 7431e17060SPaolo Bonzini #define IXR_RX_FIFO_OVERFLOW (1 << 0) 7531e17060SPaolo Bonzini #define IXR_ALL ((IXR_TX_FIFO_UNDERFLOW<<1)-1) 7631e17060SPaolo Bonzini 7731e17060SPaolo Bonzini #define R_EN (0x14 / 4) 7831e17060SPaolo Bonzini #define R_DELAY (0x18 / 4) 7931e17060SPaolo Bonzini #define R_TX_DATA (0x1C / 4) 8031e17060SPaolo Bonzini #define R_RX_DATA (0x20 / 4) 8131e17060SPaolo Bonzini #define R_SLAVE_IDLE_COUNT (0x24 / 4) 8231e17060SPaolo Bonzini #define R_TX_THRES (0x28 / 4) 8331e17060SPaolo Bonzini #define R_RX_THRES (0x2C / 4) 8431e17060SPaolo Bonzini #define R_TXD1 (0x80 / 4) 8531e17060SPaolo Bonzini #define R_TXD2 (0x84 / 4) 8631e17060SPaolo Bonzini #define R_TXD3 (0x88 / 4) 8731e17060SPaolo Bonzini 8831e17060SPaolo Bonzini #define R_LQSPI_CFG (0xa0 / 4) 8931e17060SPaolo Bonzini #define R_LQSPI_CFG_RESET 0x03A002EB 9031e17060SPaolo Bonzini #define LQSPI_CFG_LQ_MODE (1 << 31) 9131e17060SPaolo Bonzini #define LQSPI_CFG_TWO_MEM (1 << 30) 9231e17060SPaolo Bonzini #define LQSPI_CFG_SEP_BUS (1 << 30) 9331e17060SPaolo Bonzini #define LQSPI_CFG_U_PAGE (1 << 28) 9431e17060SPaolo Bonzini #define LQSPI_CFG_MODE_EN (1 << 25) 9531e17060SPaolo Bonzini #define LQSPI_CFG_MODE_WIDTH 8 9631e17060SPaolo Bonzini #define LQSPI_CFG_MODE_SHIFT 16 9731e17060SPaolo Bonzini #define LQSPI_CFG_DUMMY_WIDTH 3 9831e17060SPaolo Bonzini #define LQSPI_CFG_DUMMY_SHIFT 8 9931e17060SPaolo Bonzini #define LQSPI_CFG_INST_CODE 0xFF 10031e17060SPaolo Bonzini 10131e17060SPaolo Bonzini #define R_LQSPI_STS (0xA4 / 4) 10231e17060SPaolo Bonzini #define LQSPI_STS_WR_RECVD (1 << 1) 10331e17060SPaolo Bonzini 10431e17060SPaolo Bonzini #define R_MOD_ID (0xFC / 4) 10531e17060SPaolo Bonzini 10631e17060SPaolo Bonzini #define R_MAX (R_MOD_ID+1) 10731e17060SPaolo Bonzini 10831e17060SPaolo Bonzini /* size of TXRX FIFOs */ 10931e17060SPaolo Bonzini #define RXFF_A 32 11031e17060SPaolo Bonzini #define TXFF_A 32 11131e17060SPaolo Bonzini 11210e60b35SPeter Crosthwaite #define RXFF_A_Q (64 * 4) 11310e60b35SPeter Crosthwaite #define TXFF_A_Q (64 * 4) 11410e60b35SPeter Crosthwaite 11531e17060SPaolo Bonzini /* 16MB per linear region */ 11631e17060SPaolo Bonzini #define LQSPI_ADDRESS_BITS 24 11731e17060SPaolo Bonzini /* Bite off 4k chunks at a time */ 11831e17060SPaolo Bonzini #define LQSPI_CACHE_SIZE 1024 11931e17060SPaolo Bonzini 12031e17060SPaolo Bonzini #define SNOOP_CHECKING 0xFF 12131e17060SPaolo Bonzini #define SNOOP_NONE 0xFE 12231e17060SPaolo Bonzini #define SNOOP_STRIPING 0 12331e17060SPaolo Bonzini 12431e17060SPaolo Bonzini typedef enum { 12531e17060SPaolo Bonzini READ = 0x3, 12631e17060SPaolo Bonzini FAST_READ = 0xb, 12731e17060SPaolo Bonzini DOR = 0x3b, 12831e17060SPaolo Bonzini QOR = 0x6b, 12931e17060SPaolo Bonzini DIOR = 0xbb, 13031e17060SPaolo Bonzini QIOR = 0xeb, 13131e17060SPaolo Bonzini 13231e17060SPaolo Bonzini PP = 0x2, 13331e17060SPaolo Bonzini DPP = 0xa2, 13431e17060SPaolo Bonzini QPP = 0x32, 13531e17060SPaolo Bonzini } FlashCMD; 13631e17060SPaolo Bonzini 13731e17060SPaolo Bonzini typedef struct { 1386b91f015SPeter Crosthwaite SysBusDevice parent_obj; 1396b91f015SPeter Crosthwaite 14031e17060SPaolo Bonzini MemoryRegion iomem; 14131e17060SPaolo Bonzini MemoryRegion mmlqspi; 14231e17060SPaolo Bonzini 14331e17060SPaolo Bonzini qemu_irq irq; 14431e17060SPaolo Bonzini int irqline; 14531e17060SPaolo Bonzini 14631e17060SPaolo Bonzini uint8_t num_cs; 14731e17060SPaolo Bonzini uint8_t num_busses; 14831e17060SPaolo Bonzini 14931e17060SPaolo Bonzini uint8_t snoop_state; 15031e17060SPaolo Bonzini qemu_irq *cs_lines; 15131e17060SPaolo Bonzini SSIBus **spi; 15231e17060SPaolo Bonzini 15331e17060SPaolo Bonzini Fifo8 rx_fifo; 15431e17060SPaolo Bonzini Fifo8 tx_fifo; 15531e17060SPaolo Bonzini 15631e17060SPaolo Bonzini uint8_t num_txrx_bytes; 15731e17060SPaolo Bonzini 15831e17060SPaolo Bonzini uint32_t regs[R_MAX]; 1596b91f015SPeter Crosthwaite } XilinxSPIPS; 1606b91f015SPeter Crosthwaite 1616b91f015SPeter Crosthwaite typedef struct { 1626b91f015SPeter Crosthwaite XilinxSPIPS parent_obj; 16331e17060SPaolo Bonzini 16431e17060SPaolo Bonzini uint32_t lqspi_buf[LQSPI_CACHE_SIZE]; 16531e17060SPaolo Bonzini hwaddr lqspi_cached_addr; 1666b91f015SPeter Crosthwaite } XilinxQSPIPS; 16731e17060SPaolo Bonzini 16810e60b35SPeter Crosthwaite typedef struct XilinxSPIPSClass { 16910e60b35SPeter Crosthwaite SysBusDeviceClass parent_class; 17010e60b35SPeter Crosthwaite 171b5cd9143SPeter Crosthwaite const MemoryRegionOps *reg_ops; 172b5cd9143SPeter Crosthwaite 17310e60b35SPeter Crosthwaite uint32_t rx_fifo_size; 17410e60b35SPeter Crosthwaite uint32_t tx_fifo_size; 17510e60b35SPeter Crosthwaite } XilinxSPIPSClass; 1766b91f015SPeter Crosthwaite 1776b91f015SPeter Crosthwaite #define TYPE_XILINX_SPIPS "xlnx.ps7-spi" 1786b91f015SPeter Crosthwaite #define TYPE_XILINX_QSPIPS "xlnx.ps7-qspi" 17931e17060SPaolo Bonzini 18031e17060SPaolo Bonzini #define XILINX_SPIPS(obj) \ 18131e17060SPaolo Bonzini OBJECT_CHECK(XilinxSPIPS, (obj), TYPE_XILINX_SPIPS) 18210e60b35SPeter Crosthwaite #define XILINX_SPIPS_CLASS(klass) \ 18310e60b35SPeter Crosthwaite OBJECT_CLASS_CHECK(XilinxSPIPSClass, (klass), TYPE_XILINX_SPIPS) 18410e60b35SPeter Crosthwaite #define XILINX_SPIPS_GET_CLASS(obj) \ 18510e60b35SPeter Crosthwaite OBJECT_GET_CLASS(XilinxSPIPSClass, (obj), TYPE_XILINX_SPIPS) 18610e60b35SPeter Crosthwaite 1876b91f015SPeter Crosthwaite #define XILINX_QSPIPS(obj) \ 1886b91f015SPeter Crosthwaite OBJECT_CHECK(XilinxQSPIPS, (obj), TYPE_XILINX_QSPIPS) 18931e17060SPaolo Bonzini 19031e17060SPaolo Bonzini static inline int num_effective_busses(XilinxSPIPS *s) 19131e17060SPaolo Bonzini { 19231e17060SPaolo Bonzini return (s->regs[R_LQSPI_CFG] & LQSPI_CFG_SEP_BUS && 19331e17060SPaolo Bonzini s->regs[R_LQSPI_CFG] & LQSPI_CFG_TWO_MEM) ? s->num_busses : 1; 19431e17060SPaolo Bonzini } 19531e17060SPaolo Bonzini 196c4f08ffeSPeter Crosthwaite static inline bool xilinx_spips_cs_is_set(XilinxSPIPS *s, int i, int field) 197c4f08ffeSPeter Crosthwaite { 198c4f08ffeSPeter Crosthwaite return ~field & (1 << i) && (s->regs[R_CONFIG] & MANUAL_CS 199c4f08ffeSPeter Crosthwaite || !fifo8_is_empty(&s->tx_fifo)); 200c4f08ffeSPeter Crosthwaite } 201c4f08ffeSPeter Crosthwaite 20231e17060SPaolo Bonzini static void xilinx_spips_update_cs_lines(XilinxSPIPS *s) 20331e17060SPaolo Bonzini { 20431e17060SPaolo Bonzini int i, j; 20531e17060SPaolo Bonzini bool found = false; 20631e17060SPaolo Bonzini int field = s->regs[R_CONFIG] >> CS_SHIFT; 20731e17060SPaolo Bonzini 20831e17060SPaolo Bonzini for (i = 0; i < s->num_cs; i++) { 20931e17060SPaolo Bonzini for (j = 0; j < num_effective_busses(s); j++) { 21031e17060SPaolo Bonzini int upage = !!(s->regs[R_LQSPI_STS] & LQSPI_CFG_U_PAGE); 21131e17060SPaolo Bonzini int cs_to_set = (j * s->num_cs + i + upage) % 21231e17060SPaolo Bonzini (s->num_cs * s->num_busses); 21331e17060SPaolo Bonzini 214c4f08ffeSPeter Crosthwaite if (xilinx_spips_cs_is_set(s, i, field) && !found) { 2154a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "selecting slave %d\n", i); 21631e17060SPaolo Bonzini qemu_set_irq(s->cs_lines[cs_to_set], 0); 21731e17060SPaolo Bonzini } else { 2184a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "deselecting slave %d\n", i); 21931e17060SPaolo Bonzini qemu_set_irq(s->cs_lines[cs_to_set], 1); 22031e17060SPaolo Bonzini } 22131e17060SPaolo Bonzini } 222c4f08ffeSPeter Crosthwaite if (xilinx_spips_cs_is_set(s, i, field)) { 22331e17060SPaolo Bonzini found = true; 22431e17060SPaolo Bonzini } 22531e17060SPaolo Bonzini } 22631e17060SPaolo Bonzini if (!found) { 22731e17060SPaolo Bonzini s->snoop_state = SNOOP_CHECKING; 2284a5b6fa8SPeter Crosthwaite DB_PRINT_L(1, "moving to snoop check state\n"); 22931e17060SPaolo Bonzini } 23031e17060SPaolo Bonzini } 23131e17060SPaolo Bonzini 23231e17060SPaolo Bonzini static void xilinx_spips_update_ixr(XilinxSPIPS *s) 23331e17060SPaolo Bonzini { 2343ea728d0SPeter Crosthwaite if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_LQ_MODE) { 2353ea728d0SPeter Crosthwaite return; 2363ea728d0SPeter Crosthwaite } 23731e17060SPaolo Bonzini /* These are set/cleared as they occur */ 23831e17060SPaolo Bonzini s->regs[R_INTR_STATUS] &= (IXR_TX_FIFO_UNDERFLOW | IXR_RX_FIFO_OVERFLOW | 23931e17060SPaolo Bonzini IXR_TX_FIFO_MODE_FAIL); 24031e17060SPaolo Bonzini /* these are pure functions of fifo state, set them here */ 24131e17060SPaolo Bonzini s->regs[R_INTR_STATUS] |= 24231e17060SPaolo Bonzini (fifo8_is_full(&s->rx_fifo) ? IXR_RX_FIFO_FULL : 0) | 24331e17060SPaolo Bonzini (s->rx_fifo.num >= s->regs[R_RX_THRES] ? IXR_RX_FIFO_NOT_EMPTY : 0) | 24431e17060SPaolo Bonzini (fifo8_is_full(&s->tx_fifo) ? IXR_TX_FIFO_FULL : 0) | 24531e17060SPaolo Bonzini (s->tx_fifo.num < s->regs[R_TX_THRES] ? IXR_TX_FIFO_NOT_FULL : 0); 24631e17060SPaolo Bonzini /* drive external interrupt pin */ 24731e17060SPaolo Bonzini int new_irqline = !!(s->regs[R_INTR_MASK] & s->regs[R_INTR_STATUS] & 24831e17060SPaolo Bonzini IXR_ALL); 24931e17060SPaolo Bonzini if (new_irqline != s->irqline) { 25031e17060SPaolo Bonzini s->irqline = new_irqline; 25131e17060SPaolo Bonzini qemu_set_irq(s->irq, s->irqline); 25231e17060SPaolo Bonzini } 25331e17060SPaolo Bonzini } 25431e17060SPaolo Bonzini 25531e17060SPaolo Bonzini static void xilinx_spips_reset(DeviceState *d) 25631e17060SPaolo Bonzini { 25731e17060SPaolo Bonzini XilinxSPIPS *s = XILINX_SPIPS(d); 25831e17060SPaolo Bonzini 25931e17060SPaolo Bonzini int i; 26031e17060SPaolo Bonzini for (i = 0; i < R_MAX; i++) { 26131e17060SPaolo Bonzini s->regs[i] = 0; 26231e17060SPaolo Bonzini } 26331e17060SPaolo Bonzini 26431e17060SPaolo Bonzini fifo8_reset(&s->rx_fifo); 26531e17060SPaolo Bonzini fifo8_reset(&s->rx_fifo); 26631e17060SPaolo Bonzini /* non zero resets */ 26731e17060SPaolo Bonzini s->regs[R_CONFIG] |= MODEFAIL_GEN_EN; 26831e17060SPaolo Bonzini s->regs[R_SLAVE_IDLE_COUNT] = 0xFF; 26931e17060SPaolo Bonzini s->regs[R_TX_THRES] = 1; 27031e17060SPaolo Bonzini s->regs[R_RX_THRES] = 1; 27131e17060SPaolo Bonzini /* FIXME: move magic number definition somewhere sensible */ 27231e17060SPaolo Bonzini s->regs[R_MOD_ID] = 0x01090106; 27331e17060SPaolo Bonzini s->regs[R_LQSPI_CFG] = R_LQSPI_CFG_RESET; 27431e17060SPaolo Bonzini s->snoop_state = SNOOP_CHECKING; 27531e17060SPaolo Bonzini xilinx_spips_update_ixr(s); 27631e17060SPaolo Bonzini xilinx_spips_update_cs_lines(s); 27731e17060SPaolo Bonzini } 27831e17060SPaolo Bonzini 2799151da25SPeter Crosthwaite /* N way (num) in place bit striper. Lay out row wise bits (LSB to MSB) 2809151da25SPeter Crosthwaite * column wise (from element 0 to N-1). num is the length of x, and dir 2819151da25SPeter Crosthwaite * reverses the direction of the transform. Best illustrated by example: 2829151da25SPeter Crosthwaite * Each digit in the below array is a single bit (num == 3): 2839151da25SPeter Crosthwaite * 2849151da25SPeter Crosthwaite * {{ 76543210, } ----- stripe (dir == false) -----> {{ FCheb630, } 2859151da25SPeter Crosthwaite * { hgfedcba, } { GDAfc741, } 2869151da25SPeter Crosthwaite * { HGFEDCBA, }} <---- upstripe (dir == true) ----- { HEBgda52, }} 2879151da25SPeter Crosthwaite */ 2889151da25SPeter Crosthwaite 2899151da25SPeter Crosthwaite static inline void stripe8(uint8_t *x, int num, bool dir) 2909151da25SPeter Crosthwaite { 2919151da25SPeter Crosthwaite uint8_t r[num]; 2929151da25SPeter Crosthwaite memset(r, 0, sizeof(uint8_t) * num); 2939151da25SPeter Crosthwaite int idx[2] = {0, 0}; 2949151da25SPeter Crosthwaite int bit[2] = {0, 0}; 2959151da25SPeter Crosthwaite int d = dir; 2969151da25SPeter Crosthwaite 2979151da25SPeter Crosthwaite for (idx[0] = 0; idx[0] < num; ++idx[0]) { 2989151da25SPeter Crosthwaite for (bit[0] = 0; bit[0] < 8; ++bit[0]) { 2999151da25SPeter Crosthwaite r[idx[d]] |= x[idx[!d]] & 1 << bit[!d] ? 1 << bit[d] : 0; 3009151da25SPeter Crosthwaite idx[1] = (idx[1] + 1) % num; 3019151da25SPeter Crosthwaite if (!idx[1]) { 3029151da25SPeter Crosthwaite bit[1]++; 3039151da25SPeter Crosthwaite } 3049151da25SPeter Crosthwaite } 3059151da25SPeter Crosthwaite } 3069151da25SPeter Crosthwaite memcpy(x, r, sizeof(uint8_t) * num); 3079151da25SPeter Crosthwaite } 3089151da25SPeter Crosthwaite 30931e17060SPaolo Bonzini static void xilinx_spips_flush_txfifo(XilinxSPIPS *s) 31031e17060SPaolo Bonzini { 3114a5b6fa8SPeter Crosthwaite int debug_level = 0; 3124a5b6fa8SPeter Crosthwaite 31331e17060SPaolo Bonzini for (;;) { 31431e17060SPaolo Bonzini int i; 31531e17060SPaolo Bonzini uint8_t tx = 0; 3169151da25SPeter Crosthwaite uint8_t tx_rx[num_effective_busses(s)]; 31731e17060SPaolo Bonzini 31831e17060SPaolo Bonzini if (fifo8_is_empty(&s->tx_fifo)) { 3193ea728d0SPeter Crosthwaite if (!(s->regs[R_LQSPI_CFG] & LQSPI_CFG_LQ_MODE)) { 32031e17060SPaolo Bonzini s->regs[R_INTR_STATUS] |= IXR_TX_FIFO_UNDERFLOW; 3213ea728d0SPeter Crosthwaite } 32231e17060SPaolo Bonzini xilinx_spips_update_ixr(s); 32331e17060SPaolo Bonzini return; 3249151da25SPeter Crosthwaite } else if (s->snoop_state == SNOOP_STRIPING) { 3259151da25SPeter Crosthwaite for (i = 0; i < num_effective_busses(s); ++i) { 3269151da25SPeter Crosthwaite tx_rx[i] = fifo8_pop(&s->tx_fifo); 3279151da25SPeter Crosthwaite } 3289151da25SPeter Crosthwaite stripe8(tx_rx, num_effective_busses(s), false); 32931e17060SPaolo Bonzini } else { 33031e17060SPaolo Bonzini tx = fifo8_pop(&s->tx_fifo); 3319151da25SPeter Crosthwaite for (i = 0; i < num_effective_busses(s); ++i) { 3329151da25SPeter Crosthwaite tx_rx[i] = tx; 33331e17060SPaolo Bonzini } 33431e17060SPaolo Bonzini } 3359151da25SPeter Crosthwaite 3369151da25SPeter Crosthwaite for (i = 0; i < num_effective_busses(s); ++i) { 3374a5b6fa8SPeter Crosthwaite DB_PRINT_L(debug_level, "tx = %02x\n", tx_rx[i]); 3389151da25SPeter Crosthwaite tx_rx[i] = ssi_transfer(s->spi[i], (uint32_t)tx_rx[i]); 3394a5b6fa8SPeter Crosthwaite DB_PRINT_L(debug_level, "rx = %02x\n", tx_rx[i]); 3409151da25SPeter Crosthwaite } 3419151da25SPeter Crosthwaite 34231e17060SPaolo Bonzini if (fifo8_is_full(&s->rx_fifo)) { 34331e17060SPaolo Bonzini s->regs[R_INTR_STATUS] |= IXR_RX_FIFO_OVERFLOW; 3444a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "rx FIFO overflow"); 3459151da25SPeter Crosthwaite } else if (s->snoop_state == SNOOP_STRIPING) { 3469151da25SPeter Crosthwaite stripe8(tx_rx, num_effective_busses(s), true); 3479151da25SPeter Crosthwaite for (i = 0; i < num_effective_busses(s); ++i) { 3489151da25SPeter Crosthwaite fifo8_push(&s->rx_fifo, (uint8_t)tx_rx[i]); 3499151da25SPeter Crosthwaite } 35031e17060SPaolo Bonzini } else { 3519151da25SPeter Crosthwaite fifo8_push(&s->rx_fifo, (uint8_t)tx_rx[0]); 35231e17060SPaolo Bonzini } 35331e17060SPaolo Bonzini 3544a5b6fa8SPeter Crosthwaite DB_PRINT_L(debug_level, "initial snoop state: %x\n", 3554a5b6fa8SPeter Crosthwaite (unsigned)s->snoop_state); 35631e17060SPaolo Bonzini switch (s->snoop_state) { 35731e17060SPaolo Bonzini case (SNOOP_CHECKING): 35831e17060SPaolo Bonzini switch (tx) { /* new instruction code */ 35931e17060SPaolo Bonzini case READ: /* 3 address bytes, no dummy bytes/cycles */ 36031e17060SPaolo Bonzini case PP: 36131e17060SPaolo Bonzini case DPP: 36231e17060SPaolo Bonzini case QPP: 36331e17060SPaolo Bonzini s->snoop_state = 3; 36431e17060SPaolo Bonzini break; 36531e17060SPaolo Bonzini case FAST_READ: /* 3 address bytes, 1 dummy byte */ 36631e17060SPaolo Bonzini case DOR: 36731e17060SPaolo Bonzini case QOR: 36831e17060SPaolo Bonzini case DIOR: /* FIXME: these vary between vendor - set to spansion */ 36931e17060SPaolo Bonzini s->snoop_state = 4; 37031e17060SPaolo Bonzini break; 37131e17060SPaolo Bonzini case QIOR: /* 3 address bytes, 2 dummy bytes */ 37231e17060SPaolo Bonzini s->snoop_state = 6; 37331e17060SPaolo Bonzini break; 37431e17060SPaolo Bonzini default: 37531e17060SPaolo Bonzini s->snoop_state = SNOOP_NONE; 37631e17060SPaolo Bonzini } 37731e17060SPaolo Bonzini break; 37831e17060SPaolo Bonzini case (SNOOP_STRIPING): 37931e17060SPaolo Bonzini case (SNOOP_NONE): 3804a5b6fa8SPeter Crosthwaite /* Once we hit the boring stuff - squelch debug noise */ 3814a5b6fa8SPeter Crosthwaite if (!debug_level) { 3824a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "squelching debug info ....\n"); 3834a5b6fa8SPeter Crosthwaite debug_level = 1; 3844a5b6fa8SPeter Crosthwaite } 38531e17060SPaolo Bonzini break; 38631e17060SPaolo Bonzini default: 38731e17060SPaolo Bonzini s->snoop_state--; 38831e17060SPaolo Bonzini } 3894a5b6fa8SPeter Crosthwaite DB_PRINT_L(debug_level, "final snoop state: %x\n", 3904a5b6fa8SPeter Crosthwaite (unsigned)s->snoop_state); 39131e17060SPaolo Bonzini } 39231e17060SPaolo Bonzini } 39331e17060SPaolo Bonzini 39431e17060SPaolo Bonzini static inline void rx_data_bytes(XilinxSPIPS *s, uint32_t *value, int max) 39531e17060SPaolo Bonzini { 39631e17060SPaolo Bonzini int i; 39731e17060SPaolo Bonzini 39831e17060SPaolo Bonzini *value = 0; 39931e17060SPaolo Bonzini for (i = 0; i < max && !fifo8_is_empty(&s->rx_fifo); ++i) { 40031e17060SPaolo Bonzini uint32_t next = fifo8_pop(&s->rx_fifo) & 0xFF; 40131e17060SPaolo Bonzini *value |= next << 8 * (s->regs[R_CONFIG] & ENDIAN ? 3-i : i); 40231e17060SPaolo Bonzini } 40331e17060SPaolo Bonzini } 40431e17060SPaolo Bonzini 40531e17060SPaolo Bonzini static uint64_t xilinx_spips_read(void *opaque, hwaddr addr, 40631e17060SPaolo Bonzini unsigned size) 40731e17060SPaolo Bonzini { 40831e17060SPaolo Bonzini XilinxSPIPS *s = opaque; 40931e17060SPaolo Bonzini uint32_t mask = ~0; 41031e17060SPaolo Bonzini uint32_t ret; 41131e17060SPaolo Bonzini 41231e17060SPaolo Bonzini addr >>= 2; 41331e17060SPaolo Bonzini switch (addr) { 41431e17060SPaolo Bonzini case R_CONFIG: 4152133a5f6SPeter Crosthwaite mask = ~(R_CONFIG_RSVD | MAN_START_COM); 41631e17060SPaolo Bonzini break; 41731e17060SPaolo Bonzini case R_INTR_STATUS: 41887920b44SPeter Crosthwaite ret = s->regs[addr] & IXR_ALL; 41987920b44SPeter Crosthwaite s->regs[addr] = 0; 4204a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret); 42187920b44SPeter Crosthwaite return ret; 42231e17060SPaolo Bonzini case R_INTR_MASK: 42331e17060SPaolo Bonzini mask = IXR_ALL; 42431e17060SPaolo Bonzini break; 42531e17060SPaolo Bonzini case R_EN: 42631e17060SPaolo Bonzini mask = 0x1; 42731e17060SPaolo Bonzini break; 42831e17060SPaolo Bonzini case R_SLAVE_IDLE_COUNT: 42931e17060SPaolo Bonzini mask = 0xFF; 43031e17060SPaolo Bonzini break; 43131e17060SPaolo Bonzini case R_MOD_ID: 43231e17060SPaolo Bonzini mask = 0x01FFFFFF; 43331e17060SPaolo Bonzini break; 43431e17060SPaolo Bonzini case R_INTR_EN: 43531e17060SPaolo Bonzini case R_INTR_DIS: 43631e17060SPaolo Bonzini case R_TX_DATA: 43731e17060SPaolo Bonzini mask = 0; 43831e17060SPaolo Bonzini break; 43931e17060SPaolo Bonzini case R_RX_DATA: 44031e17060SPaolo Bonzini rx_data_bytes(s, &ret, s->num_txrx_bytes); 4414a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret); 44231e17060SPaolo Bonzini xilinx_spips_update_ixr(s); 44331e17060SPaolo Bonzini return ret; 44431e17060SPaolo Bonzini } 4454a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4, 4464a5b6fa8SPeter Crosthwaite s->regs[addr] & mask); 44731e17060SPaolo Bonzini return s->regs[addr] & mask; 44831e17060SPaolo Bonzini 44931e17060SPaolo Bonzini } 45031e17060SPaolo Bonzini 45131e17060SPaolo Bonzini static inline void tx_data_bytes(XilinxSPIPS *s, uint32_t value, int num) 45231e17060SPaolo Bonzini { 45331e17060SPaolo Bonzini int i; 45431e17060SPaolo Bonzini for (i = 0; i < num && !fifo8_is_full(&s->tx_fifo); ++i) { 45531e17060SPaolo Bonzini if (s->regs[R_CONFIG] & ENDIAN) { 45631e17060SPaolo Bonzini fifo8_push(&s->tx_fifo, (uint8_t)(value >> 24)); 45731e17060SPaolo Bonzini value <<= 8; 45831e17060SPaolo Bonzini } else { 45931e17060SPaolo Bonzini fifo8_push(&s->tx_fifo, (uint8_t)value); 46031e17060SPaolo Bonzini value >>= 8; 46131e17060SPaolo Bonzini } 46231e17060SPaolo Bonzini } 46331e17060SPaolo Bonzini } 46431e17060SPaolo Bonzini 46531e17060SPaolo Bonzini static void xilinx_spips_write(void *opaque, hwaddr addr, 46631e17060SPaolo Bonzini uint64_t value, unsigned size) 46731e17060SPaolo Bonzini { 46831e17060SPaolo Bonzini int mask = ~0; 46931e17060SPaolo Bonzini int man_start_com = 0; 47031e17060SPaolo Bonzini XilinxSPIPS *s = opaque; 47131e17060SPaolo Bonzini 4724a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr, (unsigned)value); 47331e17060SPaolo Bonzini addr >>= 2; 47431e17060SPaolo Bonzini switch (addr) { 47531e17060SPaolo Bonzini case R_CONFIG: 4762133a5f6SPeter Crosthwaite mask = ~(R_CONFIG_RSVD | MAN_START_COM); 47731e17060SPaolo Bonzini if (value & MAN_START_COM) { 47831e17060SPaolo Bonzini man_start_com = 1; 47931e17060SPaolo Bonzini } 48031e17060SPaolo Bonzini break; 48131e17060SPaolo Bonzini case R_INTR_STATUS: 48231e17060SPaolo Bonzini mask = IXR_ALL; 48331e17060SPaolo Bonzini s->regs[R_INTR_STATUS] &= ~(mask & value); 48431e17060SPaolo Bonzini goto no_reg_update; 48531e17060SPaolo Bonzini case R_INTR_DIS: 48631e17060SPaolo Bonzini mask = IXR_ALL; 48731e17060SPaolo Bonzini s->regs[R_INTR_MASK] &= ~(mask & value); 48831e17060SPaolo Bonzini goto no_reg_update; 48931e17060SPaolo Bonzini case R_INTR_EN: 49031e17060SPaolo Bonzini mask = IXR_ALL; 49131e17060SPaolo Bonzini s->regs[R_INTR_MASK] |= mask & value; 49231e17060SPaolo Bonzini goto no_reg_update; 49331e17060SPaolo Bonzini case R_EN: 49431e17060SPaolo Bonzini mask = 0x1; 49531e17060SPaolo Bonzini break; 49631e17060SPaolo Bonzini case R_SLAVE_IDLE_COUNT: 49731e17060SPaolo Bonzini mask = 0xFF; 49831e17060SPaolo Bonzini break; 49931e17060SPaolo Bonzini case R_RX_DATA: 50031e17060SPaolo Bonzini case R_INTR_MASK: 50131e17060SPaolo Bonzini case R_MOD_ID: 50231e17060SPaolo Bonzini mask = 0; 50331e17060SPaolo Bonzini break; 50431e17060SPaolo Bonzini case R_TX_DATA: 50531e17060SPaolo Bonzini tx_data_bytes(s, (uint32_t)value, s->num_txrx_bytes); 50631e17060SPaolo Bonzini goto no_reg_update; 50731e17060SPaolo Bonzini case R_TXD1: 50831e17060SPaolo Bonzini tx_data_bytes(s, (uint32_t)value, 1); 50931e17060SPaolo Bonzini goto no_reg_update; 51031e17060SPaolo Bonzini case R_TXD2: 51131e17060SPaolo Bonzini tx_data_bytes(s, (uint32_t)value, 2); 51231e17060SPaolo Bonzini goto no_reg_update; 51331e17060SPaolo Bonzini case R_TXD3: 51431e17060SPaolo Bonzini tx_data_bytes(s, (uint32_t)value, 3); 51531e17060SPaolo Bonzini goto no_reg_update; 51631e17060SPaolo Bonzini } 51731e17060SPaolo Bonzini s->regs[addr] = (s->regs[addr] & ~mask) | (value & mask); 51831e17060SPaolo Bonzini no_reg_update: 519c4f08ffeSPeter Crosthwaite xilinx_spips_update_cs_lines(s); 520e100f3beSPeter Crosthwaite if ((man_start_com && s->regs[R_CONFIG] & MAN_START_EN) || 521e100f3beSPeter Crosthwaite (fifo8_is_empty(&s->tx_fifo) && s->regs[R_CONFIG] & MAN_START_EN)) { 52231e17060SPaolo Bonzini xilinx_spips_flush_txfifo(s); 52331e17060SPaolo Bonzini } 52431e17060SPaolo Bonzini xilinx_spips_update_cs_lines(s); 525c4f08ffeSPeter Crosthwaite xilinx_spips_update_ixr(s); 52631e17060SPaolo Bonzini } 52731e17060SPaolo Bonzini 52831e17060SPaolo Bonzini static const MemoryRegionOps spips_ops = { 52931e17060SPaolo Bonzini .read = xilinx_spips_read, 53031e17060SPaolo Bonzini .write = xilinx_spips_write, 53131e17060SPaolo Bonzini .endianness = DEVICE_LITTLE_ENDIAN, 53231e17060SPaolo Bonzini }; 53331e17060SPaolo Bonzini 534b5cd9143SPeter Crosthwaite static void xilinx_qspips_write(void *opaque, hwaddr addr, 535b5cd9143SPeter Crosthwaite uint64_t value, unsigned size) 536b5cd9143SPeter Crosthwaite { 537b5cd9143SPeter Crosthwaite XilinxQSPIPS *q = XILINX_QSPIPS(opaque); 538b5cd9143SPeter Crosthwaite 539b5cd9143SPeter Crosthwaite xilinx_spips_write(opaque, addr, value, size); 540b5cd9143SPeter Crosthwaite addr >>= 2; 541b5cd9143SPeter Crosthwaite 542b5cd9143SPeter Crosthwaite if (addr == R_LQSPI_CFG) { 543b5cd9143SPeter Crosthwaite q->lqspi_cached_addr = ~0ULL; 544b5cd9143SPeter Crosthwaite } 545b5cd9143SPeter Crosthwaite } 546b5cd9143SPeter Crosthwaite 547b5cd9143SPeter Crosthwaite static const MemoryRegionOps qspips_ops = { 548b5cd9143SPeter Crosthwaite .read = xilinx_spips_read, 549b5cd9143SPeter Crosthwaite .write = xilinx_qspips_write, 550b5cd9143SPeter Crosthwaite .endianness = DEVICE_LITTLE_ENDIAN, 551b5cd9143SPeter Crosthwaite }; 552b5cd9143SPeter Crosthwaite 55331e17060SPaolo Bonzini #define LQSPI_CACHE_SIZE 1024 55431e17060SPaolo Bonzini 55531e17060SPaolo Bonzini static uint64_t 55631e17060SPaolo Bonzini lqspi_read(void *opaque, hwaddr addr, unsigned int size) 55731e17060SPaolo Bonzini { 55831e17060SPaolo Bonzini int i; 5596b91f015SPeter Crosthwaite XilinxQSPIPS *q = opaque; 56031e17060SPaolo Bonzini XilinxSPIPS *s = opaque; 561abef5fa6SPeter Crosthwaite uint32_t ret; 56231e17060SPaolo Bonzini 5636b91f015SPeter Crosthwaite if (addr >= q->lqspi_cached_addr && 5646b91f015SPeter Crosthwaite addr <= q->lqspi_cached_addr + LQSPI_CACHE_SIZE - 4) { 565abef5fa6SPeter Crosthwaite ret = q->lqspi_buf[(addr - q->lqspi_cached_addr) >> 2]; 5664a5b6fa8SPeter Crosthwaite DB_PRINT_L(1, "addr: %08x, data: %08x\n", (unsigned)addr, 5674a5b6fa8SPeter Crosthwaite (unsigned)ret); 568abef5fa6SPeter Crosthwaite return ret; 56931e17060SPaolo Bonzini } else { 57031e17060SPaolo Bonzini int flash_addr = (addr / num_effective_busses(s)); 57131e17060SPaolo Bonzini int slave = flash_addr >> LQSPI_ADDRESS_BITS; 57231e17060SPaolo Bonzini int cache_entry = 0; 57315408b42SPeter Crosthwaite uint32_t u_page_save = s->regs[R_LQSPI_STS] & ~LQSPI_CFG_U_PAGE; 57415408b42SPeter Crosthwaite 57515408b42SPeter Crosthwaite s->regs[R_LQSPI_STS] &= ~LQSPI_CFG_U_PAGE; 57615408b42SPeter Crosthwaite s->regs[R_LQSPI_STS] |= slave ? LQSPI_CFG_U_PAGE : 0; 57731e17060SPaolo Bonzini 5784a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "config reg status: %08x\n", s->regs[R_LQSPI_CFG]); 57931e17060SPaolo Bonzini 58031e17060SPaolo Bonzini fifo8_reset(&s->tx_fifo); 58131e17060SPaolo Bonzini fifo8_reset(&s->rx_fifo); 58231e17060SPaolo Bonzini 58331e17060SPaolo Bonzini /* instruction */ 5844a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "pushing read instruction: %02x\n", 5854a5b6fa8SPeter Crosthwaite (unsigned)(uint8_t)(s->regs[R_LQSPI_CFG] & 5864a5b6fa8SPeter Crosthwaite LQSPI_CFG_INST_CODE)); 58731e17060SPaolo Bonzini fifo8_push(&s->tx_fifo, s->regs[R_LQSPI_CFG] & LQSPI_CFG_INST_CODE); 58831e17060SPaolo Bonzini /* read address */ 5894a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "pushing read address %06x\n", flash_addr); 59031e17060SPaolo Bonzini fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 16)); 59131e17060SPaolo Bonzini fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 8)); 59231e17060SPaolo Bonzini fifo8_push(&s->tx_fifo, (uint8_t)flash_addr); 59331e17060SPaolo Bonzini /* mode bits */ 59431e17060SPaolo Bonzini if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_MODE_EN) { 59531e17060SPaolo Bonzini fifo8_push(&s->tx_fifo, extract32(s->regs[R_LQSPI_CFG], 59631e17060SPaolo Bonzini LQSPI_CFG_MODE_SHIFT, 59731e17060SPaolo Bonzini LQSPI_CFG_MODE_WIDTH)); 59831e17060SPaolo Bonzini } 59931e17060SPaolo Bonzini /* dummy bytes */ 60031e17060SPaolo Bonzini for (i = 0; i < (extract32(s->regs[R_LQSPI_CFG], LQSPI_CFG_DUMMY_SHIFT, 60131e17060SPaolo Bonzini LQSPI_CFG_DUMMY_WIDTH)); ++i) { 6024a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "pushing dummy byte\n"); 60331e17060SPaolo Bonzini fifo8_push(&s->tx_fifo, 0); 60431e17060SPaolo Bonzini } 605c4f08ffeSPeter Crosthwaite xilinx_spips_update_cs_lines(s); 60631e17060SPaolo Bonzini xilinx_spips_flush_txfifo(s); 60731e17060SPaolo Bonzini fifo8_reset(&s->rx_fifo); 60831e17060SPaolo Bonzini 6094a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "starting QSPI data read\n"); 61031e17060SPaolo Bonzini 611*a66418f6SPeter Crosthwaite while (cache_entry < LQSPI_CACHE_SIZE / 4) { 612*a66418f6SPeter Crosthwaite for (i = 0; i < 16; ++i) { 61331e17060SPaolo Bonzini tx_data_bytes(s, 0, 4); 614*a66418f6SPeter Crosthwaite } 61531e17060SPaolo Bonzini xilinx_spips_flush_txfifo(s); 616*a66418f6SPeter Crosthwaite for (i = 0; i < 16; ++i) { 617*a66418f6SPeter Crosthwaite rx_data_bytes(s, &q->lqspi_buf[cache_entry++], 4); 618*a66418f6SPeter Crosthwaite } 61931e17060SPaolo Bonzini } 62031e17060SPaolo Bonzini 62115408b42SPeter Crosthwaite s->regs[R_LQSPI_STS] &= ~LQSPI_CFG_U_PAGE; 62215408b42SPeter Crosthwaite s->regs[R_LQSPI_STS] |= u_page_save; 62331e17060SPaolo Bonzini xilinx_spips_update_cs_lines(s); 62431e17060SPaolo Bonzini 6256b91f015SPeter Crosthwaite q->lqspi_cached_addr = addr; 62631e17060SPaolo Bonzini return lqspi_read(opaque, addr, size); 62731e17060SPaolo Bonzini } 62831e17060SPaolo Bonzini } 62931e17060SPaolo Bonzini 63031e17060SPaolo Bonzini static const MemoryRegionOps lqspi_ops = { 63131e17060SPaolo Bonzini .read = lqspi_read, 63231e17060SPaolo Bonzini .endianness = DEVICE_NATIVE_ENDIAN, 63331e17060SPaolo Bonzini .valid = { 63431e17060SPaolo Bonzini .min_access_size = 4, 63531e17060SPaolo Bonzini .max_access_size = 4 63631e17060SPaolo Bonzini } 63731e17060SPaolo Bonzini }; 63831e17060SPaolo Bonzini 63931e17060SPaolo Bonzini static void xilinx_spips_realize(DeviceState *dev, Error **errp) 64031e17060SPaolo Bonzini { 64131e17060SPaolo Bonzini XilinxSPIPS *s = XILINX_SPIPS(dev); 64231e17060SPaolo Bonzini SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 64310e60b35SPeter Crosthwaite XilinxSPIPSClass *xsc = XILINX_SPIPS_GET_CLASS(s); 64431e17060SPaolo Bonzini int i; 64531e17060SPaolo Bonzini 6464a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "realized spips\n"); 64731e17060SPaolo Bonzini 64831e17060SPaolo Bonzini s->spi = g_new(SSIBus *, s->num_busses); 64931e17060SPaolo Bonzini for (i = 0; i < s->num_busses; ++i) { 65031e17060SPaolo Bonzini char bus_name[16]; 65131e17060SPaolo Bonzini snprintf(bus_name, 16, "spi%d", i); 65231e17060SPaolo Bonzini s->spi[i] = ssi_create_bus(dev, bus_name); 65331e17060SPaolo Bonzini } 65431e17060SPaolo Bonzini 65531e17060SPaolo Bonzini s->cs_lines = g_new0(qemu_irq, s->num_cs * s->num_busses); 65631e17060SPaolo Bonzini ssi_auto_connect_slaves(DEVICE(s), s->cs_lines, s->spi[0]); 65731e17060SPaolo Bonzini ssi_auto_connect_slaves(DEVICE(s), s->cs_lines, s->spi[1]); 65831e17060SPaolo Bonzini sysbus_init_irq(sbd, &s->irq); 65931e17060SPaolo Bonzini for (i = 0; i < s->num_cs * s->num_busses; ++i) { 66031e17060SPaolo Bonzini sysbus_init_irq(sbd, &s->cs_lines[i]); 66131e17060SPaolo Bonzini } 66231e17060SPaolo Bonzini 663b5cd9143SPeter Crosthwaite memory_region_init_io(&s->iomem, xsc->reg_ops, s, "spi", R_MAX*4); 66431e17060SPaolo Bonzini sysbus_init_mmio(sbd, &s->iomem); 66531e17060SPaolo Bonzini 6666b91f015SPeter Crosthwaite s->irqline = -1; 6676b91f015SPeter Crosthwaite 66810e60b35SPeter Crosthwaite fifo8_create(&s->rx_fifo, xsc->rx_fifo_size); 66910e60b35SPeter Crosthwaite fifo8_create(&s->tx_fifo, xsc->tx_fifo_size); 6706b91f015SPeter Crosthwaite } 6716b91f015SPeter Crosthwaite 6726b91f015SPeter Crosthwaite static void xilinx_qspips_realize(DeviceState *dev, Error **errp) 6736b91f015SPeter Crosthwaite { 6746b91f015SPeter Crosthwaite XilinxSPIPS *s = XILINX_SPIPS(dev); 6756b91f015SPeter Crosthwaite XilinxQSPIPS *q = XILINX_QSPIPS(dev); 6766b91f015SPeter Crosthwaite SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 6776b91f015SPeter Crosthwaite 6784a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "realized qspips\n"); 6796b91f015SPeter Crosthwaite 6806b91f015SPeter Crosthwaite s->num_busses = 2; 6816b91f015SPeter Crosthwaite s->num_cs = 2; 6826b91f015SPeter Crosthwaite s->num_txrx_bytes = 4; 6836b91f015SPeter Crosthwaite 6846b91f015SPeter Crosthwaite xilinx_spips_realize(dev, errp); 68531e17060SPaolo Bonzini memory_region_init_io(&s->mmlqspi, &lqspi_ops, s, "lqspi", 68631e17060SPaolo Bonzini (1 << LQSPI_ADDRESS_BITS) * 2); 68731e17060SPaolo Bonzini sysbus_init_mmio(sbd, &s->mmlqspi); 68831e17060SPaolo Bonzini 6896b91f015SPeter Crosthwaite q->lqspi_cached_addr = ~0ULL; 69031e17060SPaolo Bonzini } 69131e17060SPaolo Bonzini 69231e17060SPaolo Bonzini static int xilinx_spips_post_load(void *opaque, int version_id) 69331e17060SPaolo Bonzini { 69431e17060SPaolo Bonzini xilinx_spips_update_ixr((XilinxSPIPS *)opaque); 69531e17060SPaolo Bonzini xilinx_spips_update_cs_lines((XilinxSPIPS *)opaque); 69631e17060SPaolo Bonzini return 0; 69731e17060SPaolo Bonzini } 69831e17060SPaolo Bonzini 69931e17060SPaolo Bonzini static const VMStateDescription vmstate_xilinx_spips = { 70031e17060SPaolo Bonzini .name = "xilinx_spips", 70131e17060SPaolo Bonzini .version_id = 2, 70231e17060SPaolo Bonzini .minimum_version_id = 2, 70331e17060SPaolo Bonzini .minimum_version_id_old = 2, 70431e17060SPaolo Bonzini .post_load = xilinx_spips_post_load, 70531e17060SPaolo Bonzini .fields = (VMStateField[]) { 70631e17060SPaolo Bonzini VMSTATE_FIFO8(tx_fifo, XilinxSPIPS), 70731e17060SPaolo Bonzini VMSTATE_FIFO8(rx_fifo, XilinxSPIPS), 70831e17060SPaolo Bonzini VMSTATE_UINT32_ARRAY(regs, XilinxSPIPS, R_MAX), 70931e17060SPaolo Bonzini VMSTATE_UINT8(snoop_state, XilinxSPIPS), 71031e17060SPaolo Bonzini VMSTATE_END_OF_LIST() 71131e17060SPaolo Bonzini } 71231e17060SPaolo Bonzini }; 71331e17060SPaolo Bonzini 71431e17060SPaolo Bonzini static Property xilinx_spips_properties[] = { 71531e17060SPaolo Bonzini DEFINE_PROP_UINT8("num-busses", XilinxSPIPS, num_busses, 1), 71631e17060SPaolo Bonzini DEFINE_PROP_UINT8("num-ss-bits", XilinxSPIPS, num_cs, 4), 71731e17060SPaolo Bonzini DEFINE_PROP_UINT8("num-txrx-bytes", XilinxSPIPS, num_txrx_bytes, 1), 71831e17060SPaolo Bonzini DEFINE_PROP_END_OF_LIST(), 71931e17060SPaolo Bonzini }; 7206b91f015SPeter Crosthwaite 7216b91f015SPeter Crosthwaite static void xilinx_qspips_class_init(ObjectClass *klass, void * data) 7226b91f015SPeter Crosthwaite { 7236b91f015SPeter Crosthwaite DeviceClass *dc = DEVICE_CLASS(klass); 72410e60b35SPeter Crosthwaite XilinxSPIPSClass *xsc = XILINX_SPIPS_CLASS(klass); 7256b91f015SPeter Crosthwaite 7266b91f015SPeter Crosthwaite dc->realize = xilinx_qspips_realize; 727b5cd9143SPeter Crosthwaite xsc->reg_ops = &qspips_ops; 72810e60b35SPeter Crosthwaite xsc->rx_fifo_size = RXFF_A_Q; 72910e60b35SPeter Crosthwaite xsc->tx_fifo_size = TXFF_A_Q; 7306b91f015SPeter Crosthwaite } 7316b91f015SPeter Crosthwaite 73231e17060SPaolo Bonzini static void xilinx_spips_class_init(ObjectClass *klass, void *data) 73331e17060SPaolo Bonzini { 73431e17060SPaolo Bonzini DeviceClass *dc = DEVICE_CLASS(klass); 73510e60b35SPeter Crosthwaite XilinxSPIPSClass *xsc = XILINX_SPIPS_CLASS(klass); 73631e17060SPaolo Bonzini 73731e17060SPaolo Bonzini dc->realize = xilinx_spips_realize; 73831e17060SPaolo Bonzini dc->reset = xilinx_spips_reset; 73931e17060SPaolo Bonzini dc->props = xilinx_spips_properties; 74031e17060SPaolo Bonzini dc->vmsd = &vmstate_xilinx_spips; 74110e60b35SPeter Crosthwaite 742b5cd9143SPeter Crosthwaite xsc->reg_ops = &spips_ops; 74310e60b35SPeter Crosthwaite xsc->rx_fifo_size = RXFF_A; 74410e60b35SPeter Crosthwaite xsc->tx_fifo_size = TXFF_A; 74531e17060SPaolo Bonzini } 74631e17060SPaolo Bonzini 74731e17060SPaolo Bonzini static const TypeInfo xilinx_spips_info = { 74831e17060SPaolo Bonzini .name = TYPE_XILINX_SPIPS, 74931e17060SPaolo Bonzini .parent = TYPE_SYS_BUS_DEVICE, 75031e17060SPaolo Bonzini .instance_size = sizeof(XilinxSPIPS), 75131e17060SPaolo Bonzini .class_init = xilinx_spips_class_init, 75210e60b35SPeter Crosthwaite .class_size = sizeof(XilinxSPIPSClass), 75331e17060SPaolo Bonzini }; 75431e17060SPaolo Bonzini 7556b91f015SPeter Crosthwaite static const TypeInfo xilinx_qspips_info = { 7566b91f015SPeter Crosthwaite .name = TYPE_XILINX_QSPIPS, 7576b91f015SPeter Crosthwaite .parent = TYPE_XILINX_SPIPS, 7586b91f015SPeter Crosthwaite .instance_size = sizeof(XilinxQSPIPS), 7596b91f015SPeter Crosthwaite .class_init = xilinx_qspips_class_init, 7606b91f015SPeter Crosthwaite }; 7616b91f015SPeter Crosthwaite 76231e17060SPaolo Bonzini static void xilinx_spips_register_types(void) 76331e17060SPaolo Bonzini { 76431e17060SPaolo Bonzini type_register_static(&xilinx_spips_info); 7656b91f015SPeter Crosthwaite type_register_static(&xilinx_qspips_info); 76631e17060SPaolo Bonzini } 76731e17060SPaolo Bonzini 76831e17060SPaolo Bonzini type_init(xilinx_spips_register_types) 769