131e17060SPaolo Bonzini /* 231e17060SPaolo Bonzini * QEMU model of the Xilinx Zynq SPI controller 331e17060SPaolo Bonzini * 431e17060SPaolo Bonzini * Copyright (c) 2012 Peter A. G. Crosthwaite 531e17060SPaolo Bonzini * 631e17060SPaolo Bonzini * Permission is hereby granted, free of charge, to any person obtaining a copy 731e17060SPaolo Bonzini * of this software and associated documentation files (the "Software"), to deal 831e17060SPaolo Bonzini * in the Software without restriction, including without limitation the rights 931e17060SPaolo Bonzini * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 1031e17060SPaolo Bonzini * copies of the Software, and to permit persons to whom the Software is 1131e17060SPaolo Bonzini * furnished to do so, subject to the following conditions: 1231e17060SPaolo Bonzini * 1331e17060SPaolo Bonzini * The above copyright notice and this permission notice shall be included in 1431e17060SPaolo Bonzini * all copies or substantial portions of the Software. 1531e17060SPaolo Bonzini * 1631e17060SPaolo Bonzini * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1731e17060SPaolo Bonzini * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1831e17060SPaolo Bonzini * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 1931e17060SPaolo Bonzini * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 2031e17060SPaolo Bonzini * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 2131e17060SPaolo Bonzini * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 2231e17060SPaolo Bonzini * THE SOFTWARE. 2331e17060SPaolo Bonzini */ 2431e17060SPaolo Bonzini 258ef94f0bSPeter Maydell #include "qemu/osdep.h" 2631e17060SPaolo Bonzini #include "hw/sysbus.h" 2731e17060SPaolo Bonzini #include "sysemu/sysemu.h" 2831e17060SPaolo Bonzini #include "hw/ptimer.h" 2931e17060SPaolo Bonzini #include "qemu/log.h" 3031e17060SPaolo Bonzini #include "qemu/fifo8.h" 318fd06719SAlistair Francis #include "hw/ssi/ssi.h" 3231e17060SPaolo Bonzini #include "qemu/bitops.h" 336363235bSAlistair Francis #include "hw/ssi/xilinx_spips.h" 34*83c3a1f6SKONRAD Frederic #include "qapi/error.h" 35*83c3a1f6SKONRAD Frederic #include "migration/blocker.h" 3631e17060SPaolo Bonzini 374a5b6fa8SPeter Crosthwaite #ifndef XILINX_SPIPS_ERR_DEBUG 384a5b6fa8SPeter Crosthwaite #define XILINX_SPIPS_ERR_DEBUG 0 394a5b6fa8SPeter Crosthwaite #endif 404a5b6fa8SPeter Crosthwaite 414a5b6fa8SPeter Crosthwaite #define DB_PRINT_L(level, ...) do { \ 424a5b6fa8SPeter Crosthwaite if (XILINX_SPIPS_ERR_DEBUG > (level)) { \ 4331e17060SPaolo Bonzini fprintf(stderr, ": %s: ", __func__); \ 4431e17060SPaolo Bonzini fprintf(stderr, ## __VA_ARGS__); \ 454a5b6fa8SPeter Crosthwaite } \ 4631e17060SPaolo Bonzini } while (0); 4731e17060SPaolo Bonzini 4831e17060SPaolo Bonzini /* config register */ 4931e17060SPaolo Bonzini #define R_CONFIG (0x00 / 4) 50c8f8f9fbSPeter Maydell #define IFMODE (1U << 31) 5131e17060SPaolo Bonzini #define ENDIAN (1 << 26) 5231e17060SPaolo Bonzini #define MODEFAIL_GEN_EN (1 << 17) 5331e17060SPaolo Bonzini #define MAN_START_COM (1 << 16) 5431e17060SPaolo Bonzini #define MAN_START_EN (1 << 15) 5531e17060SPaolo Bonzini #define MANUAL_CS (1 << 14) 5631e17060SPaolo Bonzini #define CS (0xF << 10) 5731e17060SPaolo Bonzini #define CS_SHIFT (10) 5831e17060SPaolo Bonzini #define PERI_SEL (1 << 9) 5931e17060SPaolo Bonzini #define REF_CLK (1 << 8) 6031e17060SPaolo Bonzini #define FIFO_WIDTH (3 << 6) 6131e17060SPaolo Bonzini #define BAUD_RATE_DIV (7 << 3) 6231e17060SPaolo Bonzini #define CLK_PH (1 << 2) 6331e17060SPaolo Bonzini #define CLK_POL (1 << 1) 6431e17060SPaolo Bonzini #define MODE_SEL (1 << 0) 652133a5f6SPeter Crosthwaite #define R_CONFIG_RSVD (0x7bf40000) 6631e17060SPaolo Bonzini 6731e17060SPaolo Bonzini /* interrupt mechanism */ 6831e17060SPaolo Bonzini #define R_INTR_STATUS (0x04 / 4) 6931e17060SPaolo Bonzini #define R_INTR_EN (0x08 / 4) 7031e17060SPaolo Bonzini #define R_INTR_DIS (0x0C / 4) 7131e17060SPaolo Bonzini #define R_INTR_MASK (0x10 / 4) 7231e17060SPaolo Bonzini #define IXR_TX_FIFO_UNDERFLOW (1 << 6) 7331e17060SPaolo Bonzini #define IXR_RX_FIFO_FULL (1 << 5) 7431e17060SPaolo Bonzini #define IXR_RX_FIFO_NOT_EMPTY (1 << 4) 7531e17060SPaolo Bonzini #define IXR_TX_FIFO_FULL (1 << 3) 7631e17060SPaolo Bonzini #define IXR_TX_FIFO_NOT_FULL (1 << 2) 7731e17060SPaolo Bonzini #define IXR_TX_FIFO_MODE_FAIL (1 << 1) 7831e17060SPaolo Bonzini #define IXR_RX_FIFO_OVERFLOW (1 << 0) 7931e17060SPaolo Bonzini #define IXR_ALL ((IXR_TX_FIFO_UNDERFLOW<<1)-1) 8031e17060SPaolo Bonzini 8131e17060SPaolo Bonzini #define R_EN (0x14 / 4) 8231e17060SPaolo Bonzini #define R_DELAY (0x18 / 4) 8331e17060SPaolo Bonzini #define R_TX_DATA (0x1C / 4) 8431e17060SPaolo Bonzini #define R_RX_DATA (0x20 / 4) 8531e17060SPaolo Bonzini #define R_SLAVE_IDLE_COUNT (0x24 / 4) 8631e17060SPaolo Bonzini #define R_TX_THRES (0x28 / 4) 8731e17060SPaolo Bonzini #define R_RX_THRES (0x2C / 4) 8831e17060SPaolo Bonzini #define R_TXD1 (0x80 / 4) 8931e17060SPaolo Bonzini #define R_TXD2 (0x84 / 4) 9031e17060SPaolo Bonzini #define R_TXD3 (0x88 / 4) 9131e17060SPaolo Bonzini 9231e17060SPaolo Bonzini #define R_LQSPI_CFG (0xa0 / 4) 9331e17060SPaolo Bonzini #define R_LQSPI_CFG_RESET 0x03A002EB 94c8f8f9fbSPeter Maydell #define LQSPI_CFG_LQ_MODE (1U << 31) 9531e17060SPaolo Bonzini #define LQSPI_CFG_TWO_MEM (1 << 30) 9631e17060SPaolo Bonzini #define LQSPI_CFG_SEP_BUS (1 << 30) 9731e17060SPaolo Bonzini #define LQSPI_CFG_U_PAGE (1 << 28) 9831e17060SPaolo Bonzini #define LQSPI_CFG_MODE_EN (1 << 25) 9931e17060SPaolo Bonzini #define LQSPI_CFG_MODE_WIDTH 8 10031e17060SPaolo Bonzini #define LQSPI_CFG_MODE_SHIFT 16 10131e17060SPaolo Bonzini #define LQSPI_CFG_DUMMY_WIDTH 3 10231e17060SPaolo Bonzini #define LQSPI_CFG_DUMMY_SHIFT 8 10331e17060SPaolo Bonzini #define LQSPI_CFG_INST_CODE 0xFF 10431e17060SPaolo Bonzini 10531e17060SPaolo Bonzini #define R_LQSPI_STS (0xA4 / 4) 10631e17060SPaolo Bonzini #define LQSPI_STS_WR_RECVD (1 << 1) 10731e17060SPaolo Bonzini 10831e17060SPaolo Bonzini #define R_MOD_ID (0xFC / 4) 10931e17060SPaolo Bonzini 11031e17060SPaolo Bonzini /* size of TXRX FIFOs */ 11131e17060SPaolo Bonzini #define RXFF_A 32 11231e17060SPaolo Bonzini #define TXFF_A 32 11331e17060SPaolo Bonzini 11410e60b35SPeter Crosthwaite #define RXFF_A_Q (64 * 4) 11510e60b35SPeter Crosthwaite #define TXFF_A_Q (64 * 4) 11610e60b35SPeter Crosthwaite 11731e17060SPaolo Bonzini /* 16MB per linear region */ 11831e17060SPaolo Bonzini #define LQSPI_ADDRESS_BITS 24 11931e17060SPaolo Bonzini /* Bite off 4k chunks at a time */ 12031e17060SPaolo Bonzini #define LQSPI_CACHE_SIZE 1024 12131e17060SPaolo Bonzini 12231e17060SPaolo Bonzini #define SNOOP_CHECKING 0xFF 12331e17060SPaolo Bonzini #define SNOOP_NONE 0xFE 12431e17060SPaolo Bonzini #define SNOOP_STRIPING 0 12531e17060SPaolo Bonzini 12631e17060SPaolo Bonzini typedef enum { 12731e17060SPaolo Bonzini READ = 0x3, 12831e17060SPaolo Bonzini FAST_READ = 0xb, 12931e17060SPaolo Bonzini DOR = 0x3b, 13031e17060SPaolo Bonzini QOR = 0x6b, 13131e17060SPaolo Bonzini DIOR = 0xbb, 13231e17060SPaolo Bonzini QIOR = 0xeb, 13331e17060SPaolo Bonzini 13431e17060SPaolo Bonzini PP = 0x2, 13531e17060SPaolo Bonzini DPP = 0xa2, 13631e17060SPaolo Bonzini QPP = 0x32, 13731e17060SPaolo Bonzini } FlashCMD; 13831e17060SPaolo Bonzini 13931e17060SPaolo Bonzini typedef struct { 1406b91f015SPeter Crosthwaite XilinxSPIPS parent_obj; 14131e17060SPaolo Bonzini 142b0b7ae62SPeter Crosthwaite uint8_t lqspi_buf[LQSPI_CACHE_SIZE]; 14331e17060SPaolo Bonzini hwaddr lqspi_cached_addr; 144*83c3a1f6SKONRAD Frederic Error *migration_blocker; 145*83c3a1f6SKONRAD Frederic bool mmio_execution_enabled; 1466b91f015SPeter Crosthwaite } XilinxQSPIPS; 14731e17060SPaolo Bonzini 14810e60b35SPeter Crosthwaite typedef struct XilinxSPIPSClass { 14910e60b35SPeter Crosthwaite SysBusDeviceClass parent_class; 15010e60b35SPeter Crosthwaite 151b5cd9143SPeter Crosthwaite const MemoryRegionOps *reg_ops; 152b5cd9143SPeter Crosthwaite 15310e60b35SPeter Crosthwaite uint32_t rx_fifo_size; 15410e60b35SPeter Crosthwaite uint32_t tx_fifo_size; 15510e60b35SPeter Crosthwaite } XilinxSPIPSClass; 1566b91f015SPeter Crosthwaite 15731e17060SPaolo Bonzini static inline int num_effective_busses(XilinxSPIPS *s) 15831e17060SPaolo Bonzini { 15931e17060SPaolo Bonzini return (s->regs[R_LQSPI_CFG] & LQSPI_CFG_SEP_BUS && 16031e17060SPaolo Bonzini s->regs[R_LQSPI_CFG] & LQSPI_CFG_TWO_MEM) ? s->num_busses : 1; 16131e17060SPaolo Bonzini } 16231e17060SPaolo Bonzini 163c4f08ffeSPeter Crosthwaite static inline bool xilinx_spips_cs_is_set(XilinxSPIPS *s, int i, int field) 164c4f08ffeSPeter Crosthwaite { 165c4f08ffeSPeter Crosthwaite return ~field & (1 << i) && (s->regs[R_CONFIG] & MANUAL_CS 166c4f08ffeSPeter Crosthwaite || !fifo8_is_empty(&s->tx_fifo)); 167c4f08ffeSPeter Crosthwaite } 168c4f08ffeSPeter Crosthwaite 16931e17060SPaolo Bonzini static void xilinx_spips_update_cs_lines(XilinxSPIPS *s) 17031e17060SPaolo Bonzini { 17131e17060SPaolo Bonzini int i, j; 17231e17060SPaolo Bonzini bool found = false; 17331e17060SPaolo Bonzini int field = s->regs[R_CONFIG] >> CS_SHIFT; 17431e17060SPaolo Bonzini 17531e17060SPaolo Bonzini for (i = 0; i < s->num_cs; i++) { 17631e17060SPaolo Bonzini for (j = 0; j < num_effective_busses(s); j++) { 17731e17060SPaolo Bonzini int upage = !!(s->regs[R_LQSPI_STS] & LQSPI_CFG_U_PAGE); 17831e17060SPaolo Bonzini int cs_to_set = (j * s->num_cs + i + upage) % 17931e17060SPaolo Bonzini (s->num_cs * s->num_busses); 18031e17060SPaolo Bonzini 181c4f08ffeSPeter Crosthwaite if (xilinx_spips_cs_is_set(s, i, field) && !found) { 1824a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "selecting slave %d\n", i); 18331e17060SPaolo Bonzini qemu_set_irq(s->cs_lines[cs_to_set], 0); 18431e17060SPaolo Bonzini } else { 1854a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "deselecting slave %d\n", i); 18631e17060SPaolo Bonzini qemu_set_irq(s->cs_lines[cs_to_set], 1); 18731e17060SPaolo Bonzini } 18831e17060SPaolo Bonzini } 189c4f08ffeSPeter Crosthwaite if (xilinx_spips_cs_is_set(s, i, field)) { 19031e17060SPaolo Bonzini found = true; 19131e17060SPaolo Bonzini } 19231e17060SPaolo Bonzini } 19331e17060SPaolo Bonzini if (!found) { 19431e17060SPaolo Bonzini s->snoop_state = SNOOP_CHECKING; 1954a5b6fa8SPeter Crosthwaite DB_PRINT_L(1, "moving to snoop check state\n"); 19631e17060SPaolo Bonzini } 19731e17060SPaolo Bonzini } 19831e17060SPaolo Bonzini 19931e17060SPaolo Bonzini static void xilinx_spips_update_ixr(XilinxSPIPS *s) 20031e17060SPaolo Bonzini { 2013ea728d0SPeter Crosthwaite if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_LQ_MODE) { 2023ea728d0SPeter Crosthwaite return; 2033ea728d0SPeter Crosthwaite } 20431e17060SPaolo Bonzini /* These are set/cleared as they occur */ 20531e17060SPaolo Bonzini s->regs[R_INTR_STATUS] &= (IXR_TX_FIFO_UNDERFLOW | IXR_RX_FIFO_OVERFLOW | 20631e17060SPaolo Bonzini IXR_TX_FIFO_MODE_FAIL); 20731e17060SPaolo Bonzini /* these are pure functions of fifo state, set them here */ 20831e17060SPaolo Bonzini s->regs[R_INTR_STATUS] |= 20931e17060SPaolo Bonzini (fifo8_is_full(&s->rx_fifo) ? IXR_RX_FIFO_FULL : 0) | 21031e17060SPaolo Bonzini (s->rx_fifo.num >= s->regs[R_RX_THRES] ? IXR_RX_FIFO_NOT_EMPTY : 0) | 21131e17060SPaolo Bonzini (fifo8_is_full(&s->tx_fifo) ? IXR_TX_FIFO_FULL : 0) | 21231e17060SPaolo Bonzini (s->tx_fifo.num < s->regs[R_TX_THRES] ? IXR_TX_FIFO_NOT_FULL : 0); 21331e17060SPaolo Bonzini /* drive external interrupt pin */ 21431e17060SPaolo Bonzini int new_irqline = !!(s->regs[R_INTR_MASK] & s->regs[R_INTR_STATUS] & 21531e17060SPaolo Bonzini IXR_ALL); 21631e17060SPaolo Bonzini if (new_irqline != s->irqline) { 21731e17060SPaolo Bonzini s->irqline = new_irqline; 21831e17060SPaolo Bonzini qemu_set_irq(s->irq, s->irqline); 21931e17060SPaolo Bonzini } 22031e17060SPaolo Bonzini } 22131e17060SPaolo Bonzini 22231e17060SPaolo Bonzini static void xilinx_spips_reset(DeviceState *d) 22331e17060SPaolo Bonzini { 22431e17060SPaolo Bonzini XilinxSPIPS *s = XILINX_SPIPS(d); 22531e17060SPaolo Bonzini 22631e17060SPaolo Bonzini int i; 2276363235bSAlistair Francis for (i = 0; i < XLNX_SPIPS_R_MAX; i++) { 22831e17060SPaolo Bonzini s->regs[i] = 0; 22931e17060SPaolo Bonzini } 23031e17060SPaolo Bonzini 23131e17060SPaolo Bonzini fifo8_reset(&s->rx_fifo); 23231e17060SPaolo Bonzini fifo8_reset(&s->rx_fifo); 23331e17060SPaolo Bonzini /* non zero resets */ 23431e17060SPaolo Bonzini s->regs[R_CONFIG] |= MODEFAIL_GEN_EN; 23531e17060SPaolo Bonzini s->regs[R_SLAVE_IDLE_COUNT] = 0xFF; 23631e17060SPaolo Bonzini s->regs[R_TX_THRES] = 1; 23731e17060SPaolo Bonzini s->regs[R_RX_THRES] = 1; 23831e17060SPaolo Bonzini /* FIXME: move magic number definition somewhere sensible */ 23931e17060SPaolo Bonzini s->regs[R_MOD_ID] = 0x01090106; 24031e17060SPaolo Bonzini s->regs[R_LQSPI_CFG] = R_LQSPI_CFG_RESET; 24131e17060SPaolo Bonzini s->snoop_state = SNOOP_CHECKING; 24231e17060SPaolo Bonzini xilinx_spips_update_ixr(s); 24331e17060SPaolo Bonzini xilinx_spips_update_cs_lines(s); 24431e17060SPaolo Bonzini } 24531e17060SPaolo Bonzini 2469151da25SPeter Crosthwaite /* N way (num) in place bit striper. Lay out row wise bits (LSB to MSB) 2479151da25SPeter Crosthwaite * column wise (from element 0 to N-1). num is the length of x, and dir 2489151da25SPeter Crosthwaite * reverses the direction of the transform. Best illustrated by example: 2499151da25SPeter Crosthwaite * Each digit in the below array is a single bit (num == 3): 2509151da25SPeter Crosthwaite * 2519151da25SPeter Crosthwaite * {{ 76543210, } ----- stripe (dir == false) -----> {{ FCheb630, } 2529151da25SPeter Crosthwaite * { hgfedcba, } { GDAfc741, } 2539151da25SPeter Crosthwaite * { HGFEDCBA, }} <---- upstripe (dir == true) ----- { HEBgda52, }} 2549151da25SPeter Crosthwaite */ 2559151da25SPeter Crosthwaite 2569151da25SPeter Crosthwaite static inline void stripe8(uint8_t *x, int num, bool dir) 2579151da25SPeter Crosthwaite { 2589151da25SPeter Crosthwaite uint8_t r[num]; 2599151da25SPeter Crosthwaite memset(r, 0, sizeof(uint8_t) * num); 2609151da25SPeter Crosthwaite int idx[2] = {0, 0}; 2619151da25SPeter Crosthwaite int bit[2] = {0, 0}; 2629151da25SPeter Crosthwaite int d = dir; 2639151da25SPeter Crosthwaite 2649151da25SPeter Crosthwaite for (idx[0] = 0; idx[0] < num; ++idx[0]) { 2659151da25SPeter Crosthwaite for (bit[0] = 0; bit[0] < 8; ++bit[0]) { 2669151da25SPeter Crosthwaite r[idx[d]] |= x[idx[!d]] & 1 << bit[!d] ? 1 << bit[d] : 0; 2679151da25SPeter Crosthwaite idx[1] = (idx[1] + 1) % num; 2689151da25SPeter Crosthwaite if (!idx[1]) { 2699151da25SPeter Crosthwaite bit[1]++; 2709151da25SPeter Crosthwaite } 2719151da25SPeter Crosthwaite } 2729151da25SPeter Crosthwaite } 2739151da25SPeter Crosthwaite memcpy(x, r, sizeof(uint8_t) * num); 2749151da25SPeter Crosthwaite } 2759151da25SPeter Crosthwaite 27631e17060SPaolo Bonzini static void xilinx_spips_flush_txfifo(XilinxSPIPS *s) 27731e17060SPaolo Bonzini { 2784a5b6fa8SPeter Crosthwaite int debug_level = 0; 2794a5b6fa8SPeter Crosthwaite 28031e17060SPaolo Bonzini for (;;) { 28131e17060SPaolo Bonzini int i; 28231e17060SPaolo Bonzini uint8_t tx = 0; 2839151da25SPeter Crosthwaite uint8_t tx_rx[num_effective_busses(s)]; 28431e17060SPaolo Bonzini 28531e17060SPaolo Bonzini if (fifo8_is_empty(&s->tx_fifo)) { 2863ea728d0SPeter Crosthwaite if (!(s->regs[R_LQSPI_CFG] & LQSPI_CFG_LQ_MODE)) { 28731e17060SPaolo Bonzini s->regs[R_INTR_STATUS] |= IXR_TX_FIFO_UNDERFLOW; 2883ea728d0SPeter Crosthwaite } 28931e17060SPaolo Bonzini xilinx_spips_update_ixr(s); 29031e17060SPaolo Bonzini return; 2919151da25SPeter Crosthwaite } else if (s->snoop_state == SNOOP_STRIPING) { 2929151da25SPeter Crosthwaite for (i = 0; i < num_effective_busses(s); ++i) { 2939151da25SPeter Crosthwaite tx_rx[i] = fifo8_pop(&s->tx_fifo); 2949151da25SPeter Crosthwaite } 2959151da25SPeter Crosthwaite stripe8(tx_rx, num_effective_busses(s), false); 29631e17060SPaolo Bonzini } else { 29731e17060SPaolo Bonzini tx = fifo8_pop(&s->tx_fifo); 2989151da25SPeter Crosthwaite for (i = 0; i < num_effective_busses(s); ++i) { 2999151da25SPeter Crosthwaite tx_rx[i] = tx; 30031e17060SPaolo Bonzini } 30131e17060SPaolo Bonzini } 3029151da25SPeter Crosthwaite 3039151da25SPeter Crosthwaite for (i = 0; i < num_effective_busses(s); ++i) { 3044a5b6fa8SPeter Crosthwaite DB_PRINT_L(debug_level, "tx = %02x\n", tx_rx[i]); 3059151da25SPeter Crosthwaite tx_rx[i] = ssi_transfer(s->spi[i], (uint32_t)tx_rx[i]); 3064a5b6fa8SPeter Crosthwaite DB_PRINT_L(debug_level, "rx = %02x\n", tx_rx[i]); 3079151da25SPeter Crosthwaite } 3089151da25SPeter Crosthwaite 30931e17060SPaolo Bonzini if (fifo8_is_full(&s->rx_fifo)) { 31031e17060SPaolo Bonzini s->regs[R_INTR_STATUS] |= IXR_RX_FIFO_OVERFLOW; 3114a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "rx FIFO overflow"); 3129151da25SPeter Crosthwaite } else if (s->snoop_state == SNOOP_STRIPING) { 3139151da25SPeter Crosthwaite stripe8(tx_rx, num_effective_busses(s), true); 3149151da25SPeter Crosthwaite for (i = 0; i < num_effective_busses(s); ++i) { 3159151da25SPeter Crosthwaite fifo8_push(&s->rx_fifo, (uint8_t)tx_rx[i]); 3169151da25SPeter Crosthwaite } 31731e17060SPaolo Bonzini } else { 3189151da25SPeter Crosthwaite fifo8_push(&s->rx_fifo, (uint8_t)tx_rx[0]); 31931e17060SPaolo Bonzini } 32031e17060SPaolo Bonzini 3214a5b6fa8SPeter Crosthwaite DB_PRINT_L(debug_level, "initial snoop state: %x\n", 3224a5b6fa8SPeter Crosthwaite (unsigned)s->snoop_state); 32331e17060SPaolo Bonzini switch (s->snoop_state) { 32431e17060SPaolo Bonzini case (SNOOP_CHECKING): 32531e17060SPaolo Bonzini switch (tx) { /* new instruction code */ 32631e17060SPaolo Bonzini case READ: /* 3 address bytes, no dummy bytes/cycles */ 32731e17060SPaolo Bonzini case PP: 32831e17060SPaolo Bonzini case DPP: 32931e17060SPaolo Bonzini case QPP: 33031e17060SPaolo Bonzini s->snoop_state = 3; 33131e17060SPaolo Bonzini break; 33231e17060SPaolo Bonzini case FAST_READ: /* 3 address bytes, 1 dummy byte */ 33331e17060SPaolo Bonzini case DOR: 33431e17060SPaolo Bonzini case QOR: 33531e17060SPaolo Bonzini case DIOR: /* FIXME: these vary between vendor - set to spansion */ 33631e17060SPaolo Bonzini s->snoop_state = 4; 33731e17060SPaolo Bonzini break; 33831e17060SPaolo Bonzini case QIOR: /* 3 address bytes, 2 dummy bytes */ 33931e17060SPaolo Bonzini s->snoop_state = 6; 34031e17060SPaolo Bonzini break; 34131e17060SPaolo Bonzini default: 34231e17060SPaolo Bonzini s->snoop_state = SNOOP_NONE; 34331e17060SPaolo Bonzini } 34431e17060SPaolo Bonzini break; 34531e17060SPaolo Bonzini case (SNOOP_STRIPING): 34631e17060SPaolo Bonzini case (SNOOP_NONE): 3474a5b6fa8SPeter Crosthwaite /* Once we hit the boring stuff - squelch debug noise */ 3484a5b6fa8SPeter Crosthwaite if (!debug_level) { 3494a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "squelching debug info ....\n"); 3504a5b6fa8SPeter Crosthwaite debug_level = 1; 3514a5b6fa8SPeter Crosthwaite } 35231e17060SPaolo Bonzini break; 35331e17060SPaolo Bonzini default: 35431e17060SPaolo Bonzini s->snoop_state--; 35531e17060SPaolo Bonzini } 3564a5b6fa8SPeter Crosthwaite DB_PRINT_L(debug_level, "final snoop state: %x\n", 3574a5b6fa8SPeter Crosthwaite (unsigned)s->snoop_state); 35831e17060SPaolo Bonzini } 35931e17060SPaolo Bonzini } 36031e17060SPaolo Bonzini 361b0b7ae62SPeter Crosthwaite static inline void rx_data_bytes(XilinxSPIPS *s, uint8_t *value, int max) 36231e17060SPaolo Bonzini { 36331e17060SPaolo Bonzini int i; 36431e17060SPaolo Bonzini 36531e17060SPaolo Bonzini for (i = 0; i < max && !fifo8_is_empty(&s->rx_fifo); ++i) { 366b0b7ae62SPeter Crosthwaite value[i] = fifo8_pop(&s->rx_fifo); 36731e17060SPaolo Bonzini } 36831e17060SPaolo Bonzini } 36931e17060SPaolo Bonzini 37031e17060SPaolo Bonzini static uint64_t xilinx_spips_read(void *opaque, hwaddr addr, 37131e17060SPaolo Bonzini unsigned size) 37231e17060SPaolo Bonzini { 37331e17060SPaolo Bonzini XilinxSPIPS *s = opaque; 37431e17060SPaolo Bonzini uint32_t mask = ~0; 37531e17060SPaolo Bonzini uint32_t ret; 376b0b7ae62SPeter Crosthwaite uint8_t rx_buf[4]; 37731e17060SPaolo Bonzini 37831e17060SPaolo Bonzini addr >>= 2; 37931e17060SPaolo Bonzini switch (addr) { 38031e17060SPaolo Bonzini case R_CONFIG: 3812133a5f6SPeter Crosthwaite mask = ~(R_CONFIG_RSVD | MAN_START_COM); 38231e17060SPaolo Bonzini break; 38331e17060SPaolo Bonzini case R_INTR_STATUS: 38487920b44SPeter Crosthwaite ret = s->regs[addr] & IXR_ALL; 38587920b44SPeter Crosthwaite s->regs[addr] = 0; 3864a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret); 38787920b44SPeter Crosthwaite return ret; 38831e17060SPaolo Bonzini case R_INTR_MASK: 38931e17060SPaolo Bonzini mask = IXR_ALL; 39031e17060SPaolo Bonzini break; 39131e17060SPaolo Bonzini case R_EN: 39231e17060SPaolo Bonzini mask = 0x1; 39331e17060SPaolo Bonzini break; 39431e17060SPaolo Bonzini case R_SLAVE_IDLE_COUNT: 39531e17060SPaolo Bonzini mask = 0xFF; 39631e17060SPaolo Bonzini break; 39731e17060SPaolo Bonzini case R_MOD_ID: 39831e17060SPaolo Bonzini mask = 0x01FFFFFF; 39931e17060SPaolo Bonzini break; 40031e17060SPaolo Bonzini case R_INTR_EN: 40131e17060SPaolo Bonzini case R_INTR_DIS: 40231e17060SPaolo Bonzini case R_TX_DATA: 40331e17060SPaolo Bonzini mask = 0; 40431e17060SPaolo Bonzini break; 40531e17060SPaolo Bonzini case R_RX_DATA: 406b0b7ae62SPeter Crosthwaite memset(rx_buf, 0, sizeof(rx_buf)); 407b0b7ae62SPeter Crosthwaite rx_data_bytes(s, rx_buf, s->num_txrx_bytes); 408b0b7ae62SPeter Crosthwaite ret = s->regs[R_CONFIG] & ENDIAN ? cpu_to_be32(*(uint32_t *)rx_buf) 409b0b7ae62SPeter Crosthwaite : cpu_to_le32(*(uint32_t *)rx_buf); 4104a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret); 41131e17060SPaolo Bonzini xilinx_spips_update_ixr(s); 41231e17060SPaolo Bonzini return ret; 41331e17060SPaolo Bonzini } 4144a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4, 4154a5b6fa8SPeter Crosthwaite s->regs[addr] & mask); 41631e17060SPaolo Bonzini return s->regs[addr] & mask; 41731e17060SPaolo Bonzini 41831e17060SPaolo Bonzini } 41931e17060SPaolo Bonzini 42031e17060SPaolo Bonzini static inline void tx_data_bytes(XilinxSPIPS *s, uint32_t value, int num) 42131e17060SPaolo Bonzini { 42231e17060SPaolo Bonzini int i; 42331e17060SPaolo Bonzini for (i = 0; i < num && !fifo8_is_full(&s->tx_fifo); ++i) { 42431e17060SPaolo Bonzini if (s->regs[R_CONFIG] & ENDIAN) { 42531e17060SPaolo Bonzini fifo8_push(&s->tx_fifo, (uint8_t)(value >> 24)); 42631e17060SPaolo Bonzini value <<= 8; 42731e17060SPaolo Bonzini } else { 42831e17060SPaolo Bonzini fifo8_push(&s->tx_fifo, (uint8_t)value); 42931e17060SPaolo Bonzini value >>= 8; 43031e17060SPaolo Bonzini } 43131e17060SPaolo Bonzini } 43231e17060SPaolo Bonzini } 43331e17060SPaolo Bonzini 43431e17060SPaolo Bonzini static void xilinx_spips_write(void *opaque, hwaddr addr, 43531e17060SPaolo Bonzini uint64_t value, unsigned size) 43631e17060SPaolo Bonzini { 43731e17060SPaolo Bonzini int mask = ~0; 43831e17060SPaolo Bonzini int man_start_com = 0; 43931e17060SPaolo Bonzini XilinxSPIPS *s = opaque; 44031e17060SPaolo Bonzini 4414a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr, (unsigned)value); 44231e17060SPaolo Bonzini addr >>= 2; 44331e17060SPaolo Bonzini switch (addr) { 44431e17060SPaolo Bonzini case R_CONFIG: 4452133a5f6SPeter Crosthwaite mask = ~(R_CONFIG_RSVD | MAN_START_COM); 44631e17060SPaolo Bonzini if (value & MAN_START_COM) { 44731e17060SPaolo Bonzini man_start_com = 1; 44831e17060SPaolo Bonzini } 44931e17060SPaolo Bonzini break; 45031e17060SPaolo Bonzini case R_INTR_STATUS: 45131e17060SPaolo Bonzini mask = IXR_ALL; 45231e17060SPaolo Bonzini s->regs[R_INTR_STATUS] &= ~(mask & value); 45331e17060SPaolo Bonzini goto no_reg_update; 45431e17060SPaolo Bonzini case R_INTR_DIS: 45531e17060SPaolo Bonzini mask = IXR_ALL; 45631e17060SPaolo Bonzini s->regs[R_INTR_MASK] &= ~(mask & value); 45731e17060SPaolo Bonzini goto no_reg_update; 45831e17060SPaolo Bonzini case R_INTR_EN: 45931e17060SPaolo Bonzini mask = IXR_ALL; 46031e17060SPaolo Bonzini s->regs[R_INTR_MASK] |= mask & value; 46131e17060SPaolo Bonzini goto no_reg_update; 46231e17060SPaolo Bonzini case R_EN: 46331e17060SPaolo Bonzini mask = 0x1; 46431e17060SPaolo Bonzini break; 46531e17060SPaolo Bonzini case R_SLAVE_IDLE_COUNT: 46631e17060SPaolo Bonzini mask = 0xFF; 46731e17060SPaolo Bonzini break; 46831e17060SPaolo Bonzini case R_RX_DATA: 46931e17060SPaolo Bonzini case R_INTR_MASK: 47031e17060SPaolo Bonzini case R_MOD_ID: 47131e17060SPaolo Bonzini mask = 0; 47231e17060SPaolo Bonzini break; 47331e17060SPaolo Bonzini case R_TX_DATA: 47431e17060SPaolo Bonzini tx_data_bytes(s, (uint32_t)value, s->num_txrx_bytes); 47531e17060SPaolo Bonzini goto no_reg_update; 47631e17060SPaolo Bonzini case R_TXD1: 47731e17060SPaolo Bonzini tx_data_bytes(s, (uint32_t)value, 1); 47831e17060SPaolo Bonzini goto no_reg_update; 47931e17060SPaolo Bonzini case R_TXD2: 48031e17060SPaolo Bonzini tx_data_bytes(s, (uint32_t)value, 2); 48131e17060SPaolo Bonzini goto no_reg_update; 48231e17060SPaolo Bonzini case R_TXD3: 48331e17060SPaolo Bonzini tx_data_bytes(s, (uint32_t)value, 3); 48431e17060SPaolo Bonzini goto no_reg_update; 48531e17060SPaolo Bonzini } 48631e17060SPaolo Bonzini s->regs[addr] = (s->regs[addr] & ~mask) | (value & mask); 48731e17060SPaolo Bonzini no_reg_update: 488c4f08ffeSPeter Crosthwaite xilinx_spips_update_cs_lines(s); 489e100f3beSPeter Crosthwaite if ((man_start_com && s->regs[R_CONFIG] & MAN_START_EN) || 490e100f3beSPeter Crosthwaite (fifo8_is_empty(&s->tx_fifo) && s->regs[R_CONFIG] & MAN_START_EN)) { 49131e17060SPaolo Bonzini xilinx_spips_flush_txfifo(s); 49231e17060SPaolo Bonzini } 49331e17060SPaolo Bonzini xilinx_spips_update_cs_lines(s); 494c4f08ffeSPeter Crosthwaite xilinx_spips_update_ixr(s); 49531e17060SPaolo Bonzini } 49631e17060SPaolo Bonzini 49731e17060SPaolo Bonzini static const MemoryRegionOps spips_ops = { 49831e17060SPaolo Bonzini .read = xilinx_spips_read, 49931e17060SPaolo Bonzini .write = xilinx_spips_write, 50031e17060SPaolo Bonzini .endianness = DEVICE_LITTLE_ENDIAN, 50131e17060SPaolo Bonzini }; 50231e17060SPaolo Bonzini 503252b99baSKONRAD Frederic static void xilinx_qspips_invalidate_mmio_ptr(XilinxQSPIPS *q) 504252b99baSKONRAD Frederic { 505252b99baSKONRAD Frederic XilinxSPIPS *s = &q->parent_obj; 506252b99baSKONRAD Frederic 507*83c3a1f6SKONRAD Frederic if ((q->mmio_execution_enabled) && (q->lqspi_cached_addr != ~0ULL)) { 508252b99baSKONRAD Frederic /* Invalidate the current mapped mmio */ 509252b99baSKONRAD Frederic memory_region_invalidate_mmio_ptr(&s->mmlqspi, q->lqspi_cached_addr, 510252b99baSKONRAD Frederic LQSPI_CACHE_SIZE); 511252b99baSKONRAD Frederic } 512*83c3a1f6SKONRAD Frederic 513*83c3a1f6SKONRAD Frederic q->lqspi_cached_addr = ~0ULL; 514252b99baSKONRAD Frederic } 515252b99baSKONRAD Frederic 516b5cd9143SPeter Crosthwaite static void xilinx_qspips_write(void *opaque, hwaddr addr, 517b5cd9143SPeter Crosthwaite uint64_t value, unsigned size) 518b5cd9143SPeter Crosthwaite { 519b5cd9143SPeter Crosthwaite XilinxQSPIPS *q = XILINX_QSPIPS(opaque); 520b5cd9143SPeter Crosthwaite 521b5cd9143SPeter Crosthwaite xilinx_spips_write(opaque, addr, value, size); 522b5cd9143SPeter Crosthwaite addr >>= 2; 523b5cd9143SPeter Crosthwaite 524b5cd9143SPeter Crosthwaite if (addr == R_LQSPI_CFG) { 525252b99baSKONRAD Frederic xilinx_qspips_invalidate_mmio_ptr(q); 526b5cd9143SPeter Crosthwaite } 527b5cd9143SPeter Crosthwaite } 528b5cd9143SPeter Crosthwaite 529b5cd9143SPeter Crosthwaite static const MemoryRegionOps qspips_ops = { 530b5cd9143SPeter Crosthwaite .read = xilinx_spips_read, 531b5cd9143SPeter Crosthwaite .write = xilinx_qspips_write, 532b5cd9143SPeter Crosthwaite .endianness = DEVICE_LITTLE_ENDIAN, 533b5cd9143SPeter Crosthwaite }; 534b5cd9143SPeter Crosthwaite 53531e17060SPaolo Bonzini #define LQSPI_CACHE_SIZE 1024 53631e17060SPaolo Bonzini 537252b99baSKONRAD Frederic static void lqspi_load_cache(void *opaque, hwaddr addr) 53831e17060SPaolo Bonzini { 5396b91f015SPeter Crosthwaite XilinxQSPIPS *q = opaque; 54031e17060SPaolo Bonzini XilinxSPIPS *s = opaque; 541252b99baSKONRAD Frederic int i; 542252b99baSKONRAD Frederic int flash_addr = ((addr & ~(LQSPI_CACHE_SIZE - 1)) 543252b99baSKONRAD Frederic / num_effective_busses(s)); 54431e17060SPaolo Bonzini int slave = flash_addr >> LQSPI_ADDRESS_BITS; 54531e17060SPaolo Bonzini int cache_entry = 0; 54615408b42SPeter Crosthwaite uint32_t u_page_save = s->regs[R_LQSPI_STS] & ~LQSPI_CFG_U_PAGE; 54715408b42SPeter Crosthwaite 548252b99baSKONRAD Frederic if (addr < q->lqspi_cached_addr || 549252b99baSKONRAD Frederic addr > q->lqspi_cached_addr + LQSPI_CACHE_SIZE - 4) { 550252b99baSKONRAD Frederic xilinx_qspips_invalidate_mmio_ptr(q); 55115408b42SPeter Crosthwaite s->regs[R_LQSPI_STS] &= ~LQSPI_CFG_U_PAGE; 55215408b42SPeter Crosthwaite s->regs[R_LQSPI_STS] |= slave ? LQSPI_CFG_U_PAGE : 0; 55331e17060SPaolo Bonzini 5544a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "config reg status: %08x\n", s->regs[R_LQSPI_CFG]); 55531e17060SPaolo Bonzini 55631e17060SPaolo Bonzini fifo8_reset(&s->tx_fifo); 55731e17060SPaolo Bonzini fifo8_reset(&s->rx_fifo); 55831e17060SPaolo Bonzini 55931e17060SPaolo Bonzini /* instruction */ 5604a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "pushing read instruction: %02x\n", 5614a5b6fa8SPeter Crosthwaite (unsigned)(uint8_t)(s->regs[R_LQSPI_CFG] & 5624a5b6fa8SPeter Crosthwaite LQSPI_CFG_INST_CODE)); 56331e17060SPaolo Bonzini fifo8_push(&s->tx_fifo, s->regs[R_LQSPI_CFG] & LQSPI_CFG_INST_CODE); 56431e17060SPaolo Bonzini /* read address */ 5654a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "pushing read address %06x\n", flash_addr); 56631e17060SPaolo Bonzini fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 16)); 56731e17060SPaolo Bonzini fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 8)); 56831e17060SPaolo Bonzini fifo8_push(&s->tx_fifo, (uint8_t)flash_addr); 56931e17060SPaolo Bonzini /* mode bits */ 57031e17060SPaolo Bonzini if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_MODE_EN) { 57131e17060SPaolo Bonzini fifo8_push(&s->tx_fifo, extract32(s->regs[R_LQSPI_CFG], 57231e17060SPaolo Bonzini LQSPI_CFG_MODE_SHIFT, 57331e17060SPaolo Bonzini LQSPI_CFG_MODE_WIDTH)); 57431e17060SPaolo Bonzini } 57531e17060SPaolo Bonzini /* dummy bytes */ 57631e17060SPaolo Bonzini for (i = 0; i < (extract32(s->regs[R_LQSPI_CFG], LQSPI_CFG_DUMMY_SHIFT, 57731e17060SPaolo Bonzini LQSPI_CFG_DUMMY_WIDTH)); ++i) { 5784a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "pushing dummy byte\n"); 57931e17060SPaolo Bonzini fifo8_push(&s->tx_fifo, 0); 58031e17060SPaolo Bonzini } 581c4f08ffeSPeter Crosthwaite xilinx_spips_update_cs_lines(s); 58231e17060SPaolo Bonzini xilinx_spips_flush_txfifo(s); 58331e17060SPaolo Bonzini fifo8_reset(&s->rx_fifo); 58431e17060SPaolo Bonzini 5854a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "starting QSPI data read\n"); 58631e17060SPaolo Bonzini 587b0b7ae62SPeter Crosthwaite while (cache_entry < LQSPI_CACHE_SIZE) { 588b0b7ae62SPeter Crosthwaite for (i = 0; i < 64; ++i) { 589b0b7ae62SPeter Crosthwaite tx_data_bytes(s, 0, 1); 590a66418f6SPeter Crosthwaite } 59131e17060SPaolo Bonzini xilinx_spips_flush_txfifo(s); 592b0b7ae62SPeter Crosthwaite for (i = 0; i < 64; ++i) { 593b0b7ae62SPeter Crosthwaite rx_data_bytes(s, &q->lqspi_buf[cache_entry++], 1); 594a66418f6SPeter Crosthwaite } 59531e17060SPaolo Bonzini } 59631e17060SPaolo Bonzini 59715408b42SPeter Crosthwaite s->regs[R_LQSPI_STS] &= ~LQSPI_CFG_U_PAGE; 59815408b42SPeter Crosthwaite s->regs[R_LQSPI_STS] |= u_page_save; 59931e17060SPaolo Bonzini xilinx_spips_update_cs_lines(s); 60031e17060SPaolo Bonzini 601b0b7ae62SPeter Crosthwaite q->lqspi_cached_addr = flash_addr * num_effective_busses(s); 602252b99baSKONRAD Frederic } 603252b99baSKONRAD Frederic } 604252b99baSKONRAD Frederic 605252b99baSKONRAD Frederic static void *lqspi_request_mmio_ptr(void *opaque, hwaddr addr, unsigned *size, 606252b99baSKONRAD Frederic unsigned *offset) 607252b99baSKONRAD Frederic { 608252b99baSKONRAD Frederic XilinxQSPIPS *q = opaque; 609*83c3a1f6SKONRAD Frederic hwaddr offset_within_the_region; 610252b99baSKONRAD Frederic 611*83c3a1f6SKONRAD Frederic if (!q->mmio_execution_enabled) { 612*83c3a1f6SKONRAD Frederic return NULL; 613*83c3a1f6SKONRAD Frederic } 614*83c3a1f6SKONRAD Frederic 615*83c3a1f6SKONRAD Frederic offset_within_the_region = addr & ~(LQSPI_CACHE_SIZE - 1); 616252b99baSKONRAD Frederic lqspi_load_cache(opaque, offset_within_the_region); 617252b99baSKONRAD Frederic *size = LQSPI_CACHE_SIZE; 618252b99baSKONRAD Frederic *offset = offset_within_the_region; 619252b99baSKONRAD Frederic return q->lqspi_buf; 620252b99baSKONRAD Frederic } 621252b99baSKONRAD Frederic 622252b99baSKONRAD Frederic static uint64_t 623252b99baSKONRAD Frederic lqspi_read(void *opaque, hwaddr addr, unsigned int size) 624252b99baSKONRAD Frederic { 625252b99baSKONRAD Frederic XilinxQSPIPS *q = opaque; 626252b99baSKONRAD Frederic uint32_t ret; 627252b99baSKONRAD Frederic 628252b99baSKONRAD Frederic if (addr >= q->lqspi_cached_addr && 629252b99baSKONRAD Frederic addr <= q->lqspi_cached_addr + LQSPI_CACHE_SIZE - 4) { 630252b99baSKONRAD Frederic uint8_t *retp = &q->lqspi_buf[addr - q->lqspi_cached_addr]; 631252b99baSKONRAD Frederic ret = cpu_to_le32(*(uint32_t *)retp); 632252b99baSKONRAD Frederic DB_PRINT_L(1, "addr: %08x, data: %08x\n", (unsigned)addr, 633252b99baSKONRAD Frederic (unsigned)ret); 634252b99baSKONRAD Frederic return ret; 635252b99baSKONRAD Frederic } else { 636252b99baSKONRAD Frederic lqspi_load_cache(opaque, addr); 63731e17060SPaolo Bonzini return lqspi_read(opaque, addr, size); 63831e17060SPaolo Bonzini } 63931e17060SPaolo Bonzini } 64031e17060SPaolo Bonzini 64131e17060SPaolo Bonzini static const MemoryRegionOps lqspi_ops = { 64231e17060SPaolo Bonzini .read = lqspi_read, 643252b99baSKONRAD Frederic .request_ptr = lqspi_request_mmio_ptr, 64431e17060SPaolo Bonzini .endianness = DEVICE_NATIVE_ENDIAN, 64531e17060SPaolo Bonzini .valid = { 646b0b7ae62SPeter Crosthwaite .min_access_size = 1, 64731e17060SPaolo Bonzini .max_access_size = 4 64831e17060SPaolo Bonzini } 64931e17060SPaolo Bonzini }; 65031e17060SPaolo Bonzini 65131e17060SPaolo Bonzini static void xilinx_spips_realize(DeviceState *dev, Error **errp) 65231e17060SPaolo Bonzini { 65331e17060SPaolo Bonzini XilinxSPIPS *s = XILINX_SPIPS(dev); 65431e17060SPaolo Bonzini SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 65510e60b35SPeter Crosthwaite XilinxSPIPSClass *xsc = XILINX_SPIPS_GET_CLASS(s); 656c8cccba3SPaolo Bonzini qemu_irq *cs; 65731e17060SPaolo Bonzini int i; 65831e17060SPaolo Bonzini 6594a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "realized spips\n"); 66031e17060SPaolo Bonzini 66131e17060SPaolo Bonzini s->spi = g_new(SSIBus *, s->num_busses); 66231e17060SPaolo Bonzini for (i = 0; i < s->num_busses; ++i) { 66331e17060SPaolo Bonzini char bus_name[16]; 66431e17060SPaolo Bonzini snprintf(bus_name, 16, "spi%d", i); 66531e17060SPaolo Bonzini s->spi[i] = ssi_create_bus(dev, bus_name); 66631e17060SPaolo Bonzini } 66731e17060SPaolo Bonzini 66831e17060SPaolo Bonzini s->cs_lines = g_new0(qemu_irq, s->num_cs * s->num_busses); 669c8cccba3SPaolo Bonzini for (i = 0, cs = s->cs_lines; i < s->num_busses; ++i, cs += s->num_cs) { 670c8cccba3SPaolo Bonzini ssi_auto_connect_slaves(DEVICE(s), cs, s->spi[i]); 671c8cccba3SPaolo Bonzini } 672c8cccba3SPaolo Bonzini 67331e17060SPaolo Bonzini sysbus_init_irq(sbd, &s->irq); 67431e17060SPaolo Bonzini for (i = 0; i < s->num_cs * s->num_busses; ++i) { 67531e17060SPaolo Bonzini sysbus_init_irq(sbd, &s->cs_lines[i]); 67631e17060SPaolo Bonzini } 67731e17060SPaolo Bonzini 67829776739SPaolo Bonzini memory_region_init_io(&s->iomem, OBJECT(s), xsc->reg_ops, s, 6796363235bSAlistair Francis "spi", XLNX_SPIPS_R_MAX * 4); 68031e17060SPaolo Bonzini sysbus_init_mmio(sbd, &s->iomem); 68131e17060SPaolo Bonzini 6826b91f015SPeter Crosthwaite s->irqline = -1; 6836b91f015SPeter Crosthwaite 68410e60b35SPeter Crosthwaite fifo8_create(&s->rx_fifo, xsc->rx_fifo_size); 68510e60b35SPeter Crosthwaite fifo8_create(&s->tx_fifo, xsc->tx_fifo_size); 6866b91f015SPeter Crosthwaite } 6876b91f015SPeter Crosthwaite 6886b91f015SPeter Crosthwaite static void xilinx_qspips_realize(DeviceState *dev, Error **errp) 6896b91f015SPeter Crosthwaite { 6906b91f015SPeter Crosthwaite XilinxSPIPS *s = XILINX_SPIPS(dev); 6916b91f015SPeter Crosthwaite XilinxQSPIPS *q = XILINX_QSPIPS(dev); 6926b91f015SPeter Crosthwaite SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 6936b91f015SPeter Crosthwaite 6944a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "realized qspips\n"); 6956b91f015SPeter Crosthwaite 6966b91f015SPeter Crosthwaite s->num_busses = 2; 6976b91f015SPeter Crosthwaite s->num_cs = 2; 6986b91f015SPeter Crosthwaite s->num_txrx_bytes = 4; 6996b91f015SPeter Crosthwaite 7006b91f015SPeter Crosthwaite xilinx_spips_realize(dev, errp); 70129776739SPaolo Bonzini memory_region_init_io(&s->mmlqspi, OBJECT(s), &lqspi_ops, s, "lqspi", 70231e17060SPaolo Bonzini (1 << LQSPI_ADDRESS_BITS) * 2); 70331e17060SPaolo Bonzini sysbus_init_mmio(sbd, &s->mmlqspi); 70431e17060SPaolo Bonzini 7056b91f015SPeter Crosthwaite q->lqspi_cached_addr = ~0ULL; 706*83c3a1f6SKONRAD Frederic 707*83c3a1f6SKONRAD Frederic /* mmio_execution breaks migration better aborting than having strange 708*83c3a1f6SKONRAD Frederic * bugs. 709*83c3a1f6SKONRAD Frederic */ 710*83c3a1f6SKONRAD Frederic if (q->mmio_execution_enabled) { 711*83c3a1f6SKONRAD Frederic error_setg(&q->migration_blocker, 712*83c3a1f6SKONRAD Frederic "enabling mmio_execution breaks migration"); 713*83c3a1f6SKONRAD Frederic migrate_add_blocker(q->migration_blocker, &error_fatal); 714*83c3a1f6SKONRAD Frederic } 71531e17060SPaolo Bonzini } 71631e17060SPaolo Bonzini 71731e17060SPaolo Bonzini static int xilinx_spips_post_load(void *opaque, int version_id) 71831e17060SPaolo Bonzini { 71931e17060SPaolo Bonzini xilinx_spips_update_ixr((XilinxSPIPS *)opaque); 72031e17060SPaolo Bonzini xilinx_spips_update_cs_lines((XilinxSPIPS *)opaque); 72131e17060SPaolo Bonzini return 0; 72231e17060SPaolo Bonzini } 72331e17060SPaolo Bonzini 72431e17060SPaolo Bonzini static const VMStateDescription vmstate_xilinx_spips = { 72531e17060SPaolo Bonzini .name = "xilinx_spips", 72631e17060SPaolo Bonzini .version_id = 2, 72731e17060SPaolo Bonzini .minimum_version_id = 2, 72831e17060SPaolo Bonzini .post_load = xilinx_spips_post_load, 72931e17060SPaolo Bonzini .fields = (VMStateField[]) { 73031e17060SPaolo Bonzini VMSTATE_FIFO8(tx_fifo, XilinxSPIPS), 73131e17060SPaolo Bonzini VMSTATE_FIFO8(rx_fifo, XilinxSPIPS), 7326363235bSAlistair Francis VMSTATE_UINT32_ARRAY(regs, XilinxSPIPS, XLNX_SPIPS_R_MAX), 73331e17060SPaolo Bonzini VMSTATE_UINT8(snoop_state, XilinxSPIPS), 73431e17060SPaolo Bonzini VMSTATE_END_OF_LIST() 73531e17060SPaolo Bonzini } 73631e17060SPaolo Bonzini }; 73731e17060SPaolo Bonzini 738*83c3a1f6SKONRAD Frederic static Property xilinx_qspips_properties[] = { 739*83c3a1f6SKONRAD Frederic /* We had to turn this off for 2.10 as it is not compatible with migration. 740*83c3a1f6SKONRAD Frederic * It can be enabled but will prevent the device to be migrated. 741*83c3a1f6SKONRAD Frederic * This will go aways when a fix will be released. 742*83c3a1f6SKONRAD Frederic */ 743*83c3a1f6SKONRAD Frederic DEFINE_PROP_BOOL("x-mmio-exec", XilinxQSPIPS, mmio_execution_enabled, 744*83c3a1f6SKONRAD Frederic false), 745*83c3a1f6SKONRAD Frederic DEFINE_PROP_END_OF_LIST(), 746*83c3a1f6SKONRAD Frederic }; 747*83c3a1f6SKONRAD Frederic 74831e17060SPaolo Bonzini static Property xilinx_spips_properties[] = { 74931e17060SPaolo Bonzini DEFINE_PROP_UINT8("num-busses", XilinxSPIPS, num_busses, 1), 75031e17060SPaolo Bonzini DEFINE_PROP_UINT8("num-ss-bits", XilinxSPIPS, num_cs, 4), 75131e17060SPaolo Bonzini DEFINE_PROP_UINT8("num-txrx-bytes", XilinxSPIPS, num_txrx_bytes, 1), 75231e17060SPaolo Bonzini DEFINE_PROP_END_OF_LIST(), 75331e17060SPaolo Bonzini }; 7546b91f015SPeter Crosthwaite 7556b91f015SPeter Crosthwaite static void xilinx_qspips_class_init(ObjectClass *klass, void * data) 7566b91f015SPeter Crosthwaite { 7576b91f015SPeter Crosthwaite DeviceClass *dc = DEVICE_CLASS(klass); 75810e60b35SPeter Crosthwaite XilinxSPIPSClass *xsc = XILINX_SPIPS_CLASS(klass); 7596b91f015SPeter Crosthwaite 7606b91f015SPeter Crosthwaite dc->realize = xilinx_qspips_realize; 761*83c3a1f6SKONRAD Frederic dc->props = xilinx_qspips_properties; 762b5cd9143SPeter Crosthwaite xsc->reg_ops = &qspips_ops; 76310e60b35SPeter Crosthwaite xsc->rx_fifo_size = RXFF_A_Q; 76410e60b35SPeter Crosthwaite xsc->tx_fifo_size = TXFF_A_Q; 7656b91f015SPeter Crosthwaite } 7666b91f015SPeter Crosthwaite 76731e17060SPaolo Bonzini static void xilinx_spips_class_init(ObjectClass *klass, void *data) 76831e17060SPaolo Bonzini { 76931e17060SPaolo Bonzini DeviceClass *dc = DEVICE_CLASS(klass); 77010e60b35SPeter Crosthwaite XilinxSPIPSClass *xsc = XILINX_SPIPS_CLASS(klass); 77131e17060SPaolo Bonzini 77231e17060SPaolo Bonzini dc->realize = xilinx_spips_realize; 77331e17060SPaolo Bonzini dc->reset = xilinx_spips_reset; 77431e17060SPaolo Bonzini dc->props = xilinx_spips_properties; 77531e17060SPaolo Bonzini dc->vmsd = &vmstate_xilinx_spips; 77610e60b35SPeter Crosthwaite 777b5cd9143SPeter Crosthwaite xsc->reg_ops = &spips_ops; 77810e60b35SPeter Crosthwaite xsc->rx_fifo_size = RXFF_A; 77910e60b35SPeter Crosthwaite xsc->tx_fifo_size = TXFF_A; 78031e17060SPaolo Bonzini } 78131e17060SPaolo Bonzini 78231e17060SPaolo Bonzini static const TypeInfo xilinx_spips_info = { 78331e17060SPaolo Bonzini .name = TYPE_XILINX_SPIPS, 78431e17060SPaolo Bonzini .parent = TYPE_SYS_BUS_DEVICE, 78531e17060SPaolo Bonzini .instance_size = sizeof(XilinxSPIPS), 78631e17060SPaolo Bonzini .class_init = xilinx_spips_class_init, 78710e60b35SPeter Crosthwaite .class_size = sizeof(XilinxSPIPSClass), 78831e17060SPaolo Bonzini }; 78931e17060SPaolo Bonzini 7906b91f015SPeter Crosthwaite static const TypeInfo xilinx_qspips_info = { 7916b91f015SPeter Crosthwaite .name = TYPE_XILINX_QSPIPS, 7926b91f015SPeter Crosthwaite .parent = TYPE_XILINX_SPIPS, 7936b91f015SPeter Crosthwaite .instance_size = sizeof(XilinxQSPIPS), 7946b91f015SPeter Crosthwaite .class_init = xilinx_qspips_class_init, 7956b91f015SPeter Crosthwaite }; 7966b91f015SPeter Crosthwaite 79731e17060SPaolo Bonzini static void xilinx_spips_register_types(void) 79831e17060SPaolo Bonzini { 79931e17060SPaolo Bonzini type_register_static(&xilinx_spips_info); 8006b91f015SPeter Crosthwaite type_register_static(&xilinx_qspips_info); 80131e17060SPaolo Bonzini } 80231e17060SPaolo Bonzini 80331e17060SPaolo Bonzini type_init(xilinx_spips_register_types) 804