131e17060SPaolo Bonzini /* 231e17060SPaolo Bonzini * QEMU model of the Xilinx Zynq SPI controller 331e17060SPaolo Bonzini * 431e17060SPaolo Bonzini * Copyright (c) 2012 Peter A. G. Crosthwaite 531e17060SPaolo Bonzini * 631e17060SPaolo Bonzini * Permission is hereby granted, free of charge, to any person obtaining a copy 731e17060SPaolo Bonzini * of this software and associated documentation files (the "Software"), to deal 831e17060SPaolo Bonzini * in the Software without restriction, including without limitation the rights 931e17060SPaolo Bonzini * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 1031e17060SPaolo Bonzini * copies of the Software, and to permit persons to whom the Software is 1131e17060SPaolo Bonzini * furnished to do so, subject to the following conditions: 1231e17060SPaolo Bonzini * 1331e17060SPaolo Bonzini * The above copyright notice and this permission notice shall be included in 1431e17060SPaolo Bonzini * all copies or substantial portions of the Software. 1531e17060SPaolo Bonzini * 1631e17060SPaolo Bonzini * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1731e17060SPaolo Bonzini * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1831e17060SPaolo Bonzini * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 1931e17060SPaolo Bonzini * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 2031e17060SPaolo Bonzini * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 2131e17060SPaolo Bonzini * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 2231e17060SPaolo Bonzini * THE SOFTWARE. 2331e17060SPaolo Bonzini */ 2431e17060SPaolo Bonzini 2531e17060SPaolo Bonzini #include "hw/sysbus.h" 2631e17060SPaolo Bonzini #include "sysemu/sysemu.h" 2731e17060SPaolo Bonzini #include "hw/ptimer.h" 2831e17060SPaolo Bonzini #include "qemu/log.h" 2931e17060SPaolo Bonzini #include "qemu/fifo8.h" 3031e17060SPaolo Bonzini #include "hw/ssi.h" 3131e17060SPaolo Bonzini #include "qemu/bitops.h" 3231e17060SPaolo Bonzini 3331e17060SPaolo Bonzini #ifdef XILINX_SPIPS_ERR_DEBUG 3431e17060SPaolo Bonzini #define DB_PRINT(...) do { \ 3531e17060SPaolo Bonzini fprintf(stderr, ": %s: ", __func__); \ 3631e17060SPaolo Bonzini fprintf(stderr, ## __VA_ARGS__); \ 3731e17060SPaolo Bonzini } while (0); 3831e17060SPaolo Bonzini #else 3931e17060SPaolo Bonzini #define DB_PRINT(...) 4031e17060SPaolo Bonzini #endif 4131e17060SPaolo Bonzini 4231e17060SPaolo Bonzini /* config register */ 4331e17060SPaolo Bonzini #define R_CONFIG (0x00 / 4) 4431e17060SPaolo Bonzini #define IFMODE (1 << 31) 4531e17060SPaolo Bonzini #define ENDIAN (1 << 26) 4631e17060SPaolo Bonzini #define MODEFAIL_GEN_EN (1 << 17) 4731e17060SPaolo Bonzini #define MAN_START_COM (1 << 16) 4831e17060SPaolo Bonzini #define MAN_START_EN (1 << 15) 4931e17060SPaolo Bonzini #define MANUAL_CS (1 << 14) 5031e17060SPaolo Bonzini #define CS (0xF << 10) 5131e17060SPaolo Bonzini #define CS_SHIFT (10) 5231e17060SPaolo Bonzini #define PERI_SEL (1 << 9) 5331e17060SPaolo Bonzini #define REF_CLK (1 << 8) 5431e17060SPaolo Bonzini #define FIFO_WIDTH (3 << 6) 5531e17060SPaolo Bonzini #define BAUD_RATE_DIV (7 << 3) 5631e17060SPaolo Bonzini #define CLK_PH (1 << 2) 5731e17060SPaolo Bonzini #define CLK_POL (1 << 1) 5831e17060SPaolo Bonzini #define MODE_SEL (1 << 0) 5931e17060SPaolo Bonzini 6031e17060SPaolo Bonzini /* interrupt mechanism */ 6131e17060SPaolo Bonzini #define R_INTR_STATUS (0x04 / 4) 6231e17060SPaolo Bonzini #define R_INTR_EN (0x08 / 4) 6331e17060SPaolo Bonzini #define R_INTR_DIS (0x0C / 4) 6431e17060SPaolo Bonzini #define R_INTR_MASK (0x10 / 4) 6531e17060SPaolo Bonzini #define IXR_TX_FIFO_UNDERFLOW (1 << 6) 6631e17060SPaolo Bonzini #define IXR_RX_FIFO_FULL (1 << 5) 6731e17060SPaolo Bonzini #define IXR_RX_FIFO_NOT_EMPTY (1 << 4) 6831e17060SPaolo Bonzini #define IXR_TX_FIFO_FULL (1 << 3) 6931e17060SPaolo Bonzini #define IXR_TX_FIFO_NOT_FULL (1 << 2) 7031e17060SPaolo Bonzini #define IXR_TX_FIFO_MODE_FAIL (1 << 1) 7131e17060SPaolo Bonzini #define IXR_RX_FIFO_OVERFLOW (1 << 0) 7231e17060SPaolo Bonzini #define IXR_ALL ((IXR_TX_FIFO_UNDERFLOW<<1)-1) 7331e17060SPaolo Bonzini 7431e17060SPaolo Bonzini #define R_EN (0x14 / 4) 7531e17060SPaolo Bonzini #define R_DELAY (0x18 / 4) 7631e17060SPaolo Bonzini #define R_TX_DATA (0x1C / 4) 7731e17060SPaolo Bonzini #define R_RX_DATA (0x20 / 4) 7831e17060SPaolo Bonzini #define R_SLAVE_IDLE_COUNT (0x24 / 4) 7931e17060SPaolo Bonzini #define R_TX_THRES (0x28 / 4) 8031e17060SPaolo Bonzini #define R_RX_THRES (0x2C / 4) 8131e17060SPaolo Bonzini #define R_TXD1 (0x80 / 4) 8231e17060SPaolo Bonzini #define R_TXD2 (0x84 / 4) 8331e17060SPaolo Bonzini #define R_TXD3 (0x88 / 4) 8431e17060SPaolo Bonzini 8531e17060SPaolo Bonzini #define R_LQSPI_CFG (0xa0 / 4) 8631e17060SPaolo Bonzini #define R_LQSPI_CFG_RESET 0x03A002EB 8731e17060SPaolo Bonzini #define LQSPI_CFG_LQ_MODE (1 << 31) 8831e17060SPaolo Bonzini #define LQSPI_CFG_TWO_MEM (1 << 30) 8931e17060SPaolo Bonzini #define LQSPI_CFG_SEP_BUS (1 << 30) 9031e17060SPaolo Bonzini #define LQSPI_CFG_U_PAGE (1 << 28) 9131e17060SPaolo Bonzini #define LQSPI_CFG_MODE_EN (1 << 25) 9231e17060SPaolo Bonzini #define LQSPI_CFG_MODE_WIDTH 8 9331e17060SPaolo Bonzini #define LQSPI_CFG_MODE_SHIFT 16 9431e17060SPaolo Bonzini #define LQSPI_CFG_DUMMY_WIDTH 3 9531e17060SPaolo Bonzini #define LQSPI_CFG_DUMMY_SHIFT 8 9631e17060SPaolo Bonzini #define LQSPI_CFG_INST_CODE 0xFF 9731e17060SPaolo Bonzini 9831e17060SPaolo Bonzini #define R_LQSPI_STS (0xA4 / 4) 9931e17060SPaolo Bonzini #define LQSPI_STS_WR_RECVD (1 << 1) 10031e17060SPaolo Bonzini 10131e17060SPaolo Bonzini #define R_MOD_ID (0xFC / 4) 10231e17060SPaolo Bonzini 10331e17060SPaolo Bonzini #define R_MAX (R_MOD_ID+1) 10431e17060SPaolo Bonzini 10531e17060SPaolo Bonzini /* size of TXRX FIFOs */ 10631e17060SPaolo Bonzini #define RXFF_A 32 10731e17060SPaolo Bonzini #define TXFF_A 32 10831e17060SPaolo Bonzini 10931e17060SPaolo Bonzini /* 16MB per linear region */ 11031e17060SPaolo Bonzini #define LQSPI_ADDRESS_BITS 24 11131e17060SPaolo Bonzini /* Bite off 4k chunks at a time */ 11231e17060SPaolo Bonzini #define LQSPI_CACHE_SIZE 1024 11331e17060SPaolo Bonzini 11431e17060SPaolo Bonzini #define SNOOP_CHECKING 0xFF 11531e17060SPaolo Bonzini #define SNOOP_NONE 0xFE 11631e17060SPaolo Bonzini #define SNOOP_STRIPING 0 11731e17060SPaolo Bonzini 11831e17060SPaolo Bonzini typedef enum { 11931e17060SPaolo Bonzini READ = 0x3, 12031e17060SPaolo Bonzini FAST_READ = 0xb, 12131e17060SPaolo Bonzini DOR = 0x3b, 12231e17060SPaolo Bonzini QOR = 0x6b, 12331e17060SPaolo Bonzini DIOR = 0xbb, 12431e17060SPaolo Bonzini QIOR = 0xeb, 12531e17060SPaolo Bonzini 12631e17060SPaolo Bonzini PP = 0x2, 12731e17060SPaolo Bonzini DPP = 0xa2, 12831e17060SPaolo Bonzini QPP = 0x32, 12931e17060SPaolo Bonzini } FlashCMD; 13031e17060SPaolo Bonzini 13131e17060SPaolo Bonzini typedef struct { 132*6b91f015SPeter Crosthwaite SysBusDevice parent_obj; 133*6b91f015SPeter Crosthwaite 13431e17060SPaolo Bonzini MemoryRegion iomem; 13531e17060SPaolo Bonzini MemoryRegion mmlqspi; 13631e17060SPaolo Bonzini 13731e17060SPaolo Bonzini qemu_irq irq; 13831e17060SPaolo Bonzini int irqline; 13931e17060SPaolo Bonzini 14031e17060SPaolo Bonzini uint8_t num_cs; 14131e17060SPaolo Bonzini uint8_t num_busses; 14231e17060SPaolo Bonzini 14331e17060SPaolo Bonzini uint8_t snoop_state; 14431e17060SPaolo Bonzini qemu_irq *cs_lines; 14531e17060SPaolo Bonzini SSIBus **spi; 14631e17060SPaolo Bonzini 14731e17060SPaolo Bonzini Fifo8 rx_fifo; 14831e17060SPaolo Bonzini Fifo8 tx_fifo; 14931e17060SPaolo Bonzini 15031e17060SPaolo Bonzini uint8_t num_txrx_bytes; 15131e17060SPaolo Bonzini 15231e17060SPaolo Bonzini uint32_t regs[R_MAX]; 153*6b91f015SPeter Crosthwaite } XilinxSPIPS; 154*6b91f015SPeter Crosthwaite 155*6b91f015SPeter Crosthwaite typedef struct { 156*6b91f015SPeter Crosthwaite XilinxSPIPS parent_obj; 15731e17060SPaolo Bonzini 15831e17060SPaolo Bonzini uint32_t lqspi_buf[LQSPI_CACHE_SIZE]; 15931e17060SPaolo Bonzini hwaddr lqspi_cached_addr; 160*6b91f015SPeter Crosthwaite } XilinxQSPIPS; 16131e17060SPaolo Bonzini 162*6b91f015SPeter Crosthwaite 163*6b91f015SPeter Crosthwaite #define TYPE_XILINX_SPIPS "xlnx.ps7-spi" 164*6b91f015SPeter Crosthwaite #define TYPE_XILINX_QSPIPS "xlnx.ps7-qspi" 16531e17060SPaolo Bonzini 16631e17060SPaolo Bonzini #define XILINX_SPIPS(obj) \ 16731e17060SPaolo Bonzini OBJECT_CHECK(XilinxSPIPS, (obj), TYPE_XILINX_SPIPS) 168*6b91f015SPeter Crosthwaite #define XILINX_QSPIPS(obj) \ 169*6b91f015SPeter Crosthwaite OBJECT_CHECK(XilinxQSPIPS, (obj), TYPE_XILINX_QSPIPS) 17031e17060SPaolo Bonzini 17131e17060SPaolo Bonzini static inline int num_effective_busses(XilinxSPIPS *s) 17231e17060SPaolo Bonzini { 17331e17060SPaolo Bonzini return (s->regs[R_LQSPI_CFG] & LQSPI_CFG_SEP_BUS && 17431e17060SPaolo Bonzini s->regs[R_LQSPI_CFG] & LQSPI_CFG_TWO_MEM) ? s->num_busses : 1; 17531e17060SPaolo Bonzini } 17631e17060SPaolo Bonzini 17731e17060SPaolo Bonzini static void xilinx_spips_update_cs_lines(XilinxSPIPS *s) 17831e17060SPaolo Bonzini { 17931e17060SPaolo Bonzini int i, j; 18031e17060SPaolo Bonzini bool found = false; 18131e17060SPaolo Bonzini int field = s->regs[R_CONFIG] >> CS_SHIFT; 18231e17060SPaolo Bonzini 18331e17060SPaolo Bonzini for (i = 0; i < s->num_cs; i++) { 18431e17060SPaolo Bonzini for (j = 0; j < num_effective_busses(s); j++) { 18531e17060SPaolo Bonzini int upage = !!(s->regs[R_LQSPI_STS] & LQSPI_CFG_U_PAGE); 18631e17060SPaolo Bonzini int cs_to_set = (j * s->num_cs + i + upage) % 18731e17060SPaolo Bonzini (s->num_cs * s->num_busses); 18831e17060SPaolo Bonzini 18931e17060SPaolo Bonzini if (~field & (1 << i) && !found) { 19031e17060SPaolo Bonzini DB_PRINT("selecting slave %d\n", i); 19131e17060SPaolo Bonzini qemu_set_irq(s->cs_lines[cs_to_set], 0); 19231e17060SPaolo Bonzini } else { 19331e17060SPaolo Bonzini qemu_set_irq(s->cs_lines[cs_to_set], 1); 19431e17060SPaolo Bonzini } 19531e17060SPaolo Bonzini } 19631e17060SPaolo Bonzini if (~field & (1 << i)) { 19731e17060SPaolo Bonzini found = true; 19831e17060SPaolo Bonzini } 19931e17060SPaolo Bonzini } 20031e17060SPaolo Bonzini if (!found) { 20131e17060SPaolo Bonzini s->snoop_state = SNOOP_CHECKING; 20231e17060SPaolo Bonzini } 20331e17060SPaolo Bonzini } 20431e17060SPaolo Bonzini 20531e17060SPaolo Bonzini static void xilinx_spips_update_ixr(XilinxSPIPS *s) 20631e17060SPaolo Bonzini { 20731e17060SPaolo Bonzini /* These are set/cleared as they occur */ 20831e17060SPaolo Bonzini s->regs[R_INTR_STATUS] &= (IXR_TX_FIFO_UNDERFLOW | IXR_RX_FIFO_OVERFLOW | 20931e17060SPaolo Bonzini IXR_TX_FIFO_MODE_FAIL); 21031e17060SPaolo Bonzini /* these are pure functions of fifo state, set them here */ 21131e17060SPaolo Bonzini s->regs[R_INTR_STATUS] |= 21231e17060SPaolo Bonzini (fifo8_is_full(&s->rx_fifo) ? IXR_RX_FIFO_FULL : 0) | 21331e17060SPaolo Bonzini (s->rx_fifo.num >= s->regs[R_RX_THRES] ? IXR_RX_FIFO_NOT_EMPTY : 0) | 21431e17060SPaolo Bonzini (fifo8_is_full(&s->tx_fifo) ? IXR_TX_FIFO_FULL : 0) | 21531e17060SPaolo Bonzini (s->tx_fifo.num < s->regs[R_TX_THRES] ? IXR_TX_FIFO_NOT_FULL : 0); 21631e17060SPaolo Bonzini /* drive external interrupt pin */ 21731e17060SPaolo Bonzini int new_irqline = !!(s->regs[R_INTR_MASK] & s->regs[R_INTR_STATUS] & 21831e17060SPaolo Bonzini IXR_ALL); 21931e17060SPaolo Bonzini if (new_irqline != s->irqline) { 22031e17060SPaolo Bonzini s->irqline = new_irqline; 22131e17060SPaolo Bonzini qemu_set_irq(s->irq, s->irqline); 22231e17060SPaolo Bonzini } 22331e17060SPaolo Bonzini } 22431e17060SPaolo Bonzini 22531e17060SPaolo Bonzini static void xilinx_spips_reset(DeviceState *d) 22631e17060SPaolo Bonzini { 22731e17060SPaolo Bonzini XilinxSPIPS *s = XILINX_SPIPS(d); 22831e17060SPaolo Bonzini 22931e17060SPaolo Bonzini int i; 23031e17060SPaolo Bonzini for (i = 0; i < R_MAX; i++) { 23131e17060SPaolo Bonzini s->regs[i] = 0; 23231e17060SPaolo Bonzini } 23331e17060SPaolo Bonzini 23431e17060SPaolo Bonzini fifo8_reset(&s->rx_fifo); 23531e17060SPaolo Bonzini fifo8_reset(&s->rx_fifo); 23631e17060SPaolo Bonzini /* non zero resets */ 23731e17060SPaolo Bonzini s->regs[R_CONFIG] |= MODEFAIL_GEN_EN; 23831e17060SPaolo Bonzini s->regs[R_SLAVE_IDLE_COUNT] = 0xFF; 23931e17060SPaolo Bonzini s->regs[R_TX_THRES] = 1; 24031e17060SPaolo Bonzini s->regs[R_RX_THRES] = 1; 24131e17060SPaolo Bonzini /* FIXME: move magic number definition somewhere sensible */ 24231e17060SPaolo Bonzini s->regs[R_MOD_ID] = 0x01090106; 24331e17060SPaolo Bonzini s->regs[R_LQSPI_CFG] = R_LQSPI_CFG_RESET; 24431e17060SPaolo Bonzini s->snoop_state = SNOOP_CHECKING; 24531e17060SPaolo Bonzini xilinx_spips_update_ixr(s); 24631e17060SPaolo Bonzini xilinx_spips_update_cs_lines(s); 24731e17060SPaolo Bonzini } 24831e17060SPaolo Bonzini 24931e17060SPaolo Bonzini static void xilinx_spips_flush_txfifo(XilinxSPIPS *s) 25031e17060SPaolo Bonzini { 25131e17060SPaolo Bonzini for (;;) { 25231e17060SPaolo Bonzini int i; 25331e17060SPaolo Bonzini uint8_t rx; 25431e17060SPaolo Bonzini uint8_t tx = 0; 25531e17060SPaolo Bonzini 25631e17060SPaolo Bonzini for (i = 0; i < num_effective_busses(s); ++i) { 25731e17060SPaolo Bonzini if (!i || s->snoop_state == SNOOP_STRIPING) { 25831e17060SPaolo Bonzini if (fifo8_is_empty(&s->tx_fifo)) { 25931e17060SPaolo Bonzini s->regs[R_INTR_STATUS] |= IXR_TX_FIFO_UNDERFLOW; 26031e17060SPaolo Bonzini xilinx_spips_update_ixr(s); 26131e17060SPaolo Bonzini return; 26231e17060SPaolo Bonzini } else { 26331e17060SPaolo Bonzini tx = fifo8_pop(&s->tx_fifo); 26431e17060SPaolo Bonzini } 26531e17060SPaolo Bonzini } 26631e17060SPaolo Bonzini rx = ssi_transfer(s->spi[i], (uint32_t)tx); 26731e17060SPaolo Bonzini DB_PRINT("tx = %02x rx = %02x\n", tx, rx); 26831e17060SPaolo Bonzini if (!i || s->snoop_state == SNOOP_STRIPING) { 26931e17060SPaolo Bonzini if (fifo8_is_full(&s->rx_fifo)) { 27031e17060SPaolo Bonzini s->regs[R_INTR_STATUS] |= IXR_RX_FIFO_OVERFLOW; 27131e17060SPaolo Bonzini DB_PRINT("rx FIFO overflow"); 27231e17060SPaolo Bonzini } else { 27331e17060SPaolo Bonzini fifo8_push(&s->rx_fifo, (uint8_t)rx); 27431e17060SPaolo Bonzini } 27531e17060SPaolo Bonzini } 27631e17060SPaolo Bonzini } 27731e17060SPaolo Bonzini 27831e17060SPaolo Bonzini switch (s->snoop_state) { 27931e17060SPaolo Bonzini case (SNOOP_CHECKING): 28031e17060SPaolo Bonzini switch (tx) { /* new instruction code */ 28131e17060SPaolo Bonzini case READ: /* 3 address bytes, no dummy bytes/cycles */ 28231e17060SPaolo Bonzini case PP: 28331e17060SPaolo Bonzini case DPP: 28431e17060SPaolo Bonzini case QPP: 28531e17060SPaolo Bonzini s->snoop_state = 3; 28631e17060SPaolo Bonzini break; 28731e17060SPaolo Bonzini case FAST_READ: /* 3 address bytes, 1 dummy byte */ 28831e17060SPaolo Bonzini case DOR: 28931e17060SPaolo Bonzini case QOR: 29031e17060SPaolo Bonzini case DIOR: /* FIXME: these vary between vendor - set to spansion */ 29131e17060SPaolo Bonzini s->snoop_state = 4; 29231e17060SPaolo Bonzini break; 29331e17060SPaolo Bonzini case QIOR: /* 3 address bytes, 2 dummy bytes */ 29431e17060SPaolo Bonzini s->snoop_state = 6; 29531e17060SPaolo Bonzini break; 29631e17060SPaolo Bonzini default: 29731e17060SPaolo Bonzini s->snoop_state = SNOOP_NONE; 29831e17060SPaolo Bonzini } 29931e17060SPaolo Bonzini break; 30031e17060SPaolo Bonzini case (SNOOP_STRIPING): 30131e17060SPaolo Bonzini case (SNOOP_NONE): 30231e17060SPaolo Bonzini break; 30331e17060SPaolo Bonzini default: 30431e17060SPaolo Bonzini s->snoop_state--; 30531e17060SPaolo Bonzini } 30631e17060SPaolo Bonzini } 30731e17060SPaolo Bonzini } 30831e17060SPaolo Bonzini 30931e17060SPaolo Bonzini static inline void rx_data_bytes(XilinxSPIPS *s, uint32_t *value, int max) 31031e17060SPaolo Bonzini { 31131e17060SPaolo Bonzini int i; 31231e17060SPaolo Bonzini 31331e17060SPaolo Bonzini *value = 0; 31431e17060SPaolo Bonzini for (i = 0; i < max && !fifo8_is_empty(&s->rx_fifo); ++i) { 31531e17060SPaolo Bonzini uint32_t next = fifo8_pop(&s->rx_fifo) & 0xFF; 31631e17060SPaolo Bonzini *value |= next << 8 * (s->regs[R_CONFIG] & ENDIAN ? 3-i : i); 31731e17060SPaolo Bonzini } 31831e17060SPaolo Bonzini } 31931e17060SPaolo Bonzini 32031e17060SPaolo Bonzini static uint64_t xilinx_spips_read(void *opaque, hwaddr addr, 32131e17060SPaolo Bonzini unsigned size) 32231e17060SPaolo Bonzini { 32331e17060SPaolo Bonzini XilinxSPIPS *s = opaque; 32431e17060SPaolo Bonzini uint32_t mask = ~0; 32531e17060SPaolo Bonzini uint32_t ret; 32631e17060SPaolo Bonzini 32731e17060SPaolo Bonzini addr >>= 2; 32831e17060SPaolo Bonzini switch (addr) { 32931e17060SPaolo Bonzini case R_CONFIG: 33031e17060SPaolo Bonzini mask = 0x0002FFFF; 33131e17060SPaolo Bonzini break; 33231e17060SPaolo Bonzini case R_INTR_STATUS: 33331e17060SPaolo Bonzini case R_INTR_MASK: 33431e17060SPaolo Bonzini mask = IXR_ALL; 33531e17060SPaolo Bonzini break; 33631e17060SPaolo Bonzini case R_EN: 33731e17060SPaolo Bonzini mask = 0x1; 33831e17060SPaolo Bonzini break; 33931e17060SPaolo Bonzini case R_SLAVE_IDLE_COUNT: 34031e17060SPaolo Bonzini mask = 0xFF; 34131e17060SPaolo Bonzini break; 34231e17060SPaolo Bonzini case R_MOD_ID: 34331e17060SPaolo Bonzini mask = 0x01FFFFFF; 34431e17060SPaolo Bonzini break; 34531e17060SPaolo Bonzini case R_INTR_EN: 34631e17060SPaolo Bonzini case R_INTR_DIS: 34731e17060SPaolo Bonzini case R_TX_DATA: 34831e17060SPaolo Bonzini mask = 0; 34931e17060SPaolo Bonzini break; 35031e17060SPaolo Bonzini case R_RX_DATA: 35131e17060SPaolo Bonzini rx_data_bytes(s, &ret, s->num_txrx_bytes); 35231e17060SPaolo Bonzini DB_PRINT("addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret); 35331e17060SPaolo Bonzini xilinx_spips_update_ixr(s); 35431e17060SPaolo Bonzini return ret; 35531e17060SPaolo Bonzini } 35631e17060SPaolo Bonzini DB_PRINT("addr=" TARGET_FMT_plx " = %x\n", addr * 4, s->regs[addr] & mask); 35731e17060SPaolo Bonzini return s->regs[addr] & mask; 35831e17060SPaolo Bonzini 35931e17060SPaolo Bonzini } 36031e17060SPaolo Bonzini 36131e17060SPaolo Bonzini static inline void tx_data_bytes(XilinxSPIPS *s, uint32_t value, int num) 36231e17060SPaolo Bonzini { 36331e17060SPaolo Bonzini int i; 36431e17060SPaolo Bonzini for (i = 0; i < num && !fifo8_is_full(&s->tx_fifo); ++i) { 36531e17060SPaolo Bonzini if (s->regs[R_CONFIG] & ENDIAN) { 36631e17060SPaolo Bonzini fifo8_push(&s->tx_fifo, (uint8_t)(value >> 24)); 36731e17060SPaolo Bonzini value <<= 8; 36831e17060SPaolo Bonzini } else { 36931e17060SPaolo Bonzini fifo8_push(&s->tx_fifo, (uint8_t)value); 37031e17060SPaolo Bonzini value >>= 8; 37131e17060SPaolo Bonzini } 37231e17060SPaolo Bonzini } 37331e17060SPaolo Bonzini } 37431e17060SPaolo Bonzini 37531e17060SPaolo Bonzini static void xilinx_spips_write(void *opaque, hwaddr addr, 37631e17060SPaolo Bonzini uint64_t value, unsigned size) 37731e17060SPaolo Bonzini { 37831e17060SPaolo Bonzini int mask = ~0; 37931e17060SPaolo Bonzini int man_start_com = 0; 38031e17060SPaolo Bonzini XilinxSPIPS *s = opaque; 38131e17060SPaolo Bonzini 38231e17060SPaolo Bonzini DB_PRINT("addr=" TARGET_FMT_plx " = %x\n", addr, (unsigned)value); 38331e17060SPaolo Bonzini addr >>= 2; 38431e17060SPaolo Bonzini switch (addr) { 38531e17060SPaolo Bonzini case R_CONFIG: 38631e17060SPaolo Bonzini mask = 0x0002FFFF; 38731e17060SPaolo Bonzini if (value & MAN_START_COM) { 38831e17060SPaolo Bonzini man_start_com = 1; 38931e17060SPaolo Bonzini } 39031e17060SPaolo Bonzini break; 39131e17060SPaolo Bonzini case R_INTR_STATUS: 39231e17060SPaolo Bonzini mask = IXR_ALL; 39331e17060SPaolo Bonzini s->regs[R_INTR_STATUS] &= ~(mask & value); 39431e17060SPaolo Bonzini goto no_reg_update; 39531e17060SPaolo Bonzini case R_INTR_DIS: 39631e17060SPaolo Bonzini mask = IXR_ALL; 39731e17060SPaolo Bonzini s->regs[R_INTR_MASK] &= ~(mask & value); 39831e17060SPaolo Bonzini goto no_reg_update; 39931e17060SPaolo Bonzini case R_INTR_EN: 40031e17060SPaolo Bonzini mask = IXR_ALL; 40131e17060SPaolo Bonzini s->regs[R_INTR_MASK] |= mask & value; 40231e17060SPaolo Bonzini goto no_reg_update; 40331e17060SPaolo Bonzini case R_EN: 40431e17060SPaolo Bonzini mask = 0x1; 40531e17060SPaolo Bonzini break; 40631e17060SPaolo Bonzini case R_SLAVE_IDLE_COUNT: 40731e17060SPaolo Bonzini mask = 0xFF; 40831e17060SPaolo Bonzini break; 40931e17060SPaolo Bonzini case R_RX_DATA: 41031e17060SPaolo Bonzini case R_INTR_MASK: 41131e17060SPaolo Bonzini case R_MOD_ID: 41231e17060SPaolo Bonzini mask = 0; 41331e17060SPaolo Bonzini break; 41431e17060SPaolo Bonzini case R_TX_DATA: 41531e17060SPaolo Bonzini tx_data_bytes(s, (uint32_t)value, s->num_txrx_bytes); 41631e17060SPaolo Bonzini goto no_reg_update; 41731e17060SPaolo Bonzini case R_TXD1: 41831e17060SPaolo Bonzini tx_data_bytes(s, (uint32_t)value, 1); 41931e17060SPaolo Bonzini goto no_reg_update; 42031e17060SPaolo Bonzini case R_TXD2: 42131e17060SPaolo Bonzini tx_data_bytes(s, (uint32_t)value, 2); 42231e17060SPaolo Bonzini goto no_reg_update; 42331e17060SPaolo Bonzini case R_TXD3: 42431e17060SPaolo Bonzini tx_data_bytes(s, (uint32_t)value, 3); 42531e17060SPaolo Bonzini goto no_reg_update; 42631e17060SPaolo Bonzini } 42731e17060SPaolo Bonzini s->regs[addr] = (s->regs[addr] & ~mask) | (value & mask); 42831e17060SPaolo Bonzini no_reg_update: 42931e17060SPaolo Bonzini if (man_start_com) { 43031e17060SPaolo Bonzini xilinx_spips_flush_txfifo(s); 43131e17060SPaolo Bonzini } 43231e17060SPaolo Bonzini xilinx_spips_update_ixr(s); 43331e17060SPaolo Bonzini xilinx_spips_update_cs_lines(s); 43431e17060SPaolo Bonzini } 43531e17060SPaolo Bonzini 43631e17060SPaolo Bonzini static const MemoryRegionOps spips_ops = { 43731e17060SPaolo Bonzini .read = xilinx_spips_read, 43831e17060SPaolo Bonzini .write = xilinx_spips_write, 43931e17060SPaolo Bonzini .endianness = DEVICE_LITTLE_ENDIAN, 44031e17060SPaolo Bonzini }; 44131e17060SPaolo Bonzini 44231e17060SPaolo Bonzini #define LQSPI_CACHE_SIZE 1024 44331e17060SPaolo Bonzini 44431e17060SPaolo Bonzini static uint64_t 44531e17060SPaolo Bonzini lqspi_read(void *opaque, hwaddr addr, unsigned int size) 44631e17060SPaolo Bonzini { 44731e17060SPaolo Bonzini int i; 448*6b91f015SPeter Crosthwaite XilinxQSPIPS *q = opaque; 44931e17060SPaolo Bonzini XilinxSPIPS *s = opaque; 45031e17060SPaolo Bonzini 451*6b91f015SPeter Crosthwaite if (addr >= q->lqspi_cached_addr && 452*6b91f015SPeter Crosthwaite addr <= q->lqspi_cached_addr + LQSPI_CACHE_SIZE - 4) { 453*6b91f015SPeter Crosthwaite return q->lqspi_buf[(addr - q->lqspi_cached_addr) >> 2]; 45431e17060SPaolo Bonzini } else { 45531e17060SPaolo Bonzini int flash_addr = (addr / num_effective_busses(s)); 45631e17060SPaolo Bonzini int slave = flash_addr >> LQSPI_ADDRESS_BITS; 45731e17060SPaolo Bonzini int cache_entry = 0; 45831e17060SPaolo Bonzini 45931e17060SPaolo Bonzini DB_PRINT("config reg status: %08x\n", s->regs[R_LQSPI_CFG]); 46031e17060SPaolo Bonzini 46131e17060SPaolo Bonzini fifo8_reset(&s->tx_fifo); 46231e17060SPaolo Bonzini fifo8_reset(&s->rx_fifo); 46331e17060SPaolo Bonzini 46431e17060SPaolo Bonzini s->regs[R_CONFIG] &= ~CS; 46531e17060SPaolo Bonzini s->regs[R_CONFIG] |= (~(1 << slave) << CS_SHIFT) & CS; 46631e17060SPaolo Bonzini xilinx_spips_update_cs_lines(s); 46731e17060SPaolo Bonzini 46831e17060SPaolo Bonzini /* instruction */ 46931e17060SPaolo Bonzini DB_PRINT("pushing read instruction: %02x\n", 47031e17060SPaolo Bonzini (uint8_t)(s->regs[R_LQSPI_CFG] & LQSPI_CFG_INST_CODE)); 47131e17060SPaolo Bonzini fifo8_push(&s->tx_fifo, s->regs[R_LQSPI_CFG] & LQSPI_CFG_INST_CODE); 47231e17060SPaolo Bonzini /* read address */ 47331e17060SPaolo Bonzini DB_PRINT("pushing read address %06x\n", flash_addr); 47431e17060SPaolo Bonzini fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 16)); 47531e17060SPaolo Bonzini fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 8)); 47631e17060SPaolo Bonzini fifo8_push(&s->tx_fifo, (uint8_t)flash_addr); 47731e17060SPaolo Bonzini /* mode bits */ 47831e17060SPaolo Bonzini if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_MODE_EN) { 47931e17060SPaolo Bonzini fifo8_push(&s->tx_fifo, extract32(s->regs[R_LQSPI_CFG], 48031e17060SPaolo Bonzini LQSPI_CFG_MODE_SHIFT, 48131e17060SPaolo Bonzini LQSPI_CFG_MODE_WIDTH)); 48231e17060SPaolo Bonzini } 48331e17060SPaolo Bonzini /* dummy bytes */ 48431e17060SPaolo Bonzini for (i = 0; i < (extract32(s->regs[R_LQSPI_CFG], LQSPI_CFG_DUMMY_SHIFT, 48531e17060SPaolo Bonzini LQSPI_CFG_DUMMY_WIDTH)); ++i) { 48631e17060SPaolo Bonzini DB_PRINT("pushing dummy byte\n"); 48731e17060SPaolo Bonzini fifo8_push(&s->tx_fifo, 0); 48831e17060SPaolo Bonzini } 48931e17060SPaolo Bonzini xilinx_spips_flush_txfifo(s); 49031e17060SPaolo Bonzini fifo8_reset(&s->rx_fifo); 49131e17060SPaolo Bonzini 49231e17060SPaolo Bonzini DB_PRINT("starting QSPI data read\n"); 49331e17060SPaolo Bonzini 49431e17060SPaolo Bonzini for (i = 0; i < LQSPI_CACHE_SIZE / 4; ++i) { 49531e17060SPaolo Bonzini tx_data_bytes(s, 0, 4); 49631e17060SPaolo Bonzini xilinx_spips_flush_txfifo(s); 497*6b91f015SPeter Crosthwaite rx_data_bytes(s, &q->lqspi_buf[cache_entry], 4); 49831e17060SPaolo Bonzini cache_entry++; 49931e17060SPaolo Bonzini } 50031e17060SPaolo Bonzini 50131e17060SPaolo Bonzini s->regs[R_CONFIG] |= CS; 50231e17060SPaolo Bonzini xilinx_spips_update_cs_lines(s); 50331e17060SPaolo Bonzini 504*6b91f015SPeter Crosthwaite q->lqspi_cached_addr = addr; 50531e17060SPaolo Bonzini return lqspi_read(opaque, addr, size); 50631e17060SPaolo Bonzini } 50731e17060SPaolo Bonzini } 50831e17060SPaolo Bonzini 50931e17060SPaolo Bonzini static const MemoryRegionOps lqspi_ops = { 51031e17060SPaolo Bonzini .read = lqspi_read, 51131e17060SPaolo Bonzini .endianness = DEVICE_NATIVE_ENDIAN, 51231e17060SPaolo Bonzini .valid = { 51331e17060SPaolo Bonzini .min_access_size = 4, 51431e17060SPaolo Bonzini .max_access_size = 4 51531e17060SPaolo Bonzini } 51631e17060SPaolo Bonzini }; 51731e17060SPaolo Bonzini 51831e17060SPaolo Bonzini static void xilinx_spips_realize(DeviceState *dev, Error **errp) 51931e17060SPaolo Bonzini { 52031e17060SPaolo Bonzini XilinxSPIPS *s = XILINX_SPIPS(dev); 52131e17060SPaolo Bonzini SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 52231e17060SPaolo Bonzini int i; 52331e17060SPaolo Bonzini 524*6b91f015SPeter Crosthwaite DB_PRINT("realized spips\n"); 52531e17060SPaolo Bonzini 52631e17060SPaolo Bonzini s->spi = g_new(SSIBus *, s->num_busses); 52731e17060SPaolo Bonzini for (i = 0; i < s->num_busses; ++i) { 52831e17060SPaolo Bonzini char bus_name[16]; 52931e17060SPaolo Bonzini snprintf(bus_name, 16, "spi%d", i); 53031e17060SPaolo Bonzini s->spi[i] = ssi_create_bus(dev, bus_name); 53131e17060SPaolo Bonzini } 53231e17060SPaolo Bonzini 53331e17060SPaolo Bonzini s->cs_lines = g_new0(qemu_irq, s->num_cs * s->num_busses); 53431e17060SPaolo Bonzini ssi_auto_connect_slaves(DEVICE(s), s->cs_lines, s->spi[0]); 53531e17060SPaolo Bonzini ssi_auto_connect_slaves(DEVICE(s), s->cs_lines, s->spi[1]); 53631e17060SPaolo Bonzini sysbus_init_irq(sbd, &s->irq); 53731e17060SPaolo Bonzini for (i = 0; i < s->num_cs * s->num_busses; ++i) { 53831e17060SPaolo Bonzini sysbus_init_irq(sbd, &s->cs_lines[i]); 53931e17060SPaolo Bonzini } 54031e17060SPaolo Bonzini 54131e17060SPaolo Bonzini memory_region_init_io(&s->iomem, &spips_ops, s, "spi", R_MAX*4); 54231e17060SPaolo Bonzini sysbus_init_mmio(sbd, &s->iomem); 54331e17060SPaolo Bonzini 544*6b91f015SPeter Crosthwaite s->irqline = -1; 545*6b91f015SPeter Crosthwaite 546*6b91f015SPeter Crosthwaite fifo8_create(&s->rx_fifo, RXFF_A); 547*6b91f015SPeter Crosthwaite fifo8_create(&s->tx_fifo, TXFF_A); 548*6b91f015SPeter Crosthwaite } 549*6b91f015SPeter Crosthwaite 550*6b91f015SPeter Crosthwaite static void xilinx_qspips_realize(DeviceState *dev, Error **errp) 551*6b91f015SPeter Crosthwaite { 552*6b91f015SPeter Crosthwaite XilinxSPIPS *s = XILINX_SPIPS(dev); 553*6b91f015SPeter Crosthwaite XilinxQSPIPS *q = XILINX_QSPIPS(dev); 554*6b91f015SPeter Crosthwaite SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 555*6b91f015SPeter Crosthwaite 556*6b91f015SPeter Crosthwaite DB_PRINT("realized qspips\n"); 557*6b91f015SPeter Crosthwaite 558*6b91f015SPeter Crosthwaite s->num_busses = 2; 559*6b91f015SPeter Crosthwaite s->num_cs = 2; 560*6b91f015SPeter Crosthwaite s->num_txrx_bytes = 4; 561*6b91f015SPeter Crosthwaite 562*6b91f015SPeter Crosthwaite xilinx_spips_realize(dev, errp); 56331e17060SPaolo Bonzini memory_region_init_io(&s->mmlqspi, &lqspi_ops, s, "lqspi", 56431e17060SPaolo Bonzini (1 << LQSPI_ADDRESS_BITS) * 2); 56531e17060SPaolo Bonzini sysbus_init_mmio(sbd, &s->mmlqspi); 56631e17060SPaolo Bonzini 567*6b91f015SPeter Crosthwaite q->lqspi_cached_addr = ~0ULL; 56831e17060SPaolo Bonzini } 56931e17060SPaolo Bonzini 57031e17060SPaolo Bonzini static int xilinx_spips_post_load(void *opaque, int version_id) 57131e17060SPaolo Bonzini { 57231e17060SPaolo Bonzini xilinx_spips_update_ixr((XilinxSPIPS *)opaque); 57331e17060SPaolo Bonzini xilinx_spips_update_cs_lines((XilinxSPIPS *)opaque); 57431e17060SPaolo Bonzini return 0; 57531e17060SPaolo Bonzini } 57631e17060SPaolo Bonzini 57731e17060SPaolo Bonzini static const VMStateDescription vmstate_xilinx_spips = { 57831e17060SPaolo Bonzini .name = "xilinx_spips", 57931e17060SPaolo Bonzini .version_id = 2, 58031e17060SPaolo Bonzini .minimum_version_id = 2, 58131e17060SPaolo Bonzini .minimum_version_id_old = 2, 58231e17060SPaolo Bonzini .post_load = xilinx_spips_post_load, 58331e17060SPaolo Bonzini .fields = (VMStateField[]) { 58431e17060SPaolo Bonzini VMSTATE_FIFO8(tx_fifo, XilinxSPIPS), 58531e17060SPaolo Bonzini VMSTATE_FIFO8(rx_fifo, XilinxSPIPS), 58631e17060SPaolo Bonzini VMSTATE_UINT32_ARRAY(regs, XilinxSPIPS, R_MAX), 58731e17060SPaolo Bonzini VMSTATE_UINT8(snoop_state, XilinxSPIPS), 58831e17060SPaolo Bonzini VMSTATE_END_OF_LIST() 58931e17060SPaolo Bonzini } 59031e17060SPaolo Bonzini }; 59131e17060SPaolo Bonzini 59231e17060SPaolo Bonzini static Property xilinx_spips_properties[] = { 59331e17060SPaolo Bonzini DEFINE_PROP_UINT8("num-busses", XilinxSPIPS, num_busses, 1), 59431e17060SPaolo Bonzini DEFINE_PROP_UINT8("num-ss-bits", XilinxSPIPS, num_cs, 4), 59531e17060SPaolo Bonzini DEFINE_PROP_UINT8("num-txrx-bytes", XilinxSPIPS, num_txrx_bytes, 1), 59631e17060SPaolo Bonzini DEFINE_PROP_END_OF_LIST(), 59731e17060SPaolo Bonzini }; 598*6b91f015SPeter Crosthwaite 599*6b91f015SPeter Crosthwaite static void xilinx_qspips_class_init(ObjectClass *klass, void * data) 600*6b91f015SPeter Crosthwaite { 601*6b91f015SPeter Crosthwaite DeviceClass *dc = DEVICE_CLASS(klass); 602*6b91f015SPeter Crosthwaite 603*6b91f015SPeter Crosthwaite dc->realize = xilinx_qspips_realize; 604*6b91f015SPeter Crosthwaite } 605*6b91f015SPeter Crosthwaite 60631e17060SPaolo Bonzini static void xilinx_spips_class_init(ObjectClass *klass, void *data) 60731e17060SPaolo Bonzini { 60831e17060SPaolo Bonzini DeviceClass *dc = DEVICE_CLASS(klass); 60931e17060SPaolo Bonzini 61031e17060SPaolo Bonzini dc->realize = xilinx_spips_realize; 61131e17060SPaolo Bonzini dc->reset = xilinx_spips_reset; 61231e17060SPaolo Bonzini dc->props = xilinx_spips_properties; 61331e17060SPaolo Bonzini dc->vmsd = &vmstate_xilinx_spips; 61431e17060SPaolo Bonzini } 61531e17060SPaolo Bonzini 61631e17060SPaolo Bonzini static const TypeInfo xilinx_spips_info = { 61731e17060SPaolo Bonzini .name = TYPE_XILINX_SPIPS, 61831e17060SPaolo Bonzini .parent = TYPE_SYS_BUS_DEVICE, 61931e17060SPaolo Bonzini .instance_size = sizeof(XilinxSPIPS), 62031e17060SPaolo Bonzini .class_init = xilinx_spips_class_init, 62131e17060SPaolo Bonzini }; 62231e17060SPaolo Bonzini 623*6b91f015SPeter Crosthwaite static const TypeInfo xilinx_qspips_info = { 624*6b91f015SPeter Crosthwaite .name = TYPE_XILINX_QSPIPS, 625*6b91f015SPeter Crosthwaite .parent = TYPE_XILINX_SPIPS, 626*6b91f015SPeter Crosthwaite .instance_size = sizeof(XilinxQSPIPS), 627*6b91f015SPeter Crosthwaite .class_init = xilinx_qspips_class_init, 628*6b91f015SPeter Crosthwaite }; 629*6b91f015SPeter Crosthwaite 63031e17060SPaolo Bonzini static void xilinx_spips_register_types(void) 63131e17060SPaolo Bonzini { 63231e17060SPaolo Bonzini type_register_static(&xilinx_spips_info); 633*6b91f015SPeter Crosthwaite type_register_static(&xilinx_qspips_info); 63431e17060SPaolo Bonzini } 63531e17060SPaolo Bonzini 63631e17060SPaolo Bonzini type_init(xilinx_spips_register_types) 637