131e17060SPaolo Bonzini /* 231e17060SPaolo Bonzini * QEMU model of the Xilinx Zynq SPI controller 331e17060SPaolo Bonzini * 431e17060SPaolo Bonzini * Copyright (c) 2012 Peter A. G. Crosthwaite 531e17060SPaolo Bonzini * 631e17060SPaolo Bonzini * Permission is hereby granted, free of charge, to any person obtaining a copy 731e17060SPaolo Bonzini * of this software and associated documentation files (the "Software"), to deal 831e17060SPaolo Bonzini * in the Software without restriction, including without limitation the rights 931e17060SPaolo Bonzini * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 1031e17060SPaolo Bonzini * copies of the Software, and to permit persons to whom the Software is 1131e17060SPaolo Bonzini * furnished to do so, subject to the following conditions: 1231e17060SPaolo Bonzini * 1331e17060SPaolo Bonzini * The above copyright notice and this permission notice shall be included in 1431e17060SPaolo Bonzini * all copies or substantial portions of the Software. 1531e17060SPaolo Bonzini * 1631e17060SPaolo Bonzini * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1731e17060SPaolo Bonzini * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1831e17060SPaolo Bonzini * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 1931e17060SPaolo Bonzini * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 2031e17060SPaolo Bonzini * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 2131e17060SPaolo Bonzini * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 2231e17060SPaolo Bonzini * THE SOFTWARE. 2331e17060SPaolo Bonzini */ 2431e17060SPaolo Bonzini 2531e17060SPaolo Bonzini #include "hw/sysbus.h" 2631e17060SPaolo Bonzini #include "sysemu/sysemu.h" 2731e17060SPaolo Bonzini #include "hw/ptimer.h" 2831e17060SPaolo Bonzini #include "qemu/log.h" 2931e17060SPaolo Bonzini #include "qemu/fifo8.h" 308fd06719SAlistair Francis #include "hw/ssi/ssi.h" 3131e17060SPaolo Bonzini #include "qemu/bitops.h" 32*6363235bSAlistair Francis #include "hw/ssi/xilinx_spips.h" 3331e17060SPaolo Bonzini 344a5b6fa8SPeter Crosthwaite #ifndef XILINX_SPIPS_ERR_DEBUG 354a5b6fa8SPeter Crosthwaite #define XILINX_SPIPS_ERR_DEBUG 0 364a5b6fa8SPeter Crosthwaite #endif 374a5b6fa8SPeter Crosthwaite 384a5b6fa8SPeter Crosthwaite #define DB_PRINT_L(level, ...) do { \ 394a5b6fa8SPeter Crosthwaite if (XILINX_SPIPS_ERR_DEBUG > (level)) { \ 4031e17060SPaolo Bonzini fprintf(stderr, ": %s: ", __func__); \ 4131e17060SPaolo Bonzini fprintf(stderr, ## __VA_ARGS__); \ 424a5b6fa8SPeter Crosthwaite } \ 4331e17060SPaolo Bonzini } while (0); 4431e17060SPaolo Bonzini 4531e17060SPaolo Bonzini /* config register */ 4631e17060SPaolo Bonzini #define R_CONFIG (0x00 / 4) 47c8f8f9fbSPeter Maydell #define IFMODE (1U << 31) 4831e17060SPaolo Bonzini #define ENDIAN (1 << 26) 4931e17060SPaolo Bonzini #define MODEFAIL_GEN_EN (1 << 17) 5031e17060SPaolo Bonzini #define MAN_START_COM (1 << 16) 5131e17060SPaolo Bonzini #define MAN_START_EN (1 << 15) 5231e17060SPaolo Bonzini #define MANUAL_CS (1 << 14) 5331e17060SPaolo Bonzini #define CS (0xF << 10) 5431e17060SPaolo Bonzini #define CS_SHIFT (10) 5531e17060SPaolo Bonzini #define PERI_SEL (1 << 9) 5631e17060SPaolo Bonzini #define REF_CLK (1 << 8) 5731e17060SPaolo Bonzini #define FIFO_WIDTH (3 << 6) 5831e17060SPaolo Bonzini #define BAUD_RATE_DIV (7 << 3) 5931e17060SPaolo Bonzini #define CLK_PH (1 << 2) 6031e17060SPaolo Bonzini #define CLK_POL (1 << 1) 6131e17060SPaolo Bonzini #define MODE_SEL (1 << 0) 622133a5f6SPeter Crosthwaite #define R_CONFIG_RSVD (0x7bf40000) 6331e17060SPaolo Bonzini 6431e17060SPaolo Bonzini /* interrupt mechanism */ 6531e17060SPaolo Bonzini #define R_INTR_STATUS (0x04 / 4) 6631e17060SPaolo Bonzini #define R_INTR_EN (0x08 / 4) 6731e17060SPaolo Bonzini #define R_INTR_DIS (0x0C / 4) 6831e17060SPaolo Bonzini #define R_INTR_MASK (0x10 / 4) 6931e17060SPaolo Bonzini #define IXR_TX_FIFO_UNDERFLOW (1 << 6) 7031e17060SPaolo Bonzini #define IXR_RX_FIFO_FULL (1 << 5) 7131e17060SPaolo Bonzini #define IXR_RX_FIFO_NOT_EMPTY (1 << 4) 7231e17060SPaolo Bonzini #define IXR_TX_FIFO_FULL (1 << 3) 7331e17060SPaolo Bonzini #define IXR_TX_FIFO_NOT_FULL (1 << 2) 7431e17060SPaolo Bonzini #define IXR_TX_FIFO_MODE_FAIL (1 << 1) 7531e17060SPaolo Bonzini #define IXR_RX_FIFO_OVERFLOW (1 << 0) 7631e17060SPaolo Bonzini #define IXR_ALL ((IXR_TX_FIFO_UNDERFLOW<<1)-1) 7731e17060SPaolo Bonzini 7831e17060SPaolo Bonzini #define R_EN (0x14 / 4) 7931e17060SPaolo Bonzini #define R_DELAY (0x18 / 4) 8031e17060SPaolo Bonzini #define R_TX_DATA (0x1C / 4) 8131e17060SPaolo Bonzini #define R_RX_DATA (0x20 / 4) 8231e17060SPaolo Bonzini #define R_SLAVE_IDLE_COUNT (0x24 / 4) 8331e17060SPaolo Bonzini #define R_TX_THRES (0x28 / 4) 8431e17060SPaolo Bonzini #define R_RX_THRES (0x2C / 4) 8531e17060SPaolo Bonzini #define R_TXD1 (0x80 / 4) 8631e17060SPaolo Bonzini #define R_TXD2 (0x84 / 4) 8731e17060SPaolo Bonzini #define R_TXD3 (0x88 / 4) 8831e17060SPaolo Bonzini 8931e17060SPaolo Bonzini #define R_LQSPI_CFG (0xa0 / 4) 9031e17060SPaolo Bonzini #define R_LQSPI_CFG_RESET 0x03A002EB 91c8f8f9fbSPeter Maydell #define LQSPI_CFG_LQ_MODE (1U << 31) 9231e17060SPaolo Bonzini #define LQSPI_CFG_TWO_MEM (1 << 30) 9331e17060SPaolo Bonzini #define LQSPI_CFG_SEP_BUS (1 << 30) 9431e17060SPaolo Bonzini #define LQSPI_CFG_U_PAGE (1 << 28) 9531e17060SPaolo Bonzini #define LQSPI_CFG_MODE_EN (1 << 25) 9631e17060SPaolo Bonzini #define LQSPI_CFG_MODE_WIDTH 8 9731e17060SPaolo Bonzini #define LQSPI_CFG_MODE_SHIFT 16 9831e17060SPaolo Bonzini #define LQSPI_CFG_DUMMY_WIDTH 3 9931e17060SPaolo Bonzini #define LQSPI_CFG_DUMMY_SHIFT 8 10031e17060SPaolo Bonzini #define LQSPI_CFG_INST_CODE 0xFF 10131e17060SPaolo Bonzini 10231e17060SPaolo Bonzini #define R_LQSPI_STS (0xA4 / 4) 10331e17060SPaolo Bonzini #define LQSPI_STS_WR_RECVD (1 << 1) 10431e17060SPaolo Bonzini 10531e17060SPaolo Bonzini #define R_MOD_ID (0xFC / 4) 10631e17060SPaolo Bonzini 10731e17060SPaolo Bonzini /* size of TXRX FIFOs */ 10831e17060SPaolo Bonzini #define RXFF_A 32 10931e17060SPaolo Bonzini #define TXFF_A 32 11031e17060SPaolo Bonzini 11110e60b35SPeter Crosthwaite #define RXFF_A_Q (64 * 4) 11210e60b35SPeter Crosthwaite #define TXFF_A_Q (64 * 4) 11310e60b35SPeter Crosthwaite 11431e17060SPaolo Bonzini /* 16MB per linear region */ 11531e17060SPaolo Bonzini #define LQSPI_ADDRESS_BITS 24 11631e17060SPaolo Bonzini /* Bite off 4k chunks at a time */ 11731e17060SPaolo Bonzini #define LQSPI_CACHE_SIZE 1024 11831e17060SPaolo Bonzini 11931e17060SPaolo Bonzini #define SNOOP_CHECKING 0xFF 12031e17060SPaolo Bonzini #define SNOOP_NONE 0xFE 12131e17060SPaolo Bonzini #define SNOOP_STRIPING 0 12231e17060SPaolo Bonzini 12331e17060SPaolo Bonzini typedef enum { 12431e17060SPaolo Bonzini READ = 0x3, 12531e17060SPaolo Bonzini FAST_READ = 0xb, 12631e17060SPaolo Bonzini DOR = 0x3b, 12731e17060SPaolo Bonzini QOR = 0x6b, 12831e17060SPaolo Bonzini DIOR = 0xbb, 12931e17060SPaolo Bonzini QIOR = 0xeb, 13031e17060SPaolo Bonzini 13131e17060SPaolo Bonzini PP = 0x2, 13231e17060SPaolo Bonzini DPP = 0xa2, 13331e17060SPaolo Bonzini QPP = 0x32, 13431e17060SPaolo Bonzini } FlashCMD; 13531e17060SPaolo Bonzini 13631e17060SPaolo Bonzini typedef struct { 1376b91f015SPeter Crosthwaite XilinxSPIPS parent_obj; 13831e17060SPaolo Bonzini 139b0b7ae62SPeter Crosthwaite uint8_t lqspi_buf[LQSPI_CACHE_SIZE]; 14031e17060SPaolo Bonzini hwaddr lqspi_cached_addr; 1416b91f015SPeter Crosthwaite } XilinxQSPIPS; 14231e17060SPaolo Bonzini 14310e60b35SPeter Crosthwaite typedef struct XilinxSPIPSClass { 14410e60b35SPeter Crosthwaite SysBusDeviceClass parent_class; 14510e60b35SPeter Crosthwaite 146b5cd9143SPeter Crosthwaite const MemoryRegionOps *reg_ops; 147b5cd9143SPeter Crosthwaite 14810e60b35SPeter Crosthwaite uint32_t rx_fifo_size; 14910e60b35SPeter Crosthwaite uint32_t tx_fifo_size; 15010e60b35SPeter Crosthwaite } XilinxSPIPSClass; 1516b91f015SPeter Crosthwaite 15231e17060SPaolo Bonzini static inline int num_effective_busses(XilinxSPIPS *s) 15331e17060SPaolo Bonzini { 15431e17060SPaolo Bonzini return (s->regs[R_LQSPI_CFG] & LQSPI_CFG_SEP_BUS && 15531e17060SPaolo Bonzini s->regs[R_LQSPI_CFG] & LQSPI_CFG_TWO_MEM) ? s->num_busses : 1; 15631e17060SPaolo Bonzini } 15731e17060SPaolo Bonzini 158c4f08ffeSPeter Crosthwaite static inline bool xilinx_spips_cs_is_set(XilinxSPIPS *s, int i, int field) 159c4f08ffeSPeter Crosthwaite { 160c4f08ffeSPeter Crosthwaite return ~field & (1 << i) && (s->regs[R_CONFIG] & MANUAL_CS 161c4f08ffeSPeter Crosthwaite || !fifo8_is_empty(&s->tx_fifo)); 162c4f08ffeSPeter Crosthwaite } 163c4f08ffeSPeter Crosthwaite 16431e17060SPaolo Bonzini static void xilinx_spips_update_cs_lines(XilinxSPIPS *s) 16531e17060SPaolo Bonzini { 16631e17060SPaolo Bonzini int i, j; 16731e17060SPaolo Bonzini bool found = false; 16831e17060SPaolo Bonzini int field = s->regs[R_CONFIG] >> CS_SHIFT; 16931e17060SPaolo Bonzini 17031e17060SPaolo Bonzini for (i = 0; i < s->num_cs; i++) { 17131e17060SPaolo Bonzini for (j = 0; j < num_effective_busses(s); j++) { 17231e17060SPaolo Bonzini int upage = !!(s->regs[R_LQSPI_STS] & LQSPI_CFG_U_PAGE); 17331e17060SPaolo Bonzini int cs_to_set = (j * s->num_cs + i + upage) % 17431e17060SPaolo Bonzini (s->num_cs * s->num_busses); 17531e17060SPaolo Bonzini 176c4f08ffeSPeter Crosthwaite if (xilinx_spips_cs_is_set(s, i, field) && !found) { 1774a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "selecting slave %d\n", i); 17831e17060SPaolo Bonzini qemu_set_irq(s->cs_lines[cs_to_set], 0); 17931e17060SPaolo Bonzini } else { 1804a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "deselecting slave %d\n", i); 18131e17060SPaolo Bonzini qemu_set_irq(s->cs_lines[cs_to_set], 1); 18231e17060SPaolo Bonzini } 18331e17060SPaolo Bonzini } 184c4f08ffeSPeter Crosthwaite if (xilinx_spips_cs_is_set(s, i, field)) { 18531e17060SPaolo Bonzini found = true; 18631e17060SPaolo Bonzini } 18731e17060SPaolo Bonzini } 18831e17060SPaolo Bonzini if (!found) { 18931e17060SPaolo Bonzini s->snoop_state = SNOOP_CHECKING; 1904a5b6fa8SPeter Crosthwaite DB_PRINT_L(1, "moving to snoop check state\n"); 19131e17060SPaolo Bonzini } 19231e17060SPaolo Bonzini } 19331e17060SPaolo Bonzini 19431e17060SPaolo Bonzini static void xilinx_spips_update_ixr(XilinxSPIPS *s) 19531e17060SPaolo Bonzini { 1963ea728d0SPeter Crosthwaite if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_LQ_MODE) { 1973ea728d0SPeter Crosthwaite return; 1983ea728d0SPeter Crosthwaite } 19931e17060SPaolo Bonzini /* These are set/cleared as they occur */ 20031e17060SPaolo Bonzini s->regs[R_INTR_STATUS] &= (IXR_TX_FIFO_UNDERFLOW | IXR_RX_FIFO_OVERFLOW | 20131e17060SPaolo Bonzini IXR_TX_FIFO_MODE_FAIL); 20231e17060SPaolo Bonzini /* these are pure functions of fifo state, set them here */ 20331e17060SPaolo Bonzini s->regs[R_INTR_STATUS] |= 20431e17060SPaolo Bonzini (fifo8_is_full(&s->rx_fifo) ? IXR_RX_FIFO_FULL : 0) | 20531e17060SPaolo Bonzini (s->rx_fifo.num >= s->regs[R_RX_THRES] ? IXR_RX_FIFO_NOT_EMPTY : 0) | 20631e17060SPaolo Bonzini (fifo8_is_full(&s->tx_fifo) ? IXR_TX_FIFO_FULL : 0) | 20731e17060SPaolo Bonzini (s->tx_fifo.num < s->regs[R_TX_THRES] ? IXR_TX_FIFO_NOT_FULL : 0); 20831e17060SPaolo Bonzini /* drive external interrupt pin */ 20931e17060SPaolo Bonzini int new_irqline = !!(s->regs[R_INTR_MASK] & s->regs[R_INTR_STATUS] & 21031e17060SPaolo Bonzini IXR_ALL); 21131e17060SPaolo Bonzini if (new_irqline != s->irqline) { 21231e17060SPaolo Bonzini s->irqline = new_irqline; 21331e17060SPaolo Bonzini qemu_set_irq(s->irq, s->irqline); 21431e17060SPaolo Bonzini } 21531e17060SPaolo Bonzini } 21631e17060SPaolo Bonzini 21731e17060SPaolo Bonzini static void xilinx_spips_reset(DeviceState *d) 21831e17060SPaolo Bonzini { 21931e17060SPaolo Bonzini XilinxSPIPS *s = XILINX_SPIPS(d); 22031e17060SPaolo Bonzini 22131e17060SPaolo Bonzini int i; 222*6363235bSAlistair Francis for (i = 0; i < XLNX_SPIPS_R_MAX; i++) { 22331e17060SPaolo Bonzini s->regs[i] = 0; 22431e17060SPaolo Bonzini } 22531e17060SPaolo Bonzini 22631e17060SPaolo Bonzini fifo8_reset(&s->rx_fifo); 22731e17060SPaolo Bonzini fifo8_reset(&s->rx_fifo); 22831e17060SPaolo Bonzini /* non zero resets */ 22931e17060SPaolo Bonzini s->regs[R_CONFIG] |= MODEFAIL_GEN_EN; 23031e17060SPaolo Bonzini s->regs[R_SLAVE_IDLE_COUNT] = 0xFF; 23131e17060SPaolo Bonzini s->regs[R_TX_THRES] = 1; 23231e17060SPaolo Bonzini s->regs[R_RX_THRES] = 1; 23331e17060SPaolo Bonzini /* FIXME: move magic number definition somewhere sensible */ 23431e17060SPaolo Bonzini s->regs[R_MOD_ID] = 0x01090106; 23531e17060SPaolo Bonzini s->regs[R_LQSPI_CFG] = R_LQSPI_CFG_RESET; 23631e17060SPaolo Bonzini s->snoop_state = SNOOP_CHECKING; 23731e17060SPaolo Bonzini xilinx_spips_update_ixr(s); 23831e17060SPaolo Bonzini xilinx_spips_update_cs_lines(s); 23931e17060SPaolo Bonzini } 24031e17060SPaolo Bonzini 2419151da25SPeter Crosthwaite /* N way (num) in place bit striper. Lay out row wise bits (LSB to MSB) 2429151da25SPeter Crosthwaite * column wise (from element 0 to N-1). num is the length of x, and dir 2439151da25SPeter Crosthwaite * reverses the direction of the transform. Best illustrated by example: 2449151da25SPeter Crosthwaite * Each digit in the below array is a single bit (num == 3): 2459151da25SPeter Crosthwaite * 2469151da25SPeter Crosthwaite * {{ 76543210, } ----- stripe (dir == false) -----> {{ FCheb630, } 2479151da25SPeter Crosthwaite * { hgfedcba, } { GDAfc741, } 2489151da25SPeter Crosthwaite * { HGFEDCBA, }} <---- upstripe (dir == true) ----- { HEBgda52, }} 2499151da25SPeter Crosthwaite */ 2509151da25SPeter Crosthwaite 2519151da25SPeter Crosthwaite static inline void stripe8(uint8_t *x, int num, bool dir) 2529151da25SPeter Crosthwaite { 2539151da25SPeter Crosthwaite uint8_t r[num]; 2549151da25SPeter Crosthwaite memset(r, 0, sizeof(uint8_t) * num); 2559151da25SPeter Crosthwaite int idx[2] = {0, 0}; 2569151da25SPeter Crosthwaite int bit[2] = {0, 0}; 2579151da25SPeter Crosthwaite int d = dir; 2589151da25SPeter Crosthwaite 2599151da25SPeter Crosthwaite for (idx[0] = 0; idx[0] < num; ++idx[0]) { 2609151da25SPeter Crosthwaite for (bit[0] = 0; bit[0] < 8; ++bit[0]) { 2619151da25SPeter Crosthwaite r[idx[d]] |= x[idx[!d]] & 1 << bit[!d] ? 1 << bit[d] : 0; 2629151da25SPeter Crosthwaite idx[1] = (idx[1] + 1) % num; 2639151da25SPeter Crosthwaite if (!idx[1]) { 2649151da25SPeter Crosthwaite bit[1]++; 2659151da25SPeter Crosthwaite } 2669151da25SPeter Crosthwaite } 2679151da25SPeter Crosthwaite } 2689151da25SPeter Crosthwaite memcpy(x, r, sizeof(uint8_t) * num); 2699151da25SPeter Crosthwaite } 2709151da25SPeter Crosthwaite 27131e17060SPaolo Bonzini static void xilinx_spips_flush_txfifo(XilinxSPIPS *s) 27231e17060SPaolo Bonzini { 2734a5b6fa8SPeter Crosthwaite int debug_level = 0; 2744a5b6fa8SPeter Crosthwaite 27531e17060SPaolo Bonzini for (;;) { 27631e17060SPaolo Bonzini int i; 27731e17060SPaolo Bonzini uint8_t tx = 0; 2789151da25SPeter Crosthwaite uint8_t tx_rx[num_effective_busses(s)]; 27931e17060SPaolo Bonzini 28031e17060SPaolo Bonzini if (fifo8_is_empty(&s->tx_fifo)) { 2813ea728d0SPeter Crosthwaite if (!(s->regs[R_LQSPI_CFG] & LQSPI_CFG_LQ_MODE)) { 28231e17060SPaolo Bonzini s->regs[R_INTR_STATUS] |= IXR_TX_FIFO_UNDERFLOW; 2833ea728d0SPeter Crosthwaite } 28431e17060SPaolo Bonzini xilinx_spips_update_ixr(s); 28531e17060SPaolo Bonzini return; 2869151da25SPeter Crosthwaite } else if (s->snoop_state == SNOOP_STRIPING) { 2879151da25SPeter Crosthwaite for (i = 0; i < num_effective_busses(s); ++i) { 2889151da25SPeter Crosthwaite tx_rx[i] = fifo8_pop(&s->tx_fifo); 2899151da25SPeter Crosthwaite } 2909151da25SPeter Crosthwaite stripe8(tx_rx, num_effective_busses(s), false); 29131e17060SPaolo Bonzini } else { 29231e17060SPaolo Bonzini tx = fifo8_pop(&s->tx_fifo); 2939151da25SPeter Crosthwaite for (i = 0; i < num_effective_busses(s); ++i) { 2949151da25SPeter Crosthwaite tx_rx[i] = tx; 29531e17060SPaolo Bonzini } 29631e17060SPaolo Bonzini } 2979151da25SPeter Crosthwaite 2989151da25SPeter Crosthwaite for (i = 0; i < num_effective_busses(s); ++i) { 2994a5b6fa8SPeter Crosthwaite DB_PRINT_L(debug_level, "tx = %02x\n", tx_rx[i]); 3009151da25SPeter Crosthwaite tx_rx[i] = ssi_transfer(s->spi[i], (uint32_t)tx_rx[i]); 3014a5b6fa8SPeter Crosthwaite DB_PRINT_L(debug_level, "rx = %02x\n", tx_rx[i]); 3029151da25SPeter Crosthwaite } 3039151da25SPeter Crosthwaite 30431e17060SPaolo Bonzini if (fifo8_is_full(&s->rx_fifo)) { 30531e17060SPaolo Bonzini s->regs[R_INTR_STATUS] |= IXR_RX_FIFO_OVERFLOW; 3064a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "rx FIFO overflow"); 3079151da25SPeter Crosthwaite } else if (s->snoop_state == SNOOP_STRIPING) { 3089151da25SPeter Crosthwaite stripe8(tx_rx, num_effective_busses(s), true); 3099151da25SPeter Crosthwaite for (i = 0; i < num_effective_busses(s); ++i) { 3109151da25SPeter Crosthwaite fifo8_push(&s->rx_fifo, (uint8_t)tx_rx[i]); 3119151da25SPeter Crosthwaite } 31231e17060SPaolo Bonzini } else { 3139151da25SPeter Crosthwaite fifo8_push(&s->rx_fifo, (uint8_t)tx_rx[0]); 31431e17060SPaolo Bonzini } 31531e17060SPaolo Bonzini 3164a5b6fa8SPeter Crosthwaite DB_PRINT_L(debug_level, "initial snoop state: %x\n", 3174a5b6fa8SPeter Crosthwaite (unsigned)s->snoop_state); 31831e17060SPaolo Bonzini switch (s->snoop_state) { 31931e17060SPaolo Bonzini case (SNOOP_CHECKING): 32031e17060SPaolo Bonzini switch (tx) { /* new instruction code */ 32131e17060SPaolo Bonzini case READ: /* 3 address bytes, no dummy bytes/cycles */ 32231e17060SPaolo Bonzini case PP: 32331e17060SPaolo Bonzini case DPP: 32431e17060SPaolo Bonzini case QPP: 32531e17060SPaolo Bonzini s->snoop_state = 3; 32631e17060SPaolo Bonzini break; 32731e17060SPaolo Bonzini case FAST_READ: /* 3 address bytes, 1 dummy byte */ 32831e17060SPaolo Bonzini case DOR: 32931e17060SPaolo Bonzini case QOR: 33031e17060SPaolo Bonzini case DIOR: /* FIXME: these vary between vendor - set to spansion */ 33131e17060SPaolo Bonzini s->snoop_state = 4; 33231e17060SPaolo Bonzini break; 33331e17060SPaolo Bonzini case QIOR: /* 3 address bytes, 2 dummy bytes */ 33431e17060SPaolo Bonzini s->snoop_state = 6; 33531e17060SPaolo Bonzini break; 33631e17060SPaolo Bonzini default: 33731e17060SPaolo Bonzini s->snoop_state = SNOOP_NONE; 33831e17060SPaolo Bonzini } 33931e17060SPaolo Bonzini break; 34031e17060SPaolo Bonzini case (SNOOP_STRIPING): 34131e17060SPaolo Bonzini case (SNOOP_NONE): 3424a5b6fa8SPeter Crosthwaite /* Once we hit the boring stuff - squelch debug noise */ 3434a5b6fa8SPeter Crosthwaite if (!debug_level) { 3444a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "squelching debug info ....\n"); 3454a5b6fa8SPeter Crosthwaite debug_level = 1; 3464a5b6fa8SPeter Crosthwaite } 34731e17060SPaolo Bonzini break; 34831e17060SPaolo Bonzini default: 34931e17060SPaolo Bonzini s->snoop_state--; 35031e17060SPaolo Bonzini } 3514a5b6fa8SPeter Crosthwaite DB_PRINT_L(debug_level, "final snoop state: %x\n", 3524a5b6fa8SPeter Crosthwaite (unsigned)s->snoop_state); 35331e17060SPaolo Bonzini } 35431e17060SPaolo Bonzini } 35531e17060SPaolo Bonzini 356b0b7ae62SPeter Crosthwaite static inline void rx_data_bytes(XilinxSPIPS *s, uint8_t *value, int max) 35731e17060SPaolo Bonzini { 35831e17060SPaolo Bonzini int i; 35931e17060SPaolo Bonzini 36031e17060SPaolo Bonzini for (i = 0; i < max && !fifo8_is_empty(&s->rx_fifo); ++i) { 361b0b7ae62SPeter Crosthwaite value[i] = fifo8_pop(&s->rx_fifo); 36231e17060SPaolo Bonzini } 36331e17060SPaolo Bonzini } 36431e17060SPaolo Bonzini 36531e17060SPaolo Bonzini static uint64_t xilinx_spips_read(void *opaque, hwaddr addr, 36631e17060SPaolo Bonzini unsigned size) 36731e17060SPaolo Bonzini { 36831e17060SPaolo Bonzini XilinxSPIPS *s = opaque; 36931e17060SPaolo Bonzini uint32_t mask = ~0; 37031e17060SPaolo Bonzini uint32_t ret; 371b0b7ae62SPeter Crosthwaite uint8_t rx_buf[4]; 37231e17060SPaolo Bonzini 37331e17060SPaolo Bonzini addr >>= 2; 37431e17060SPaolo Bonzini switch (addr) { 37531e17060SPaolo Bonzini case R_CONFIG: 3762133a5f6SPeter Crosthwaite mask = ~(R_CONFIG_RSVD | MAN_START_COM); 37731e17060SPaolo Bonzini break; 37831e17060SPaolo Bonzini case R_INTR_STATUS: 37987920b44SPeter Crosthwaite ret = s->regs[addr] & IXR_ALL; 38087920b44SPeter Crosthwaite s->regs[addr] = 0; 3814a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret); 38287920b44SPeter Crosthwaite return ret; 38331e17060SPaolo Bonzini case R_INTR_MASK: 38431e17060SPaolo Bonzini mask = IXR_ALL; 38531e17060SPaolo Bonzini break; 38631e17060SPaolo Bonzini case R_EN: 38731e17060SPaolo Bonzini mask = 0x1; 38831e17060SPaolo Bonzini break; 38931e17060SPaolo Bonzini case R_SLAVE_IDLE_COUNT: 39031e17060SPaolo Bonzini mask = 0xFF; 39131e17060SPaolo Bonzini break; 39231e17060SPaolo Bonzini case R_MOD_ID: 39331e17060SPaolo Bonzini mask = 0x01FFFFFF; 39431e17060SPaolo Bonzini break; 39531e17060SPaolo Bonzini case R_INTR_EN: 39631e17060SPaolo Bonzini case R_INTR_DIS: 39731e17060SPaolo Bonzini case R_TX_DATA: 39831e17060SPaolo Bonzini mask = 0; 39931e17060SPaolo Bonzini break; 40031e17060SPaolo Bonzini case R_RX_DATA: 401b0b7ae62SPeter Crosthwaite memset(rx_buf, 0, sizeof(rx_buf)); 402b0b7ae62SPeter Crosthwaite rx_data_bytes(s, rx_buf, s->num_txrx_bytes); 403b0b7ae62SPeter Crosthwaite ret = s->regs[R_CONFIG] & ENDIAN ? cpu_to_be32(*(uint32_t *)rx_buf) 404b0b7ae62SPeter Crosthwaite : cpu_to_le32(*(uint32_t *)rx_buf); 4054a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret); 40631e17060SPaolo Bonzini xilinx_spips_update_ixr(s); 40731e17060SPaolo Bonzini return ret; 40831e17060SPaolo Bonzini } 4094a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4, 4104a5b6fa8SPeter Crosthwaite s->regs[addr] & mask); 41131e17060SPaolo Bonzini return s->regs[addr] & mask; 41231e17060SPaolo Bonzini 41331e17060SPaolo Bonzini } 41431e17060SPaolo Bonzini 41531e17060SPaolo Bonzini static inline void tx_data_bytes(XilinxSPIPS *s, uint32_t value, int num) 41631e17060SPaolo Bonzini { 41731e17060SPaolo Bonzini int i; 41831e17060SPaolo Bonzini for (i = 0; i < num && !fifo8_is_full(&s->tx_fifo); ++i) { 41931e17060SPaolo Bonzini if (s->regs[R_CONFIG] & ENDIAN) { 42031e17060SPaolo Bonzini fifo8_push(&s->tx_fifo, (uint8_t)(value >> 24)); 42131e17060SPaolo Bonzini value <<= 8; 42231e17060SPaolo Bonzini } else { 42331e17060SPaolo Bonzini fifo8_push(&s->tx_fifo, (uint8_t)value); 42431e17060SPaolo Bonzini value >>= 8; 42531e17060SPaolo Bonzini } 42631e17060SPaolo Bonzini } 42731e17060SPaolo Bonzini } 42831e17060SPaolo Bonzini 42931e17060SPaolo Bonzini static void xilinx_spips_write(void *opaque, hwaddr addr, 43031e17060SPaolo Bonzini uint64_t value, unsigned size) 43131e17060SPaolo Bonzini { 43231e17060SPaolo Bonzini int mask = ~0; 43331e17060SPaolo Bonzini int man_start_com = 0; 43431e17060SPaolo Bonzini XilinxSPIPS *s = opaque; 43531e17060SPaolo Bonzini 4364a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr, (unsigned)value); 43731e17060SPaolo Bonzini addr >>= 2; 43831e17060SPaolo Bonzini switch (addr) { 43931e17060SPaolo Bonzini case R_CONFIG: 4402133a5f6SPeter Crosthwaite mask = ~(R_CONFIG_RSVD | MAN_START_COM); 44131e17060SPaolo Bonzini if (value & MAN_START_COM) { 44231e17060SPaolo Bonzini man_start_com = 1; 44331e17060SPaolo Bonzini } 44431e17060SPaolo Bonzini break; 44531e17060SPaolo Bonzini case R_INTR_STATUS: 44631e17060SPaolo Bonzini mask = IXR_ALL; 44731e17060SPaolo Bonzini s->regs[R_INTR_STATUS] &= ~(mask & value); 44831e17060SPaolo Bonzini goto no_reg_update; 44931e17060SPaolo Bonzini case R_INTR_DIS: 45031e17060SPaolo Bonzini mask = IXR_ALL; 45131e17060SPaolo Bonzini s->regs[R_INTR_MASK] &= ~(mask & value); 45231e17060SPaolo Bonzini goto no_reg_update; 45331e17060SPaolo Bonzini case R_INTR_EN: 45431e17060SPaolo Bonzini mask = IXR_ALL; 45531e17060SPaolo Bonzini s->regs[R_INTR_MASK] |= mask & value; 45631e17060SPaolo Bonzini goto no_reg_update; 45731e17060SPaolo Bonzini case R_EN: 45831e17060SPaolo Bonzini mask = 0x1; 45931e17060SPaolo Bonzini break; 46031e17060SPaolo Bonzini case R_SLAVE_IDLE_COUNT: 46131e17060SPaolo Bonzini mask = 0xFF; 46231e17060SPaolo Bonzini break; 46331e17060SPaolo Bonzini case R_RX_DATA: 46431e17060SPaolo Bonzini case R_INTR_MASK: 46531e17060SPaolo Bonzini case R_MOD_ID: 46631e17060SPaolo Bonzini mask = 0; 46731e17060SPaolo Bonzini break; 46831e17060SPaolo Bonzini case R_TX_DATA: 46931e17060SPaolo Bonzini tx_data_bytes(s, (uint32_t)value, s->num_txrx_bytes); 47031e17060SPaolo Bonzini goto no_reg_update; 47131e17060SPaolo Bonzini case R_TXD1: 47231e17060SPaolo Bonzini tx_data_bytes(s, (uint32_t)value, 1); 47331e17060SPaolo Bonzini goto no_reg_update; 47431e17060SPaolo Bonzini case R_TXD2: 47531e17060SPaolo Bonzini tx_data_bytes(s, (uint32_t)value, 2); 47631e17060SPaolo Bonzini goto no_reg_update; 47731e17060SPaolo Bonzini case R_TXD3: 47831e17060SPaolo Bonzini tx_data_bytes(s, (uint32_t)value, 3); 47931e17060SPaolo Bonzini goto no_reg_update; 48031e17060SPaolo Bonzini } 48131e17060SPaolo Bonzini s->regs[addr] = (s->regs[addr] & ~mask) | (value & mask); 48231e17060SPaolo Bonzini no_reg_update: 483c4f08ffeSPeter Crosthwaite xilinx_spips_update_cs_lines(s); 484e100f3beSPeter Crosthwaite if ((man_start_com && s->regs[R_CONFIG] & MAN_START_EN) || 485e100f3beSPeter Crosthwaite (fifo8_is_empty(&s->tx_fifo) && s->regs[R_CONFIG] & MAN_START_EN)) { 48631e17060SPaolo Bonzini xilinx_spips_flush_txfifo(s); 48731e17060SPaolo Bonzini } 48831e17060SPaolo Bonzini xilinx_spips_update_cs_lines(s); 489c4f08ffeSPeter Crosthwaite xilinx_spips_update_ixr(s); 49031e17060SPaolo Bonzini } 49131e17060SPaolo Bonzini 49231e17060SPaolo Bonzini static const MemoryRegionOps spips_ops = { 49331e17060SPaolo Bonzini .read = xilinx_spips_read, 49431e17060SPaolo Bonzini .write = xilinx_spips_write, 49531e17060SPaolo Bonzini .endianness = DEVICE_LITTLE_ENDIAN, 49631e17060SPaolo Bonzini }; 49731e17060SPaolo Bonzini 498b5cd9143SPeter Crosthwaite static void xilinx_qspips_write(void *opaque, hwaddr addr, 499b5cd9143SPeter Crosthwaite uint64_t value, unsigned size) 500b5cd9143SPeter Crosthwaite { 501b5cd9143SPeter Crosthwaite XilinxQSPIPS *q = XILINX_QSPIPS(opaque); 502b5cd9143SPeter Crosthwaite 503b5cd9143SPeter Crosthwaite xilinx_spips_write(opaque, addr, value, size); 504b5cd9143SPeter Crosthwaite addr >>= 2; 505b5cd9143SPeter Crosthwaite 506b5cd9143SPeter Crosthwaite if (addr == R_LQSPI_CFG) { 507b5cd9143SPeter Crosthwaite q->lqspi_cached_addr = ~0ULL; 508b5cd9143SPeter Crosthwaite } 509b5cd9143SPeter Crosthwaite } 510b5cd9143SPeter Crosthwaite 511b5cd9143SPeter Crosthwaite static const MemoryRegionOps qspips_ops = { 512b5cd9143SPeter Crosthwaite .read = xilinx_spips_read, 513b5cd9143SPeter Crosthwaite .write = xilinx_qspips_write, 514b5cd9143SPeter Crosthwaite .endianness = DEVICE_LITTLE_ENDIAN, 515b5cd9143SPeter Crosthwaite }; 516b5cd9143SPeter Crosthwaite 51731e17060SPaolo Bonzini #define LQSPI_CACHE_SIZE 1024 51831e17060SPaolo Bonzini 51931e17060SPaolo Bonzini static uint64_t 52031e17060SPaolo Bonzini lqspi_read(void *opaque, hwaddr addr, unsigned int size) 52131e17060SPaolo Bonzini { 52231e17060SPaolo Bonzini int i; 5236b91f015SPeter Crosthwaite XilinxQSPIPS *q = opaque; 52431e17060SPaolo Bonzini XilinxSPIPS *s = opaque; 525abef5fa6SPeter Crosthwaite uint32_t ret; 52631e17060SPaolo Bonzini 5276b91f015SPeter Crosthwaite if (addr >= q->lqspi_cached_addr && 5286b91f015SPeter Crosthwaite addr <= q->lqspi_cached_addr + LQSPI_CACHE_SIZE - 4) { 529b0b7ae62SPeter Crosthwaite uint8_t *retp = &q->lqspi_buf[addr - q->lqspi_cached_addr]; 530b0b7ae62SPeter Crosthwaite ret = cpu_to_le32(*(uint32_t *)retp); 5314a5b6fa8SPeter Crosthwaite DB_PRINT_L(1, "addr: %08x, data: %08x\n", (unsigned)addr, 5324a5b6fa8SPeter Crosthwaite (unsigned)ret); 533abef5fa6SPeter Crosthwaite return ret; 53431e17060SPaolo Bonzini } else { 53531e17060SPaolo Bonzini int flash_addr = (addr / num_effective_busses(s)); 53631e17060SPaolo Bonzini int slave = flash_addr >> LQSPI_ADDRESS_BITS; 53731e17060SPaolo Bonzini int cache_entry = 0; 53815408b42SPeter Crosthwaite uint32_t u_page_save = s->regs[R_LQSPI_STS] & ~LQSPI_CFG_U_PAGE; 53915408b42SPeter Crosthwaite 54015408b42SPeter Crosthwaite s->regs[R_LQSPI_STS] &= ~LQSPI_CFG_U_PAGE; 54115408b42SPeter Crosthwaite s->regs[R_LQSPI_STS] |= slave ? LQSPI_CFG_U_PAGE : 0; 54231e17060SPaolo Bonzini 5434a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "config reg status: %08x\n", s->regs[R_LQSPI_CFG]); 54431e17060SPaolo Bonzini 54531e17060SPaolo Bonzini fifo8_reset(&s->tx_fifo); 54631e17060SPaolo Bonzini fifo8_reset(&s->rx_fifo); 54731e17060SPaolo Bonzini 54831e17060SPaolo Bonzini /* instruction */ 5494a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "pushing read instruction: %02x\n", 5504a5b6fa8SPeter Crosthwaite (unsigned)(uint8_t)(s->regs[R_LQSPI_CFG] & 5514a5b6fa8SPeter Crosthwaite LQSPI_CFG_INST_CODE)); 55231e17060SPaolo Bonzini fifo8_push(&s->tx_fifo, s->regs[R_LQSPI_CFG] & LQSPI_CFG_INST_CODE); 55331e17060SPaolo Bonzini /* read address */ 5544a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "pushing read address %06x\n", flash_addr); 55531e17060SPaolo Bonzini fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 16)); 55631e17060SPaolo Bonzini fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 8)); 55731e17060SPaolo Bonzini fifo8_push(&s->tx_fifo, (uint8_t)flash_addr); 55831e17060SPaolo Bonzini /* mode bits */ 55931e17060SPaolo Bonzini if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_MODE_EN) { 56031e17060SPaolo Bonzini fifo8_push(&s->tx_fifo, extract32(s->regs[R_LQSPI_CFG], 56131e17060SPaolo Bonzini LQSPI_CFG_MODE_SHIFT, 56231e17060SPaolo Bonzini LQSPI_CFG_MODE_WIDTH)); 56331e17060SPaolo Bonzini } 56431e17060SPaolo Bonzini /* dummy bytes */ 56531e17060SPaolo Bonzini for (i = 0; i < (extract32(s->regs[R_LQSPI_CFG], LQSPI_CFG_DUMMY_SHIFT, 56631e17060SPaolo Bonzini LQSPI_CFG_DUMMY_WIDTH)); ++i) { 5674a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "pushing dummy byte\n"); 56831e17060SPaolo Bonzini fifo8_push(&s->tx_fifo, 0); 56931e17060SPaolo Bonzini } 570c4f08ffeSPeter Crosthwaite xilinx_spips_update_cs_lines(s); 57131e17060SPaolo Bonzini xilinx_spips_flush_txfifo(s); 57231e17060SPaolo Bonzini fifo8_reset(&s->rx_fifo); 57331e17060SPaolo Bonzini 5744a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "starting QSPI data read\n"); 57531e17060SPaolo Bonzini 576b0b7ae62SPeter Crosthwaite while (cache_entry < LQSPI_CACHE_SIZE) { 577b0b7ae62SPeter Crosthwaite for (i = 0; i < 64; ++i) { 578b0b7ae62SPeter Crosthwaite tx_data_bytes(s, 0, 1); 579a66418f6SPeter Crosthwaite } 58031e17060SPaolo Bonzini xilinx_spips_flush_txfifo(s); 581b0b7ae62SPeter Crosthwaite for (i = 0; i < 64; ++i) { 582b0b7ae62SPeter Crosthwaite rx_data_bytes(s, &q->lqspi_buf[cache_entry++], 1); 583a66418f6SPeter Crosthwaite } 58431e17060SPaolo Bonzini } 58531e17060SPaolo Bonzini 58615408b42SPeter Crosthwaite s->regs[R_LQSPI_STS] &= ~LQSPI_CFG_U_PAGE; 58715408b42SPeter Crosthwaite s->regs[R_LQSPI_STS] |= u_page_save; 58831e17060SPaolo Bonzini xilinx_spips_update_cs_lines(s); 58931e17060SPaolo Bonzini 590b0b7ae62SPeter Crosthwaite q->lqspi_cached_addr = flash_addr * num_effective_busses(s); 59131e17060SPaolo Bonzini return lqspi_read(opaque, addr, size); 59231e17060SPaolo Bonzini } 59331e17060SPaolo Bonzini } 59431e17060SPaolo Bonzini 59531e17060SPaolo Bonzini static const MemoryRegionOps lqspi_ops = { 59631e17060SPaolo Bonzini .read = lqspi_read, 59731e17060SPaolo Bonzini .endianness = DEVICE_NATIVE_ENDIAN, 59831e17060SPaolo Bonzini .valid = { 599b0b7ae62SPeter Crosthwaite .min_access_size = 1, 60031e17060SPaolo Bonzini .max_access_size = 4 60131e17060SPaolo Bonzini } 60231e17060SPaolo Bonzini }; 60331e17060SPaolo Bonzini 60431e17060SPaolo Bonzini static void xilinx_spips_realize(DeviceState *dev, Error **errp) 60531e17060SPaolo Bonzini { 60631e17060SPaolo Bonzini XilinxSPIPS *s = XILINX_SPIPS(dev); 60731e17060SPaolo Bonzini SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 60810e60b35SPeter Crosthwaite XilinxSPIPSClass *xsc = XILINX_SPIPS_GET_CLASS(s); 60931e17060SPaolo Bonzini int i; 61031e17060SPaolo Bonzini 6114a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "realized spips\n"); 61231e17060SPaolo Bonzini 61331e17060SPaolo Bonzini s->spi = g_new(SSIBus *, s->num_busses); 61431e17060SPaolo Bonzini for (i = 0; i < s->num_busses; ++i) { 61531e17060SPaolo Bonzini char bus_name[16]; 61631e17060SPaolo Bonzini snprintf(bus_name, 16, "spi%d", i); 61731e17060SPaolo Bonzini s->spi[i] = ssi_create_bus(dev, bus_name); 61831e17060SPaolo Bonzini } 61931e17060SPaolo Bonzini 62031e17060SPaolo Bonzini s->cs_lines = g_new0(qemu_irq, s->num_cs * s->num_busses); 62131e17060SPaolo Bonzini ssi_auto_connect_slaves(DEVICE(s), s->cs_lines, s->spi[0]); 62231e17060SPaolo Bonzini ssi_auto_connect_slaves(DEVICE(s), s->cs_lines, s->spi[1]); 62331e17060SPaolo Bonzini sysbus_init_irq(sbd, &s->irq); 62431e17060SPaolo Bonzini for (i = 0; i < s->num_cs * s->num_busses; ++i) { 62531e17060SPaolo Bonzini sysbus_init_irq(sbd, &s->cs_lines[i]); 62631e17060SPaolo Bonzini } 62731e17060SPaolo Bonzini 62829776739SPaolo Bonzini memory_region_init_io(&s->iomem, OBJECT(s), xsc->reg_ops, s, 629*6363235bSAlistair Francis "spi", XLNX_SPIPS_R_MAX * 4); 63031e17060SPaolo Bonzini sysbus_init_mmio(sbd, &s->iomem); 63131e17060SPaolo Bonzini 6326b91f015SPeter Crosthwaite s->irqline = -1; 6336b91f015SPeter Crosthwaite 63410e60b35SPeter Crosthwaite fifo8_create(&s->rx_fifo, xsc->rx_fifo_size); 63510e60b35SPeter Crosthwaite fifo8_create(&s->tx_fifo, xsc->tx_fifo_size); 6366b91f015SPeter Crosthwaite } 6376b91f015SPeter Crosthwaite 6386b91f015SPeter Crosthwaite static void xilinx_qspips_realize(DeviceState *dev, Error **errp) 6396b91f015SPeter Crosthwaite { 6406b91f015SPeter Crosthwaite XilinxSPIPS *s = XILINX_SPIPS(dev); 6416b91f015SPeter Crosthwaite XilinxQSPIPS *q = XILINX_QSPIPS(dev); 6426b91f015SPeter Crosthwaite SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 6436b91f015SPeter Crosthwaite 6444a5b6fa8SPeter Crosthwaite DB_PRINT_L(0, "realized qspips\n"); 6456b91f015SPeter Crosthwaite 6466b91f015SPeter Crosthwaite s->num_busses = 2; 6476b91f015SPeter Crosthwaite s->num_cs = 2; 6486b91f015SPeter Crosthwaite s->num_txrx_bytes = 4; 6496b91f015SPeter Crosthwaite 6506b91f015SPeter Crosthwaite xilinx_spips_realize(dev, errp); 65129776739SPaolo Bonzini memory_region_init_io(&s->mmlqspi, OBJECT(s), &lqspi_ops, s, "lqspi", 65231e17060SPaolo Bonzini (1 << LQSPI_ADDRESS_BITS) * 2); 65331e17060SPaolo Bonzini sysbus_init_mmio(sbd, &s->mmlqspi); 65431e17060SPaolo Bonzini 6556b91f015SPeter Crosthwaite q->lqspi_cached_addr = ~0ULL; 65631e17060SPaolo Bonzini } 65731e17060SPaolo Bonzini 65831e17060SPaolo Bonzini static int xilinx_spips_post_load(void *opaque, int version_id) 65931e17060SPaolo Bonzini { 66031e17060SPaolo Bonzini xilinx_spips_update_ixr((XilinxSPIPS *)opaque); 66131e17060SPaolo Bonzini xilinx_spips_update_cs_lines((XilinxSPIPS *)opaque); 66231e17060SPaolo Bonzini return 0; 66331e17060SPaolo Bonzini } 66431e17060SPaolo Bonzini 66531e17060SPaolo Bonzini static const VMStateDescription vmstate_xilinx_spips = { 66631e17060SPaolo Bonzini .name = "xilinx_spips", 66731e17060SPaolo Bonzini .version_id = 2, 66831e17060SPaolo Bonzini .minimum_version_id = 2, 66931e17060SPaolo Bonzini .post_load = xilinx_spips_post_load, 67031e17060SPaolo Bonzini .fields = (VMStateField[]) { 67131e17060SPaolo Bonzini VMSTATE_FIFO8(tx_fifo, XilinxSPIPS), 67231e17060SPaolo Bonzini VMSTATE_FIFO8(rx_fifo, XilinxSPIPS), 673*6363235bSAlistair Francis VMSTATE_UINT32_ARRAY(regs, XilinxSPIPS, XLNX_SPIPS_R_MAX), 67431e17060SPaolo Bonzini VMSTATE_UINT8(snoop_state, XilinxSPIPS), 67531e17060SPaolo Bonzini VMSTATE_END_OF_LIST() 67631e17060SPaolo Bonzini } 67731e17060SPaolo Bonzini }; 67831e17060SPaolo Bonzini 67931e17060SPaolo Bonzini static Property xilinx_spips_properties[] = { 68031e17060SPaolo Bonzini DEFINE_PROP_UINT8("num-busses", XilinxSPIPS, num_busses, 1), 68131e17060SPaolo Bonzini DEFINE_PROP_UINT8("num-ss-bits", XilinxSPIPS, num_cs, 4), 68231e17060SPaolo Bonzini DEFINE_PROP_UINT8("num-txrx-bytes", XilinxSPIPS, num_txrx_bytes, 1), 68331e17060SPaolo Bonzini DEFINE_PROP_END_OF_LIST(), 68431e17060SPaolo Bonzini }; 6856b91f015SPeter Crosthwaite 6866b91f015SPeter Crosthwaite static void xilinx_qspips_class_init(ObjectClass *klass, void * data) 6876b91f015SPeter Crosthwaite { 6886b91f015SPeter Crosthwaite DeviceClass *dc = DEVICE_CLASS(klass); 68910e60b35SPeter Crosthwaite XilinxSPIPSClass *xsc = XILINX_SPIPS_CLASS(klass); 6906b91f015SPeter Crosthwaite 6916b91f015SPeter Crosthwaite dc->realize = xilinx_qspips_realize; 692b5cd9143SPeter Crosthwaite xsc->reg_ops = &qspips_ops; 69310e60b35SPeter Crosthwaite xsc->rx_fifo_size = RXFF_A_Q; 69410e60b35SPeter Crosthwaite xsc->tx_fifo_size = TXFF_A_Q; 6956b91f015SPeter Crosthwaite } 6966b91f015SPeter Crosthwaite 69731e17060SPaolo Bonzini static void xilinx_spips_class_init(ObjectClass *klass, void *data) 69831e17060SPaolo Bonzini { 69931e17060SPaolo Bonzini DeviceClass *dc = DEVICE_CLASS(klass); 70010e60b35SPeter Crosthwaite XilinxSPIPSClass *xsc = XILINX_SPIPS_CLASS(klass); 70131e17060SPaolo Bonzini 70231e17060SPaolo Bonzini dc->realize = xilinx_spips_realize; 70331e17060SPaolo Bonzini dc->reset = xilinx_spips_reset; 70431e17060SPaolo Bonzini dc->props = xilinx_spips_properties; 70531e17060SPaolo Bonzini dc->vmsd = &vmstate_xilinx_spips; 70610e60b35SPeter Crosthwaite 707b5cd9143SPeter Crosthwaite xsc->reg_ops = &spips_ops; 70810e60b35SPeter Crosthwaite xsc->rx_fifo_size = RXFF_A; 70910e60b35SPeter Crosthwaite xsc->tx_fifo_size = TXFF_A; 71031e17060SPaolo Bonzini } 71131e17060SPaolo Bonzini 71231e17060SPaolo Bonzini static const TypeInfo xilinx_spips_info = { 71331e17060SPaolo Bonzini .name = TYPE_XILINX_SPIPS, 71431e17060SPaolo Bonzini .parent = TYPE_SYS_BUS_DEVICE, 71531e17060SPaolo Bonzini .instance_size = sizeof(XilinxSPIPS), 71631e17060SPaolo Bonzini .class_init = xilinx_spips_class_init, 71710e60b35SPeter Crosthwaite .class_size = sizeof(XilinxSPIPSClass), 71831e17060SPaolo Bonzini }; 71931e17060SPaolo Bonzini 7206b91f015SPeter Crosthwaite static const TypeInfo xilinx_qspips_info = { 7216b91f015SPeter Crosthwaite .name = TYPE_XILINX_QSPIPS, 7226b91f015SPeter Crosthwaite .parent = TYPE_XILINX_SPIPS, 7236b91f015SPeter Crosthwaite .instance_size = sizeof(XilinxQSPIPS), 7246b91f015SPeter Crosthwaite .class_init = xilinx_qspips_class_init, 7256b91f015SPeter Crosthwaite }; 7266b91f015SPeter Crosthwaite 72731e17060SPaolo Bonzini static void xilinx_spips_register_types(void) 72831e17060SPaolo Bonzini { 72931e17060SPaolo Bonzini type_register_static(&xilinx_spips_info); 7306b91f015SPeter Crosthwaite type_register_static(&xilinx_qspips_info); 73131e17060SPaolo Bonzini } 73231e17060SPaolo Bonzini 73331e17060SPaolo Bonzini type_init(xilinx_spips_register_types) 734