xref: /openbmc/qemu/hw/ssi/xilinx_spi.c (revision 6a0acfff) 
1 /*
2  * QEMU model of the Xilinx SPI Controller
3  *
4  * Copyright (C) 2010 Edgar E. Iglesias.
5  * Copyright (C) 2012 Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>
6  * Copyright (C) 2012 PetaLogix
7  *
8  * Permission is hereby granted, free of charge, to any person obtaining a copy
9  * of this software and associated documentation files (the "Software"), to deal
10  * in the Software without restriction, including without limitation the rights
11  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12  * copies of the Software, and to permit persons to whom the Software is
13  * furnished to do so, subject to the following conditions:
14  *
15  * The above copyright notice and this permission notice shall be included in
16  * all copies or substantial portions of the Software.
17  *
18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24  * THE SOFTWARE.
25  */
26 
27 #include "qemu/osdep.h"
28 #include "hw/sysbus.h"
29 #include "sysemu/sysemu.h"
30 #include "qemu/log.h"
31 #include "qemu/module.h"
32 #include "qemu/fifo8.h"
33 
34 #include "hw/irq.h"
35 #include "hw/ssi/ssi.h"
36 
37 #ifdef XILINX_SPI_ERR_DEBUG
38 #define DB_PRINT(...) do { \
39     fprintf(stderr,  ": %s: ", __func__); \
40     fprintf(stderr, ## __VA_ARGS__); \
41     } while (0)
42 #else
43     #define DB_PRINT(...)
44 #endif
45 
46 #define R_DGIER     (0x1c / 4)
47 #define R_DGIER_IE  (1 << 31)
48 
49 #define R_IPISR     (0x20 / 4)
50 #define IRQ_DRR_NOT_EMPTY    (1 << (31 - 23))
51 #define IRQ_DRR_OVERRUN      (1 << (31 - 26))
52 #define IRQ_DRR_FULL         (1 << (31 - 27))
53 #define IRQ_TX_FF_HALF_EMPTY (1 << 6)
54 #define IRQ_DTR_UNDERRUN     (1 << 3)
55 #define IRQ_DTR_EMPTY        (1 << (31 - 29))
56 
57 #define R_IPIER     (0x28 / 4)
58 #define R_SRR       (0x40 / 4)
59 #define R_SPICR     (0x60 / 4)
60 #define R_SPICR_TXFF_RST     (1 << 5)
61 #define R_SPICR_RXFF_RST     (1 << 6)
62 #define R_SPICR_MTI          (1 << 8)
63 
64 #define R_SPISR     (0x64 / 4)
65 #define SR_TX_FULL    (1 << 3)
66 #define SR_TX_EMPTY   (1 << 2)
67 #define SR_RX_FULL    (1 << 1)
68 #define SR_RX_EMPTY   (1 << 0)
69 
70 #define R_SPIDTR    (0x68 / 4)
71 #define R_SPIDRR    (0x6C / 4)
72 #define R_SPISSR    (0x70 / 4)
73 #define R_TX_FF_OCY (0x74 / 4)
74 #define R_RX_FF_OCY (0x78 / 4)
75 #define R_MAX       (0x7C / 4)
76 
77 #define FIFO_CAPACITY 256
78 
79 #define TYPE_XILINX_SPI "xlnx.xps-spi"
80 #define XILINX_SPI(obj) OBJECT_CHECK(XilinxSPI, (obj), TYPE_XILINX_SPI)
81 
82 typedef struct XilinxSPI {
83     SysBusDevice parent_obj;
84 
85     MemoryRegion mmio;
86 
87     qemu_irq irq;
88     int irqline;
89 
90     uint8_t num_cs;
91     qemu_irq *cs_lines;
92 
93     SSIBus *spi;
94 
95     Fifo8 rx_fifo;
96     Fifo8 tx_fifo;
97 
98     uint32_t regs[R_MAX];
99 } XilinxSPI;
100 
101 static void txfifo_reset(XilinxSPI *s)
102 {
103     fifo8_reset(&s->tx_fifo);
104 
105     s->regs[R_SPISR] &= ~SR_TX_FULL;
106     s->regs[R_SPISR] |= SR_TX_EMPTY;
107 }
108 
109 static void rxfifo_reset(XilinxSPI *s)
110 {
111     fifo8_reset(&s->rx_fifo);
112 
113     s->regs[R_SPISR] |= SR_RX_EMPTY;
114     s->regs[R_SPISR] &= ~SR_RX_FULL;
115 }
116 
117 static void xlx_spi_update_cs(XilinxSPI *s)
118 {
119     int i;
120 
121     for (i = 0; i < s->num_cs; ++i) {
122         qemu_set_irq(s->cs_lines[i], !(~s->regs[R_SPISSR] & 1 << i));
123     }
124 }
125 
126 static void xlx_spi_update_irq(XilinxSPI *s)
127 {
128     uint32_t pending;
129 
130     s->regs[R_IPISR] |=
131             (!fifo8_is_empty(&s->rx_fifo) ? IRQ_DRR_NOT_EMPTY : 0) |
132             (fifo8_is_full(&s->rx_fifo) ? IRQ_DRR_FULL : 0);
133 
134     pending = s->regs[R_IPISR] & s->regs[R_IPIER];
135 
136     pending = pending && (s->regs[R_DGIER] & R_DGIER_IE);
137     pending = !!pending;
138 
139     /* This call lies right in the data paths so don't call the
140        irq chain unless things really changed.  */
141     if (pending != s->irqline) {
142         s->irqline = pending;
143         DB_PRINT("irq_change of state %d ISR:%x IER:%X\n",
144                     pending, s->regs[R_IPISR], s->regs[R_IPIER]);
145         qemu_set_irq(s->irq, pending);
146     }
147 
148 }
149 
150 static void xlx_spi_do_reset(XilinxSPI *s)
151 {
152     memset(s->regs, 0, sizeof s->regs);
153 
154     rxfifo_reset(s);
155     txfifo_reset(s);
156 
157     s->regs[R_SPISSR] = ~0;
158     xlx_spi_update_irq(s);
159     xlx_spi_update_cs(s);
160 }
161 
162 static void xlx_spi_reset(DeviceState *d)
163 {
164     xlx_spi_do_reset(XILINX_SPI(d));
165 }
166 
167 static inline int spi_master_enabled(XilinxSPI *s)
168 {
169     return !(s->regs[R_SPICR] & R_SPICR_MTI);
170 }
171 
172 static void spi_flush_txfifo(XilinxSPI *s)
173 {
174     uint32_t tx;
175     uint32_t rx;
176 
177     while (!fifo8_is_empty(&s->tx_fifo)) {
178         tx = (uint32_t)fifo8_pop(&s->tx_fifo);
179         DB_PRINT("data tx:%x\n", tx);
180         rx = ssi_transfer(s->spi, tx);
181         DB_PRINT("data rx:%x\n", rx);
182         if (fifo8_is_full(&s->rx_fifo)) {
183             s->regs[R_IPISR] |= IRQ_DRR_OVERRUN;
184         } else {
185             fifo8_push(&s->rx_fifo, (uint8_t)rx);
186             if (fifo8_is_full(&s->rx_fifo)) {
187                 s->regs[R_SPISR] |= SR_RX_FULL;
188                 s->regs[R_IPISR] |= IRQ_DRR_FULL;
189             }
190         }
191 
192         s->regs[R_SPISR] &= ~SR_RX_EMPTY;
193         s->regs[R_SPISR] &= ~SR_TX_FULL;
194         s->regs[R_SPISR] |= SR_TX_EMPTY;
195 
196         s->regs[R_IPISR] |= IRQ_DTR_EMPTY;
197         s->regs[R_IPISR] |= IRQ_DRR_NOT_EMPTY;
198     }
199 
200 }
201 
202 static uint64_t
203 spi_read(void *opaque, hwaddr addr, unsigned int size)
204 {
205     XilinxSPI *s = opaque;
206     uint32_t r = 0;
207 
208     addr >>= 2;
209     switch (addr) {
210     case R_SPIDRR:
211         if (fifo8_is_empty(&s->rx_fifo)) {
212             DB_PRINT("Read from empty FIFO!\n");
213             return 0xdeadbeef;
214         }
215 
216         s->regs[R_SPISR] &= ~SR_RX_FULL;
217         r = fifo8_pop(&s->rx_fifo);
218         if (fifo8_is_empty(&s->rx_fifo)) {
219             s->regs[R_SPISR] |= SR_RX_EMPTY;
220         }
221         break;
222 
223     case R_SPISR:
224         r = s->regs[addr];
225         break;
226 
227     default:
228         if (addr < ARRAY_SIZE(s->regs)) {
229             r = s->regs[addr];
230         }
231         break;
232 
233     }
234     DB_PRINT("addr=" TARGET_FMT_plx " = %x\n", addr * 4, r);
235     xlx_spi_update_irq(s);
236     return r;
237 }
238 
239 static void
240 spi_write(void *opaque, hwaddr addr,
241             uint64_t val64, unsigned int size)
242 {
243     XilinxSPI *s = opaque;
244     uint32_t value = val64;
245 
246     DB_PRINT("addr=" TARGET_FMT_plx " = %x\n", addr, value);
247     addr >>= 2;
248     switch (addr) {
249     case R_SRR:
250         if (value != 0xa) {
251             DB_PRINT("Invalid write to SRR %x\n", value);
252         } else {
253             xlx_spi_do_reset(s);
254         }
255         break;
256 
257     case R_SPIDTR:
258         s->regs[R_SPISR] &= ~SR_TX_EMPTY;
259         fifo8_push(&s->tx_fifo, (uint8_t)value);
260         if (fifo8_is_full(&s->tx_fifo)) {
261             s->regs[R_SPISR] |= SR_TX_FULL;
262         }
263         if (!spi_master_enabled(s)) {
264             goto done;
265         } else {
266             DB_PRINT("DTR and master enabled\n");
267         }
268         spi_flush_txfifo(s);
269         break;
270 
271     case R_SPISR:
272         DB_PRINT("Invalid write to SPISR %x\n", value);
273         break;
274 
275     case R_IPISR:
276         /* Toggle the bits.  */
277         s->regs[addr] ^= value;
278         break;
279 
280     /* Slave Select Register.  */
281     case R_SPISSR:
282         s->regs[addr] = value;
283         xlx_spi_update_cs(s);
284         break;
285 
286     case R_SPICR:
287         /* FIXME: reset irq and sr state to empty queues.  */
288         if (value & R_SPICR_RXFF_RST) {
289             rxfifo_reset(s);
290         }
291 
292         if (value & R_SPICR_TXFF_RST) {
293             txfifo_reset(s);
294         }
295         value &= ~(R_SPICR_RXFF_RST | R_SPICR_TXFF_RST);
296         s->regs[addr] = value;
297 
298         if (!(value & R_SPICR_MTI)) {
299             spi_flush_txfifo(s);
300         }
301         break;
302 
303     default:
304         if (addr < ARRAY_SIZE(s->regs)) {
305             s->regs[addr] = value;
306         }
307         break;
308     }
309 
310 done:
311     xlx_spi_update_irq(s);
312 }
313 
314 static const MemoryRegionOps spi_ops = {
315     .read = spi_read,
316     .write = spi_write,
317     .endianness = DEVICE_NATIVE_ENDIAN,
318     .valid = {
319         .min_access_size = 4,
320         .max_access_size = 4
321     }
322 };
323 
324 static void xilinx_spi_realize(DeviceState *dev, Error **errp)
325 {
326     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
327     XilinxSPI *s = XILINX_SPI(dev);
328     int i;
329 
330     DB_PRINT("\n");
331 
332     s->spi = ssi_create_bus(dev, "spi");
333 
334     sysbus_init_irq(sbd, &s->irq);
335     s->cs_lines = g_new0(qemu_irq, s->num_cs);
336     ssi_auto_connect_slaves(dev, s->cs_lines, s->spi);
337     for (i = 0; i < s->num_cs; ++i) {
338         sysbus_init_irq(sbd, &s->cs_lines[i]);
339     }
340 
341     memory_region_init_io(&s->mmio, OBJECT(s), &spi_ops, s,
342                           "xilinx-spi", R_MAX * 4);
343     sysbus_init_mmio(sbd, &s->mmio);
344 
345     s->irqline = -1;
346 
347     fifo8_create(&s->tx_fifo, FIFO_CAPACITY);
348     fifo8_create(&s->rx_fifo, FIFO_CAPACITY);
349 }
350 
351 static const VMStateDescription vmstate_xilinx_spi = {
352     .name = "xilinx_spi",
353     .version_id = 1,
354     .minimum_version_id = 1,
355     .fields = (VMStateField[]) {
356         VMSTATE_FIFO8(tx_fifo, XilinxSPI),
357         VMSTATE_FIFO8(rx_fifo, XilinxSPI),
358         VMSTATE_UINT32_ARRAY(regs, XilinxSPI, R_MAX),
359         VMSTATE_END_OF_LIST()
360     }
361 };
362 
363 static Property xilinx_spi_properties[] = {
364     DEFINE_PROP_UINT8("num-ss-bits", XilinxSPI, num_cs, 1),
365     DEFINE_PROP_END_OF_LIST(),
366 };
367 
368 static void xilinx_spi_class_init(ObjectClass *klass, void *data)
369 {
370     DeviceClass *dc = DEVICE_CLASS(klass);
371 
372     dc->realize = xilinx_spi_realize;
373     dc->reset = xlx_spi_reset;
374     dc->props = xilinx_spi_properties;
375     dc->vmsd = &vmstate_xilinx_spi;
376 }
377 
378 static const TypeInfo xilinx_spi_info = {
379     .name           = TYPE_XILINX_SPI,
380     .parent         = TYPE_SYS_BUS_DEVICE,
381     .instance_size  = sizeof(XilinxSPI),
382     .class_init     = xilinx_spi_class_init,
383 };
384 
385 static void xilinx_spi_register_types(void)
386 {
387     type_register_static(&xilinx_spi_info);
388 }
389 
390 type_init(xilinx_spi_register_types)
391