1 /* 2 * QEMU model of the Xilinx SPI Controller 3 * 4 * Copyright (C) 2010 Edgar E. Iglesias. 5 * Copyright (C) 2012 Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com> 6 * Copyright (C) 2012 PetaLogix 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27 #include "qemu/osdep.h" 28 #include "hw/sysbus.h" 29 #include "sysemu/sysemu.h" 30 #include "qemu/log.h" 31 #include "qemu/module.h" 32 #include "qemu/fifo8.h" 33 34 #include "hw/ssi/ssi.h" 35 36 #ifdef XILINX_SPI_ERR_DEBUG 37 #define DB_PRINT(...) do { \ 38 fprintf(stderr, ": %s: ", __func__); \ 39 fprintf(stderr, ## __VA_ARGS__); \ 40 } while (0) 41 #else 42 #define DB_PRINT(...) 43 #endif 44 45 #define R_DGIER (0x1c / 4) 46 #define R_DGIER_IE (1 << 31) 47 48 #define R_IPISR (0x20 / 4) 49 #define IRQ_DRR_NOT_EMPTY (1 << (31 - 23)) 50 #define IRQ_DRR_OVERRUN (1 << (31 - 26)) 51 #define IRQ_DRR_FULL (1 << (31 - 27)) 52 #define IRQ_TX_FF_HALF_EMPTY (1 << 6) 53 #define IRQ_DTR_UNDERRUN (1 << 3) 54 #define IRQ_DTR_EMPTY (1 << (31 - 29)) 55 56 #define R_IPIER (0x28 / 4) 57 #define R_SRR (0x40 / 4) 58 #define R_SPICR (0x60 / 4) 59 #define R_SPICR_TXFF_RST (1 << 5) 60 #define R_SPICR_RXFF_RST (1 << 6) 61 #define R_SPICR_MTI (1 << 8) 62 63 #define R_SPISR (0x64 / 4) 64 #define SR_TX_FULL (1 << 3) 65 #define SR_TX_EMPTY (1 << 2) 66 #define SR_RX_FULL (1 << 1) 67 #define SR_RX_EMPTY (1 << 0) 68 69 #define R_SPIDTR (0x68 / 4) 70 #define R_SPIDRR (0x6C / 4) 71 #define R_SPISSR (0x70 / 4) 72 #define R_TX_FF_OCY (0x74 / 4) 73 #define R_RX_FF_OCY (0x78 / 4) 74 #define R_MAX (0x7C / 4) 75 76 #define FIFO_CAPACITY 256 77 78 #define TYPE_XILINX_SPI "xlnx.xps-spi" 79 #define XILINX_SPI(obj) OBJECT_CHECK(XilinxSPI, (obj), TYPE_XILINX_SPI) 80 81 typedef struct XilinxSPI { 82 SysBusDevice parent_obj; 83 84 MemoryRegion mmio; 85 86 qemu_irq irq; 87 int irqline; 88 89 uint8_t num_cs; 90 qemu_irq *cs_lines; 91 92 SSIBus *spi; 93 94 Fifo8 rx_fifo; 95 Fifo8 tx_fifo; 96 97 uint32_t regs[R_MAX]; 98 } XilinxSPI; 99 100 static void txfifo_reset(XilinxSPI *s) 101 { 102 fifo8_reset(&s->tx_fifo); 103 104 s->regs[R_SPISR] &= ~SR_TX_FULL; 105 s->regs[R_SPISR] |= SR_TX_EMPTY; 106 } 107 108 static void rxfifo_reset(XilinxSPI *s) 109 { 110 fifo8_reset(&s->rx_fifo); 111 112 s->regs[R_SPISR] |= SR_RX_EMPTY; 113 s->regs[R_SPISR] &= ~SR_RX_FULL; 114 } 115 116 static void xlx_spi_update_cs(XilinxSPI *s) 117 { 118 int i; 119 120 for (i = 0; i < s->num_cs; ++i) { 121 qemu_set_irq(s->cs_lines[i], !(~s->regs[R_SPISSR] & 1 << i)); 122 } 123 } 124 125 static void xlx_spi_update_irq(XilinxSPI *s) 126 { 127 uint32_t pending; 128 129 s->regs[R_IPISR] |= 130 (!fifo8_is_empty(&s->rx_fifo) ? IRQ_DRR_NOT_EMPTY : 0) | 131 (fifo8_is_full(&s->rx_fifo) ? IRQ_DRR_FULL : 0); 132 133 pending = s->regs[R_IPISR] & s->regs[R_IPIER]; 134 135 pending = pending && (s->regs[R_DGIER] & R_DGIER_IE); 136 pending = !!pending; 137 138 /* This call lies right in the data paths so don't call the 139 irq chain unless things really changed. */ 140 if (pending != s->irqline) { 141 s->irqline = pending; 142 DB_PRINT("irq_change of state %d ISR:%x IER:%X\n", 143 pending, s->regs[R_IPISR], s->regs[R_IPIER]); 144 qemu_set_irq(s->irq, pending); 145 } 146 147 } 148 149 static void xlx_spi_do_reset(XilinxSPI *s) 150 { 151 memset(s->regs, 0, sizeof s->regs); 152 153 rxfifo_reset(s); 154 txfifo_reset(s); 155 156 s->regs[R_SPISSR] = ~0; 157 xlx_spi_update_irq(s); 158 xlx_spi_update_cs(s); 159 } 160 161 static void xlx_spi_reset(DeviceState *d) 162 { 163 xlx_spi_do_reset(XILINX_SPI(d)); 164 } 165 166 static inline int spi_master_enabled(XilinxSPI *s) 167 { 168 return !(s->regs[R_SPICR] & R_SPICR_MTI); 169 } 170 171 static void spi_flush_txfifo(XilinxSPI *s) 172 { 173 uint32_t tx; 174 uint32_t rx; 175 176 while (!fifo8_is_empty(&s->tx_fifo)) { 177 tx = (uint32_t)fifo8_pop(&s->tx_fifo); 178 DB_PRINT("data tx:%x\n", tx); 179 rx = ssi_transfer(s->spi, tx); 180 DB_PRINT("data rx:%x\n", rx); 181 if (fifo8_is_full(&s->rx_fifo)) { 182 s->regs[R_IPISR] |= IRQ_DRR_OVERRUN; 183 } else { 184 fifo8_push(&s->rx_fifo, (uint8_t)rx); 185 if (fifo8_is_full(&s->rx_fifo)) { 186 s->regs[R_SPISR] |= SR_RX_FULL; 187 s->regs[R_IPISR] |= IRQ_DRR_FULL; 188 } 189 } 190 191 s->regs[R_SPISR] &= ~SR_RX_EMPTY; 192 s->regs[R_SPISR] &= ~SR_TX_FULL; 193 s->regs[R_SPISR] |= SR_TX_EMPTY; 194 195 s->regs[R_IPISR] |= IRQ_DTR_EMPTY; 196 s->regs[R_IPISR] |= IRQ_DRR_NOT_EMPTY; 197 } 198 199 } 200 201 static uint64_t 202 spi_read(void *opaque, hwaddr addr, unsigned int size) 203 { 204 XilinxSPI *s = opaque; 205 uint32_t r = 0; 206 207 addr >>= 2; 208 switch (addr) { 209 case R_SPIDRR: 210 if (fifo8_is_empty(&s->rx_fifo)) { 211 DB_PRINT("Read from empty FIFO!\n"); 212 return 0xdeadbeef; 213 } 214 215 s->regs[R_SPISR] &= ~SR_RX_FULL; 216 r = fifo8_pop(&s->rx_fifo); 217 if (fifo8_is_empty(&s->rx_fifo)) { 218 s->regs[R_SPISR] |= SR_RX_EMPTY; 219 } 220 break; 221 222 case R_SPISR: 223 r = s->regs[addr]; 224 break; 225 226 default: 227 if (addr < ARRAY_SIZE(s->regs)) { 228 r = s->regs[addr]; 229 } 230 break; 231 232 } 233 DB_PRINT("addr=" TARGET_FMT_plx " = %x\n", addr * 4, r); 234 xlx_spi_update_irq(s); 235 return r; 236 } 237 238 static void 239 spi_write(void *opaque, hwaddr addr, 240 uint64_t val64, unsigned int size) 241 { 242 XilinxSPI *s = opaque; 243 uint32_t value = val64; 244 245 DB_PRINT("addr=" TARGET_FMT_plx " = %x\n", addr, value); 246 addr >>= 2; 247 switch (addr) { 248 case R_SRR: 249 if (value != 0xa) { 250 DB_PRINT("Invalid write to SRR %x\n", value); 251 } else { 252 xlx_spi_do_reset(s); 253 } 254 break; 255 256 case R_SPIDTR: 257 s->regs[R_SPISR] &= ~SR_TX_EMPTY; 258 fifo8_push(&s->tx_fifo, (uint8_t)value); 259 if (fifo8_is_full(&s->tx_fifo)) { 260 s->regs[R_SPISR] |= SR_TX_FULL; 261 } 262 if (!spi_master_enabled(s)) { 263 goto done; 264 } else { 265 DB_PRINT("DTR and master enabled\n"); 266 } 267 spi_flush_txfifo(s); 268 break; 269 270 case R_SPISR: 271 DB_PRINT("Invalid write to SPISR %x\n", value); 272 break; 273 274 case R_IPISR: 275 /* Toggle the bits. */ 276 s->regs[addr] ^= value; 277 break; 278 279 /* Slave Select Register. */ 280 case R_SPISSR: 281 s->regs[addr] = value; 282 xlx_spi_update_cs(s); 283 break; 284 285 case R_SPICR: 286 /* FIXME: reset irq and sr state to empty queues. */ 287 if (value & R_SPICR_RXFF_RST) { 288 rxfifo_reset(s); 289 } 290 291 if (value & R_SPICR_TXFF_RST) { 292 txfifo_reset(s); 293 } 294 value &= ~(R_SPICR_RXFF_RST | R_SPICR_TXFF_RST); 295 s->regs[addr] = value; 296 297 if (!(value & R_SPICR_MTI)) { 298 spi_flush_txfifo(s); 299 } 300 break; 301 302 default: 303 if (addr < ARRAY_SIZE(s->regs)) { 304 s->regs[addr] = value; 305 } 306 break; 307 } 308 309 done: 310 xlx_spi_update_irq(s); 311 } 312 313 static const MemoryRegionOps spi_ops = { 314 .read = spi_read, 315 .write = spi_write, 316 .endianness = DEVICE_NATIVE_ENDIAN, 317 .valid = { 318 .min_access_size = 4, 319 .max_access_size = 4 320 } 321 }; 322 323 static void xilinx_spi_realize(DeviceState *dev, Error **errp) 324 { 325 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 326 XilinxSPI *s = XILINX_SPI(dev); 327 int i; 328 329 DB_PRINT("\n"); 330 331 s->spi = ssi_create_bus(dev, "spi"); 332 333 sysbus_init_irq(sbd, &s->irq); 334 s->cs_lines = g_new0(qemu_irq, s->num_cs); 335 ssi_auto_connect_slaves(dev, s->cs_lines, s->spi); 336 for (i = 0; i < s->num_cs; ++i) { 337 sysbus_init_irq(sbd, &s->cs_lines[i]); 338 } 339 340 memory_region_init_io(&s->mmio, OBJECT(s), &spi_ops, s, 341 "xilinx-spi", R_MAX * 4); 342 sysbus_init_mmio(sbd, &s->mmio); 343 344 s->irqline = -1; 345 346 fifo8_create(&s->tx_fifo, FIFO_CAPACITY); 347 fifo8_create(&s->rx_fifo, FIFO_CAPACITY); 348 } 349 350 static const VMStateDescription vmstate_xilinx_spi = { 351 .name = "xilinx_spi", 352 .version_id = 1, 353 .minimum_version_id = 1, 354 .fields = (VMStateField[]) { 355 VMSTATE_FIFO8(tx_fifo, XilinxSPI), 356 VMSTATE_FIFO8(rx_fifo, XilinxSPI), 357 VMSTATE_UINT32_ARRAY(regs, XilinxSPI, R_MAX), 358 VMSTATE_END_OF_LIST() 359 } 360 }; 361 362 static Property xilinx_spi_properties[] = { 363 DEFINE_PROP_UINT8("num-ss-bits", XilinxSPI, num_cs, 1), 364 DEFINE_PROP_END_OF_LIST(), 365 }; 366 367 static void xilinx_spi_class_init(ObjectClass *klass, void *data) 368 { 369 DeviceClass *dc = DEVICE_CLASS(klass); 370 371 dc->realize = xilinx_spi_realize; 372 dc->reset = xlx_spi_reset; 373 dc->props = xilinx_spi_properties; 374 dc->vmsd = &vmstate_xilinx_spi; 375 } 376 377 static const TypeInfo xilinx_spi_info = { 378 .name = TYPE_XILINX_SPI, 379 .parent = TYPE_SYS_BUS_DEVICE, 380 .instance_size = sizeof(XilinxSPI), 381 .class_init = xilinx_spi_class_init, 382 }; 383 384 static void xilinx_spi_register_types(void) 385 { 386 type_register_static(&xilinx_spi_info); 387 } 388 389 type_init(xilinx_spi_register_types) 390