1 /* 2 * STM32F405 SPI 3 * 4 * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/log.h" 27 #include "hw/ssi/stm32f2xx_spi.h" 28 29 #ifndef STM_SPI_ERR_DEBUG 30 #define STM_SPI_ERR_DEBUG 0 31 #endif 32 33 #define DB_PRINT_L(lvl, fmt, args...) do { \ 34 if (STM_SPI_ERR_DEBUG >= lvl) { \ 35 qemu_log("%s: " fmt, __func__, ## args); \ 36 } \ 37 } while (0) 38 39 #define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args) 40 41 static void stm32f2xx_spi_reset(DeviceState *dev) 42 { 43 STM32F2XXSPIState *s = STM32F2XX_SPI(dev); 44 45 s->spi_cr1 = 0x00000000; 46 s->spi_cr2 = 0x00000000; 47 s->spi_sr = 0x0000000A; 48 s->spi_dr = 0x0000000C; 49 s->spi_crcpr = 0x00000007; 50 s->spi_rxcrcr = 0x00000000; 51 s->spi_txcrcr = 0x00000000; 52 s->spi_i2scfgr = 0x00000000; 53 s->spi_i2spr = 0x00000002; 54 } 55 56 static void stm32f2xx_spi_transfer(STM32F2XXSPIState *s) 57 { 58 DB_PRINT("Data to send: 0x%x\n", s->spi_dr); 59 60 s->spi_dr = ssi_transfer(s->ssi, s->spi_dr); 61 s->spi_sr |= STM_SPI_SR_RXNE; 62 63 DB_PRINT("Data received: 0x%x\n", s->spi_dr); 64 } 65 66 static uint64_t stm32f2xx_spi_read(void *opaque, hwaddr addr, 67 unsigned int size) 68 { 69 STM32F2XXSPIState *s = opaque; 70 71 DB_PRINT("Address: 0x%" HWADDR_PRIx "\n", addr); 72 73 switch (addr) { 74 case STM_SPI_CR1: 75 return s->spi_cr1; 76 case STM_SPI_CR2: 77 qemu_log_mask(LOG_UNIMP, "%s: Interrupts and DMA are not implemented\n", 78 __func__); 79 return s->spi_cr2; 80 case STM_SPI_SR: 81 return s->spi_sr; 82 case STM_SPI_DR: 83 stm32f2xx_spi_transfer(s); 84 s->spi_sr &= ~STM_SPI_SR_RXNE; 85 return s->spi_dr; 86 case STM_SPI_CRCPR: 87 qemu_log_mask(LOG_UNIMP, "%s: CRC is not implemented, the registers " \ 88 "are included for compatibility\n", __func__); 89 return s->spi_crcpr; 90 case STM_SPI_RXCRCR: 91 qemu_log_mask(LOG_UNIMP, "%s: CRC is not implemented, the registers " \ 92 "are included for compatibility\n", __func__); 93 return s->spi_rxcrcr; 94 case STM_SPI_TXCRCR: 95 qemu_log_mask(LOG_UNIMP, "%s: CRC is not implemented, the registers " \ 96 "are included for compatibility\n", __func__); 97 return s->spi_txcrcr; 98 case STM_SPI_I2SCFGR: 99 qemu_log_mask(LOG_UNIMP, "%s: I2S is not implemented, the registers " \ 100 "are included for compatibility\n", __func__); 101 return s->spi_i2scfgr; 102 case STM_SPI_I2SPR: 103 qemu_log_mask(LOG_UNIMP, "%s: I2S is not implemented, the registers " \ 104 "are included for compatibility\n", __func__); 105 return s->spi_i2spr; 106 default: 107 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", 108 __func__, addr); 109 } 110 111 return 0; 112 } 113 114 static void stm32f2xx_spi_write(void *opaque, hwaddr addr, 115 uint64_t val64, unsigned int size) 116 { 117 STM32F2XXSPIState *s = opaque; 118 uint32_t value = val64; 119 120 DB_PRINT("Address: 0x%" HWADDR_PRIx ", Value: 0x%x\n", addr, value); 121 122 switch (addr) { 123 case STM_SPI_CR1: 124 s->spi_cr1 = value; 125 return; 126 case STM_SPI_CR2: 127 qemu_log_mask(LOG_UNIMP, "%s: " \ 128 "Interrupts and DMA are not implemented\n", __func__); 129 s->spi_cr2 = value; 130 return; 131 case STM_SPI_SR: 132 /* Read only register, except for clearing the CRCERR bit, which 133 * is not supported 134 */ 135 return; 136 case STM_SPI_DR: 137 s->spi_dr = value; 138 stm32f2xx_spi_transfer(s); 139 return; 140 case STM_SPI_CRCPR: 141 qemu_log_mask(LOG_UNIMP, "%s: CRC is not implemented\n", __func__); 142 return; 143 case STM_SPI_RXCRCR: 144 qemu_log_mask(LOG_GUEST_ERROR, "%s: Read only register: " \ 145 "0x%" HWADDR_PRIx "\n", __func__, addr); 146 return; 147 case STM_SPI_TXCRCR: 148 qemu_log_mask(LOG_GUEST_ERROR, "%s: Read only register: " \ 149 "0x%" HWADDR_PRIx "\n", __func__, addr); 150 return; 151 case STM_SPI_I2SCFGR: 152 qemu_log_mask(LOG_UNIMP, "%s: " \ 153 "I2S is not implemented\n", __func__); 154 return; 155 case STM_SPI_I2SPR: 156 qemu_log_mask(LOG_UNIMP, "%s: " \ 157 "I2S is not implemented\n", __func__); 158 return; 159 default: 160 qemu_log_mask(LOG_GUEST_ERROR, 161 "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, addr); 162 } 163 } 164 165 static const MemoryRegionOps stm32f2xx_spi_ops = { 166 .read = stm32f2xx_spi_read, 167 .write = stm32f2xx_spi_write, 168 .endianness = DEVICE_NATIVE_ENDIAN, 169 }; 170 171 static const VMStateDescription vmstate_stm32f2xx_spi = { 172 .name = TYPE_STM32F2XX_SPI, 173 .version_id = 1, 174 .minimum_version_id = 1, 175 .fields = (VMStateField[]) { 176 VMSTATE_UINT32(spi_cr1, STM32F2XXSPIState), 177 VMSTATE_UINT32(spi_cr2, STM32F2XXSPIState), 178 VMSTATE_UINT32(spi_sr, STM32F2XXSPIState), 179 VMSTATE_UINT32(spi_dr, STM32F2XXSPIState), 180 VMSTATE_UINT32(spi_crcpr, STM32F2XXSPIState), 181 VMSTATE_UINT32(spi_rxcrcr, STM32F2XXSPIState), 182 VMSTATE_UINT32(spi_txcrcr, STM32F2XXSPIState), 183 VMSTATE_UINT32(spi_i2scfgr, STM32F2XXSPIState), 184 VMSTATE_UINT32(spi_i2spr, STM32F2XXSPIState), 185 VMSTATE_END_OF_LIST() 186 } 187 }; 188 189 static void stm32f2xx_spi_init(Object *obj) 190 { 191 STM32F2XXSPIState *s = STM32F2XX_SPI(obj); 192 DeviceState *dev = DEVICE(obj); 193 194 memory_region_init_io(&s->mmio, obj, &stm32f2xx_spi_ops, s, 195 TYPE_STM32F2XX_SPI, 0x400); 196 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); 197 198 sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); 199 200 s->ssi = ssi_create_bus(dev, "ssi"); 201 } 202 203 static void stm32f2xx_spi_class_init(ObjectClass *klass, void *data) 204 { 205 DeviceClass *dc = DEVICE_CLASS(klass); 206 207 dc->reset = stm32f2xx_spi_reset; 208 dc->vmsd = &vmstate_stm32f2xx_spi; 209 } 210 211 static const TypeInfo stm32f2xx_spi_info = { 212 .name = TYPE_STM32F2XX_SPI, 213 .parent = TYPE_SYS_BUS_DEVICE, 214 .instance_size = sizeof(STM32F2XXSPIState), 215 .instance_init = stm32f2xx_spi_init, 216 .class_init = stm32f2xx_spi_class_init, 217 }; 218 219 static void stm32f2xx_spi_register_types(void) 220 { 221 type_register_static(&stm32f2xx_spi_info); 222 } 223 224 type_init(stm32f2xx_spi_register_types) 225