xref: /openbmc/qemu/hw/ssi/ssi.c (revision da3c22c7)
1 /*
2  * QEMU Synchronous Serial Interface support
3  *
4  * Copyright (c) 2009 CodeSourcery.
5  * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.crosthwaite@petalogix.com)
6  * Copyright (c) 2012 PetaLogix Pty Ltd.
7  * Written by Paul Brook
8  *
9  * This code is licensed under the GNU GPL v2.
10  *
11  * Contributions after 2012-01-13 are licensed under the terms of the
12  * GNU GPL, version 2 or (at your option) any later version.
13  */
14 
15 #include "qemu/osdep.h"
16 #include "hw/qdev-properties.h"
17 #include "hw/ssi/ssi.h"
18 #include "migration/vmstate.h"
19 #include "qemu/module.h"
20 #include "qapi/error.h"
21 #include "qom/object.h"
22 
23 struct SSIBus {
24     BusState parent_obj;
25 };
26 
27 #define TYPE_SSI_BUS "SSI"
28 OBJECT_DECLARE_SIMPLE_TYPE(SSIBus, SSI_BUS)
29 
30 DeviceState *ssi_get_cs(SSIBus *bus, uint8_t cs_index)
31 {
32     BusState *b = BUS(bus);
33     BusChild *kid;
34 
35     QTAILQ_FOREACH(kid, &b->children, sibling) {
36         SSIPeripheral *kid_ssi = SSI_PERIPHERAL(kid->child);
37         if (kid_ssi->cs_index == cs_index) {
38             return kid->child;
39         }
40     }
41 
42     return NULL;
43 }
44 
45 static bool ssi_bus_check_address(BusState *b, DeviceState *dev, Error **errp)
46 {
47     SSIPeripheral *s = SSI_PERIPHERAL(dev);
48 
49     if (ssi_get_cs(SSI_BUS(b), s->cs_index)) {
50         error_setg(errp, "CS index '0x%x' in use by a %s device", s->cs_index,
51                    object_get_typename(OBJECT(dev)));
52         return false;
53     }
54 
55     return true;
56 }
57 
58 static void ssi_bus_class_init(ObjectClass *klass, void *data)
59 {
60     BusClass *k = BUS_CLASS(klass);
61 
62     k->check_address = ssi_bus_check_address;
63 }
64 
65 static const TypeInfo ssi_bus_info = {
66     .name = TYPE_SSI_BUS,
67     .parent = TYPE_BUS,
68     .instance_size = sizeof(SSIBus),
69     .class_init = ssi_bus_class_init,
70 };
71 
72 static void ssi_cs_default(void *opaque, int n, int level)
73 {
74     SSIPeripheral *s = SSI_PERIPHERAL(opaque);
75     bool cs = !!level;
76     assert(n == 0);
77     if (s->cs != cs) {
78         if (s->spc->set_cs) {
79             s->spc->set_cs(s, cs);
80         }
81     }
82     s->cs = cs;
83 }
84 
85 static uint32_t ssi_transfer_raw_default(SSIPeripheral *dev, uint32_t val)
86 {
87     SSIPeripheralClass *ssc = dev->spc;
88 
89     if ((dev->cs && ssc->cs_polarity == SSI_CS_HIGH) ||
90         (!dev->cs && ssc->cs_polarity == SSI_CS_LOW) ||
91         ssc->cs_polarity == SSI_CS_NONE) {
92         return ssc->transfer(dev, val);
93     }
94     return 0;
95 }
96 
97 static void ssi_peripheral_realize(DeviceState *dev, Error **errp)
98 {
99     SSIPeripheral *s = SSI_PERIPHERAL(dev);
100     SSIPeripheralClass *ssc = SSI_PERIPHERAL_GET_CLASS(s);
101 
102     if (ssc->transfer_raw == ssi_transfer_raw_default &&
103             ssc->cs_polarity != SSI_CS_NONE) {
104         qdev_init_gpio_in_named(dev, ssi_cs_default, SSI_GPIO_CS, 1);
105     }
106     s->spc = ssc;
107 
108     ssc->realize(s, errp);
109 }
110 
111 static Property ssi_peripheral_properties[] = {
112     DEFINE_PROP_UINT8("cs", SSIPeripheral, cs_index, 0),
113     DEFINE_PROP_END_OF_LIST(),
114 };
115 
116 static void ssi_peripheral_class_init(ObjectClass *klass, void *data)
117 {
118     SSIPeripheralClass *ssc = SSI_PERIPHERAL_CLASS(klass);
119     DeviceClass *dc = DEVICE_CLASS(klass);
120 
121     dc->realize = ssi_peripheral_realize;
122     dc->bus_type = TYPE_SSI_BUS;
123     if (!ssc->transfer_raw) {
124         ssc->transfer_raw = ssi_transfer_raw_default;
125     }
126     device_class_set_props(dc, ssi_peripheral_properties);
127 }
128 
129 static const TypeInfo ssi_peripheral_info = {
130     .name = TYPE_SSI_PERIPHERAL,
131     .parent = TYPE_DEVICE,
132     .class_init = ssi_peripheral_class_init,
133     .class_size = sizeof(SSIPeripheralClass),
134     .abstract = true,
135 };
136 
137 bool ssi_realize_and_unref(DeviceState *dev, SSIBus *bus, Error **errp)
138 {
139     return qdev_realize_and_unref(dev, &bus->parent_obj, errp);
140 }
141 
142 DeviceState *ssi_create_peripheral(SSIBus *bus, const char *name)
143 {
144     DeviceState *dev = qdev_new(name);
145 
146     ssi_realize_and_unref(dev, bus, &error_fatal);
147     return dev;
148 }
149 
150 SSIBus *ssi_create_bus(DeviceState *parent, const char *name)
151 {
152     BusState *bus;
153     bus = qbus_new(TYPE_SSI_BUS, parent, name);
154     return SSI_BUS(bus);
155 }
156 
157 uint32_t ssi_transfer(SSIBus *bus, uint32_t val)
158 {
159     BusState *b = BUS(bus);
160     BusChild *kid;
161     uint32_t r = 0;
162 
163     QTAILQ_FOREACH(kid, &b->children, sibling) {
164         SSIPeripheral *p = SSI_PERIPHERAL(kid->child);
165         r |= p->spc->transfer_raw(p, val);
166     }
167 
168     return r;
169 }
170 
171 const VMStateDescription vmstate_ssi_peripheral = {
172     .name = "SSISlave",
173     .version_id = 1,
174     .minimum_version_id = 1,
175     .fields = (VMStateField[]) {
176         VMSTATE_BOOL(cs, SSIPeripheral),
177         VMSTATE_END_OF_LIST()
178     }
179 };
180 
181 static void ssi_peripheral_register_types(void)
182 {
183     type_register_static(&ssi_bus_info);
184     type_register_static(&ssi_peripheral_info);
185 }
186 
187 type_init(ssi_peripheral_register_types)
188