1 /* 2 * QEMU Synchronous Serial Interface support 3 * 4 * Copyright (c) 2009 CodeSourcery. 5 * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.crosthwaite@petalogix.com) 6 * Copyright (c) 2012 PetaLogix Pty Ltd. 7 * Written by Paul Brook 8 * 9 * This code is licensed under the GNU GPL v2. 10 * 11 * Contributions after 2012-01-13 are licensed under the terms of the 12 * GNU GPL, version 2 or (at your option) any later version. 13 */ 14 15 #include "qemu/osdep.h" 16 #include "hw/qdev-properties.h" 17 #include "hw/ssi/ssi.h" 18 #include "migration/vmstate.h" 19 #include "qemu/module.h" 20 #include "qapi/error.h" 21 #include "qom/object.h" 22 23 struct SSIBus { 24 BusState parent_obj; 25 }; 26 27 #define TYPE_SSI_BUS "SSI" 28 OBJECT_DECLARE_SIMPLE_TYPE(SSIBus, SSI_BUS) 29 30 DeviceState *ssi_get_cs(SSIBus *bus, int addr) 31 { 32 BusState *b = BUS(bus); 33 BusChild *kid; 34 35 QTAILQ_FOREACH(kid, &b->children, sibling) { 36 SSIPeripheral *kid_ssi = SSI_PERIPHERAL(kid->child); 37 if (kid_ssi->addr == addr) { 38 return kid->child; 39 } 40 } 41 42 return NULL; 43 } 44 45 static bool ssi_bus_check_address(BusState *b, DeviceState *dev, Error **errp) 46 { 47 SSIPeripheral *s = SSI_PERIPHERAL(dev); 48 49 if (ssi_get_cs(SSI_BUS(b), s->addr)) { 50 error_setg(errp, "addr '0x%x' already in use", s->addr); 51 return false; 52 } 53 54 return true; 55 } 56 57 static void ssi_bus_class_init(ObjectClass *klass, void *data) 58 { 59 BusClass *k = BUS_CLASS(klass); 60 61 k->check_address = ssi_bus_check_address; 62 } 63 64 static const TypeInfo ssi_bus_info = { 65 .name = TYPE_SSI_BUS, 66 .parent = TYPE_BUS, 67 .instance_size = sizeof(SSIBus), 68 .class_init = ssi_bus_class_init, 69 }; 70 71 static void ssi_cs_default(void *opaque, int n, int level) 72 { 73 SSIPeripheral *s = SSI_PERIPHERAL(opaque); 74 bool cs = !!level; 75 assert(n == 0); 76 if (s->cs != cs) { 77 if (s->spc->set_cs) { 78 s->spc->set_cs(s, cs); 79 } 80 } 81 s->cs = cs; 82 } 83 84 static uint32_t ssi_transfer_raw_default(SSIPeripheral *dev, uint32_t val) 85 { 86 SSIPeripheralClass *ssc = dev->spc; 87 88 if ((dev->cs && ssc->cs_polarity == SSI_CS_HIGH) || 89 (!dev->cs && ssc->cs_polarity == SSI_CS_LOW) || 90 ssc->cs_polarity == SSI_CS_NONE) { 91 return ssc->transfer(dev, val); 92 } 93 return 0; 94 } 95 96 static void ssi_peripheral_realize(DeviceState *dev, Error **errp) 97 { 98 SSIPeripheral *s = SSI_PERIPHERAL(dev); 99 SSIPeripheralClass *ssc = SSI_PERIPHERAL_GET_CLASS(s); 100 101 if (ssc->transfer_raw == ssi_transfer_raw_default && 102 ssc->cs_polarity != SSI_CS_NONE) { 103 qdev_init_gpio_in_named(dev, ssi_cs_default, SSI_GPIO_CS, 1); 104 } 105 s->spc = ssc; 106 107 ssc->realize(s, errp); 108 } 109 110 static Property ssi_peripheral_properties[] = { 111 DEFINE_PROP_UINT32("addr", SSIPeripheral, addr, 0), 112 DEFINE_PROP_END_OF_LIST(), 113 }; 114 115 static void ssi_peripheral_class_init(ObjectClass *klass, void *data) 116 { 117 SSIPeripheralClass *ssc = SSI_PERIPHERAL_CLASS(klass); 118 DeviceClass *dc = DEVICE_CLASS(klass); 119 120 dc->realize = ssi_peripheral_realize; 121 dc->bus_type = TYPE_SSI_BUS; 122 if (!ssc->transfer_raw) { 123 ssc->transfer_raw = ssi_transfer_raw_default; 124 } 125 device_class_set_props(dc, ssi_peripheral_properties); 126 } 127 128 static const TypeInfo ssi_peripheral_info = { 129 .name = TYPE_SSI_PERIPHERAL, 130 .parent = TYPE_DEVICE, 131 .class_init = ssi_peripheral_class_init, 132 .class_size = sizeof(SSIPeripheralClass), 133 .abstract = true, 134 }; 135 136 bool ssi_realize_and_unref(DeviceState *dev, SSIBus *bus, Error **errp) 137 { 138 return qdev_realize_and_unref(dev, &bus->parent_obj, errp); 139 } 140 141 DeviceState *ssi_create_peripheral(SSIBus *bus, const char *name) 142 { 143 DeviceState *dev = qdev_new(name); 144 145 ssi_realize_and_unref(dev, bus, &error_fatal); 146 return dev; 147 } 148 149 SSIBus *ssi_create_bus(DeviceState *parent, const char *name) 150 { 151 BusState *bus; 152 bus = qbus_new(TYPE_SSI_BUS, parent, name); 153 return SSI_BUS(bus); 154 } 155 156 uint32_t ssi_transfer(SSIBus *bus, uint32_t val) 157 { 158 BusState *b = BUS(bus); 159 BusChild *kid; 160 uint32_t r = 0; 161 162 QTAILQ_FOREACH(kid, &b->children, sibling) { 163 SSIPeripheral *p = SSI_PERIPHERAL(kid->child); 164 r |= p->spc->transfer_raw(p, val); 165 } 166 167 return r; 168 } 169 170 const VMStateDescription vmstate_ssi_peripheral = { 171 .name = "SSISlave", 172 .version_id = 1, 173 .minimum_version_id = 1, 174 .fields = (VMStateField[]) { 175 VMSTATE_BOOL(cs, SSIPeripheral), 176 VMSTATE_END_OF_LIST() 177 } 178 }; 179 180 static void ssi_peripheral_register_types(void) 181 { 182 type_register_static(&ssi_bus_info); 183 type_register_static(&ssi_peripheral_info); 184 } 185 186 type_init(ssi_peripheral_register_types) 187