1 /* 2 * Arm PrimeCell PL022 Synchronous Serial Port 3 * 4 * Copyright (c) 2007 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "hw/sysbus.h" 12 #include "hw/irq.h" 13 #include "hw/ssi/pl022.h" 14 #include "hw/ssi/ssi.h" 15 #include "qemu/log.h" 16 #include "qemu/module.h" 17 18 //#define DEBUG_PL022 1 19 20 #ifdef DEBUG_PL022 21 #define DPRINTF(fmt, ...) \ 22 do { printf("pl022: " fmt , ## __VA_ARGS__); } while (0) 23 #define BADF(fmt, ...) \ 24 do { fprintf(stderr, "pl022: error: " fmt , ## __VA_ARGS__); exit(1);} while (0) 25 #else 26 #define DPRINTF(fmt, ...) do {} while(0) 27 #define BADF(fmt, ...) \ 28 do { fprintf(stderr, "pl022: error: " fmt , ## __VA_ARGS__);} while (0) 29 #endif 30 31 #define PL022_CR1_LBM 0x01 32 #define PL022_CR1_SSE 0x02 33 #define PL022_CR1_MS 0x04 34 #define PL022_CR1_SDO 0x08 35 36 #define PL022_SR_TFE 0x01 37 #define PL022_SR_TNF 0x02 38 #define PL022_SR_RNE 0x04 39 #define PL022_SR_RFF 0x08 40 #define PL022_SR_BSY 0x10 41 42 #define PL022_INT_ROR 0x01 43 #define PL022_INT_RT 0x02 44 #define PL022_INT_RX 0x04 45 #define PL022_INT_TX 0x08 46 47 static const unsigned char pl022_id[8] = 48 { 0x22, 0x10, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 }; 49 50 static void pl022_update(PL022State *s) 51 { 52 s->sr = 0; 53 if (s->tx_fifo_len == 0) 54 s->sr |= PL022_SR_TFE; 55 if (s->tx_fifo_len != 8) 56 s->sr |= PL022_SR_TNF; 57 if (s->rx_fifo_len != 0) 58 s->sr |= PL022_SR_RNE; 59 if (s->rx_fifo_len == 8) 60 s->sr |= PL022_SR_RFF; 61 if (s->tx_fifo_len) 62 s->sr |= PL022_SR_BSY; 63 s->is = 0; 64 if (s->rx_fifo_len >= 4) 65 s->is |= PL022_INT_RX; 66 if (s->tx_fifo_len <= 4) 67 s->is |= PL022_INT_TX; 68 69 qemu_set_irq(s->irq, (s->is & s->im) != 0); 70 } 71 72 static void pl022_xfer(PL022State *s) 73 { 74 int i; 75 int o; 76 int val; 77 78 if ((s->cr1 & PL022_CR1_SSE) == 0) { 79 pl022_update(s); 80 DPRINTF("Disabled\n"); 81 return; 82 } 83 84 DPRINTF("Maybe xfer %d/%d\n", s->tx_fifo_len, s->rx_fifo_len); 85 i = (s->tx_fifo_head - s->tx_fifo_len) & 7; 86 o = s->rx_fifo_head; 87 /* ??? We do not emulate the line speed. 88 This may break some applications. The are two problematic cases: 89 (a) A driver feeds data into the TX FIFO until it is full, 90 and only then drains the RX FIFO. On real hardware the CPU can 91 feed data fast enough that the RX fifo never gets chance to overflow. 92 (b) A driver transmits data, deliberately allowing the RX FIFO to 93 overflow because it ignores the RX data anyway. 94 95 We choose to support (a) by stalling the transmit engine if it would 96 cause the RX FIFO to overflow. In practice much transmit-only code 97 falls into (a) because it flushes the RX FIFO to determine when 98 the transfer has completed. */ 99 while (s->tx_fifo_len && s->rx_fifo_len < 8) { 100 DPRINTF("xfer\n"); 101 val = s->tx_fifo[i]; 102 if (s->cr1 & PL022_CR1_LBM) { 103 /* Loopback mode. */ 104 } else { 105 val = ssi_transfer(s->ssi, val); 106 } 107 s->rx_fifo[o] = val & s->bitmask; 108 i = (i + 1) & 7; 109 o = (o + 1) & 7; 110 s->tx_fifo_len--; 111 s->rx_fifo_len++; 112 } 113 s->rx_fifo_head = o; 114 pl022_update(s); 115 } 116 117 static uint64_t pl022_read(void *opaque, hwaddr offset, 118 unsigned size) 119 { 120 PL022State *s = (PL022State *)opaque; 121 int val; 122 123 if (offset >= 0xfe0 && offset < 0x1000) { 124 return pl022_id[(offset - 0xfe0) >> 2]; 125 } 126 switch (offset) { 127 case 0x00: /* CR0 */ 128 return s->cr0; 129 case 0x04: /* CR1 */ 130 return s->cr1; 131 case 0x08: /* DR */ 132 if (s->rx_fifo_len) { 133 val = s->rx_fifo[(s->rx_fifo_head - s->rx_fifo_len) & 7]; 134 DPRINTF("RX %02x\n", val); 135 s->rx_fifo_len--; 136 pl022_xfer(s); 137 } else { 138 val = 0; 139 } 140 return val; 141 case 0x0c: /* SR */ 142 return s->sr; 143 case 0x10: /* CPSR */ 144 return s->cpsr; 145 case 0x14: /* IMSC */ 146 return s->im; 147 case 0x18: /* RIS */ 148 return s->is; 149 case 0x1c: /* MIS */ 150 return s->im & s->is; 151 case 0x24: /* DMACR */ 152 /* Not implemented. */ 153 return 0; 154 default: 155 qemu_log_mask(LOG_GUEST_ERROR, 156 "pl022_read: Bad offset %x\n", (int)offset); 157 return 0; 158 } 159 } 160 161 static void pl022_write(void *opaque, hwaddr offset, 162 uint64_t value, unsigned size) 163 { 164 PL022State *s = (PL022State *)opaque; 165 166 switch (offset) { 167 case 0x00: /* CR0 */ 168 s->cr0 = value; 169 /* Clock rate and format are ignored. */ 170 s->bitmask = (1 << ((value & 15) + 1)) - 1; 171 break; 172 case 0x04: /* CR1 */ 173 s->cr1 = value; 174 if ((s->cr1 & (PL022_CR1_MS | PL022_CR1_SSE)) 175 == (PL022_CR1_MS | PL022_CR1_SSE)) { 176 BADF("SPI slave mode not implemented\n"); 177 } 178 pl022_xfer(s); 179 break; 180 case 0x08: /* DR */ 181 if (s->tx_fifo_len < 8) { 182 DPRINTF("TX %02x\n", (unsigned)value); 183 s->tx_fifo[s->tx_fifo_head] = value & s->bitmask; 184 s->tx_fifo_head = (s->tx_fifo_head + 1) & 7; 185 s->tx_fifo_len++; 186 pl022_xfer(s); 187 } 188 break; 189 case 0x10: /* CPSR */ 190 /* Prescaler. Ignored. */ 191 s->cpsr = value & 0xff; 192 break; 193 case 0x14: /* IMSC */ 194 s->im = value; 195 pl022_update(s); 196 break; 197 case 0x20: /* ICR */ 198 /* 199 * write-1-to-clear: bit 0 clears ROR, bit 1 clears RT; 200 * RX and TX interrupts cannot be cleared this way. 201 */ 202 value &= PL022_INT_ROR | PL022_INT_RT; 203 s->is &= ~value; 204 break; 205 case 0x24: /* DMACR */ 206 if (value) { 207 qemu_log_mask(LOG_UNIMP, "pl022: DMA not implemented\n"); 208 } 209 break; 210 default: 211 qemu_log_mask(LOG_GUEST_ERROR, 212 "pl022_write: Bad offset %x\n", (int)offset); 213 } 214 } 215 216 static void pl022_reset(DeviceState *dev) 217 { 218 PL022State *s = PL022(dev); 219 220 s->rx_fifo_len = 0; 221 s->tx_fifo_len = 0; 222 s->im = 0; 223 s->is = PL022_INT_TX; 224 s->sr = PL022_SR_TFE | PL022_SR_TNF; 225 } 226 227 static const MemoryRegionOps pl022_ops = { 228 .read = pl022_read, 229 .write = pl022_write, 230 .endianness = DEVICE_NATIVE_ENDIAN, 231 }; 232 233 static int pl022_post_load(void *opaque, int version_id) 234 { 235 PL022State *s = opaque; 236 237 if (s->tx_fifo_head < 0 || 238 s->tx_fifo_head >= ARRAY_SIZE(s->tx_fifo) || 239 s->rx_fifo_head < 0 || 240 s->rx_fifo_head >= ARRAY_SIZE(s->rx_fifo)) { 241 return -1; 242 } 243 return 0; 244 } 245 246 static const VMStateDescription vmstate_pl022 = { 247 .name = "pl022_ssp", 248 .version_id = 1, 249 .minimum_version_id = 1, 250 .post_load = pl022_post_load, 251 .fields = (VMStateField[]) { 252 VMSTATE_UINT32(cr0, PL022State), 253 VMSTATE_UINT32(cr1, PL022State), 254 VMSTATE_UINT32(bitmask, PL022State), 255 VMSTATE_UINT32(sr, PL022State), 256 VMSTATE_UINT32(cpsr, PL022State), 257 VMSTATE_UINT32(is, PL022State), 258 VMSTATE_UINT32(im, PL022State), 259 VMSTATE_INT32(tx_fifo_head, PL022State), 260 VMSTATE_INT32(rx_fifo_head, PL022State), 261 VMSTATE_INT32(tx_fifo_len, PL022State), 262 VMSTATE_INT32(rx_fifo_len, PL022State), 263 VMSTATE_UINT16(tx_fifo[0], PL022State), 264 VMSTATE_UINT16(rx_fifo[0], PL022State), 265 VMSTATE_UINT16(tx_fifo[1], PL022State), 266 VMSTATE_UINT16(rx_fifo[1], PL022State), 267 VMSTATE_UINT16(tx_fifo[2], PL022State), 268 VMSTATE_UINT16(rx_fifo[2], PL022State), 269 VMSTATE_UINT16(tx_fifo[3], PL022State), 270 VMSTATE_UINT16(rx_fifo[3], PL022State), 271 VMSTATE_UINT16(tx_fifo[4], PL022State), 272 VMSTATE_UINT16(rx_fifo[4], PL022State), 273 VMSTATE_UINT16(tx_fifo[5], PL022State), 274 VMSTATE_UINT16(rx_fifo[5], PL022State), 275 VMSTATE_UINT16(tx_fifo[6], PL022State), 276 VMSTATE_UINT16(rx_fifo[6], PL022State), 277 VMSTATE_UINT16(tx_fifo[7], PL022State), 278 VMSTATE_UINT16(rx_fifo[7], PL022State), 279 VMSTATE_END_OF_LIST() 280 } 281 }; 282 283 static void pl022_realize(DeviceState *dev, Error **errp) 284 { 285 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 286 PL022State *s = PL022(dev); 287 288 memory_region_init_io(&s->iomem, OBJECT(s), &pl022_ops, s, "pl022", 0x1000); 289 sysbus_init_mmio(sbd, &s->iomem); 290 sysbus_init_irq(sbd, &s->irq); 291 s->ssi = ssi_create_bus(dev, "ssi"); 292 } 293 294 static void pl022_class_init(ObjectClass *klass, void *data) 295 { 296 DeviceClass *dc = DEVICE_CLASS(klass); 297 298 dc->reset = pl022_reset; 299 dc->vmsd = &vmstate_pl022; 300 dc->realize = pl022_realize; 301 } 302 303 static const TypeInfo pl022_info = { 304 .name = TYPE_PL022, 305 .parent = TYPE_SYS_BUS_DEVICE, 306 .instance_size = sizeof(PL022State), 307 .class_init = pl022_class_init, 308 }; 309 310 static void pl022_register_types(void) 311 { 312 type_register_static(&pl022_info); 313 } 314 315 type_init(pl022_register_types) 316