1 /* 2 * Block model of SPI controller present in 3 * Microsemi's SmartFusion2 and SmartFusion SoCs. 4 * 5 * Copyright (C) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com> 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 26 #include "qemu/osdep.h" 27 #include "hw/irq.h" 28 #include "hw/ssi/mss-spi.h" 29 #include "qemu/log.h" 30 #include "qemu/module.h" 31 32 #ifndef MSS_SPI_ERR_DEBUG 33 #define MSS_SPI_ERR_DEBUG 0 34 #endif 35 36 #define DB_PRINT_L(lvl, fmt, args...) do { \ 37 if (MSS_SPI_ERR_DEBUG >= lvl) { \ 38 qemu_log("%s: " fmt "\n", __func__, ## args); \ 39 } \ 40 } while (0) 41 42 #define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args) 43 44 #define FIFO_CAPACITY 32 45 46 #define R_SPI_CONTROL 0 47 #define R_SPI_DFSIZE 1 48 #define R_SPI_STATUS 2 49 #define R_SPI_INTCLR 3 50 #define R_SPI_RX 4 51 #define R_SPI_TX 5 52 #define R_SPI_CLKGEN 6 53 #define R_SPI_SS 7 54 #define R_SPI_MIS 8 55 #define R_SPI_RIS 9 56 57 #define S_TXDONE (1 << 0) 58 #define S_RXRDY (1 << 1) 59 #define S_RXCHOVRF (1 << 2) 60 #define S_RXFIFOFUL (1 << 4) 61 #define S_RXFIFOFULNXT (1 << 5) 62 #define S_RXFIFOEMP (1 << 6) 63 #define S_RXFIFOEMPNXT (1 << 7) 64 #define S_TXFIFOFUL (1 << 8) 65 #define S_TXFIFOFULNXT (1 << 9) 66 #define S_TXFIFOEMP (1 << 10) 67 #define S_TXFIFOEMPNXT (1 << 11) 68 #define S_FRAMESTART (1 << 12) 69 #define S_SSEL (1 << 13) 70 #define S_ACTIVE (1 << 14) 71 72 #define C_ENABLE (1 << 0) 73 #define C_MODE (1 << 1) 74 #define C_INTRXDATA (1 << 4) 75 #define C_INTTXDATA (1 << 5) 76 #define C_INTRXOVRFLO (1 << 6) 77 #define C_SPS (1 << 26) 78 #define C_BIGFIFO (1 << 29) 79 #define C_RESET (1 << 31) 80 81 #define FRAMESZ_MASK 0x3F 82 #define FMCOUNT_MASK 0x00FFFF00 83 #define FMCOUNT_SHIFT 8 84 #define FRAMESZ_MAX 32 85 86 static void txfifo_reset(MSSSpiState *s) 87 { 88 fifo32_reset(&s->tx_fifo); 89 90 s->regs[R_SPI_STATUS] &= ~S_TXFIFOFUL; 91 s->regs[R_SPI_STATUS] |= S_TXFIFOEMP; 92 } 93 94 static void rxfifo_reset(MSSSpiState *s) 95 { 96 fifo32_reset(&s->rx_fifo); 97 98 s->regs[R_SPI_STATUS] &= ~S_RXFIFOFUL; 99 s->regs[R_SPI_STATUS] |= S_RXFIFOEMP; 100 } 101 102 static void set_fifodepth(MSSSpiState *s) 103 { 104 unsigned int size = s->regs[R_SPI_DFSIZE] & FRAMESZ_MASK; 105 106 if (size <= 8) { 107 s->fifo_depth = 32; 108 } else if (size <= 16) { 109 s->fifo_depth = 16; 110 } else { 111 s->fifo_depth = 8; 112 } 113 } 114 115 static void update_mis(MSSSpiState *s) 116 { 117 uint32_t reg = s->regs[R_SPI_CONTROL]; 118 uint32_t tmp; 119 120 /* 121 * form the Control register interrupt enable bits 122 * same as RIS, MIS and Interrupt clear registers for simplicity 123 */ 124 tmp = ((reg & C_INTRXOVRFLO) >> 4) | ((reg & C_INTRXDATA) >> 3) | 125 ((reg & C_INTTXDATA) >> 5); 126 s->regs[R_SPI_MIS] |= tmp & s->regs[R_SPI_RIS]; 127 } 128 129 static void spi_update_irq(MSSSpiState *s) 130 { 131 int irq; 132 133 update_mis(s); 134 irq = !!(s->regs[R_SPI_MIS]); 135 136 qemu_set_irq(s->irq, irq); 137 } 138 139 static void mss_spi_reset(DeviceState *d) 140 { 141 MSSSpiState *s = MSS_SPI(d); 142 143 memset(s->regs, 0, sizeof s->regs); 144 s->regs[R_SPI_CONTROL] = 0x80000102; 145 s->regs[R_SPI_DFSIZE] = 0x4; 146 s->regs[R_SPI_STATUS] = S_SSEL | S_TXFIFOEMP | S_RXFIFOEMP; 147 s->regs[R_SPI_CLKGEN] = 0x7; 148 s->regs[R_SPI_RIS] = 0x0; 149 150 s->fifo_depth = 4; 151 s->frame_count = 1; 152 s->enabled = false; 153 154 rxfifo_reset(s); 155 txfifo_reset(s); 156 } 157 158 static uint64_t 159 spi_read(void *opaque, hwaddr addr, unsigned int size) 160 { 161 MSSSpiState *s = opaque; 162 uint32_t ret = 0; 163 164 addr >>= 2; 165 switch (addr) { 166 case R_SPI_RX: 167 s->regs[R_SPI_STATUS] &= ~S_RXFIFOFUL; 168 s->regs[R_SPI_STATUS] &= ~S_RXCHOVRF; 169 if (fifo32_is_empty(&s->rx_fifo)) { 170 qemu_log_mask(LOG_GUEST_ERROR, 171 "%s: Reading empty RX_FIFO\n", 172 __func__); 173 } else { 174 ret = fifo32_pop(&s->rx_fifo); 175 } 176 if (fifo32_is_empty(&s->rx_fifo)) { 177 s->regs[R_SPI_STATUS] |= S_RXFIFOEMP; 178 } 179 break; 180 181 case R_SPI_MIS: 182 update_mis(s); 183 ret = s->regs[R_SPI_MIS]; 184 break; 185 186 default: 187 if (addr < ARRAY_SIZE(s->regs)) { 188 ret = s->regs[addr]; 189 } else { 190 qemu_log_mask(LOG_GUEST_ERROR, 191 "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, 192 addr * 4); 193 return ret; 194 } 195 break; 196 } 197 198 DB_PRINT("addr=0x%" HWADDR_PRIx " = 0x%" PRIx32, addr * 4, ret); 199 spi_update_irq(s); 200 return ret; 201 } 202 203 static void assert_cs(MSSSpiState *s) 204 { 205 qemu_set_irq(s->cs_line, 0); 206 } 207 208 static void deassert_cs(MSSSpiState *s) 209 { 210 qemu_set_irq(s->cs_line, 1); 211 } 212 213 static void spi_flush_txfifo(MSSSpiState *s) 214 { 215 uint32_t tx; 216 uint32_t rx; 217 bool sps = !!(s->regs[R_SPI_CONTROL] & C_SPS); 218 219 /* 220 * Chip Select(CS) is automatically controlled by this controller. 221 * If SPS bit is set in Control register then CS is asserted 222 * until all the frames set in frame count of Control register are 223 * transferred. If SPS is not set then CS pulses between frames. 224 * Note that Slave Select register specifies which of the CS line 225 * has to be controlled automatically by controller. Bits SS[7:1] are for 226 * masters in FPGA fabric since we model only Microcontroller subsystem 227 * of Smartfusion2 we control only one CS(SS[0]) line. 228 */ 229 while (!fifo32_is_empty(&s->tx_fifo) && s->frame_count) { 230 assert_cs(s); 231 232 s->regs[R_SPI_STATUS] &= ~(S_TXDONE | S_RXRDY); 233 234 tx = fifo32_pop(&s->tx_fifo); 235 DB_PRINT("data tx:0x%" PRIx32, tx); 236 rx = ssi_transfer(s->spi, tx); 237 DB_PRINT("data rx:0x%" PRIx32, rx); 238 239 if (fifo32_num_used(&s->rx_fifo) == s->fifo_depth) { 240 s->regs[R_SPI_STATUS] |= S_RXCHOVRF; 241 s->regs[R_SPI_RIS] |= S_RXCHOVRF; 242 } else { 243 fifo32_push(&s->rx_fifo, rx); 244 s->regs[R_SPI_STATUS] &= ~S_RXFIFOEMP; 245 if (fifo32_num_used(&s->rx_fifo) == (s->fifo_depth - 1)) { 246 s->regs[R_SPI_STATUS] |= S_RXFIFOFULNXT; 247 } else if (fifo32_num_used(&s->rx_fifo) == s->fifo_depth) { 248 s->regs[R_SPI_STATUS] |= S_RXFIFOFUL; 249 } 250 } 251 s->frame_count--; 252 if (!sps) { 253 deassert_cs(s); 254 } 255 } 256 257 if (!s->frame_count) { 258 s->frame_count = (s->regs[R_SPI_CONTROL] & FMCOUNT_MASK) >> 259 FMCOUNT_SHIFT; 260 deassert_cs(s); 261 s->regs[R_SPI_RIS] |= S_TXDONE | S_RXRDY; 262 s->regs[R_SPI_STATUS] |= S_TXDONE | S_RXRDY; 263 } 264 } 265 266 static void spi_write(void *opaque, hwaddr addr, 267 uint64_t val64, unsigned int size) 268 { 269 MSSSpiState *s = opaque; 270 uint32_t value = val64; 271 272 DB_PRINT("addr=0x%" HWADDR_PRIx " =0x%" PRIx32, addr, value); 273 addr >>= 2; 274 275 switch (addr) { 276 case R_SPI_TX: 277 /* adding to already full FIFO */ 278 if (fifo32_num_used(&s->tx_fifo) == s->fifo_depth) { 279 break; 280 } 281 s->regs[R_SPI_STATUS] &= ~S_TXFIFOEMP; 282 fifo32_push(&s->tx_fifo, value); 283 if (fifo32_num_used(&s->tx_fifo) == (s->fifo_depth - 1)) { 284 s->regs[R_SPI_STATUS] |= S_TXFIFOFULNXT; 285 } else if (fifo32_num_used(&s->tx_fifo) == s->fifo_depth) { 286 s->regs[R_SPI_STATUS] |= S_TXFIFOFUL; 287 } 288 if (s->enabled) { 289 spi_flush_txfifo(s); 290 } 291 break; 292 293 case R_SPI_CONTROL: 294 s->regs[R_SPI_CONTROL] = value; 295 if (value & C_BIGFIFO) { 296 set_fifodepth(s); 297 } else { 298 s->fifo_depth = 4; 299 } 300 s->enabled = value & C_ENABLE; 301 s->frame_count = (value & FMCOUNT_MASK) >> FMCOUNT_SHIFT; 302 if (value & C_RESET) { 303 mss_spi_reset(DEVICE(s)); 304 } 305 break; 306 307 case R_SPI_DFSIZE: 308 if (s->enabled) { 309 break; 310 } 311 /* 312 * [31:6] bits are reserved bits and for future use. 313 * [5:0] are for frame size. Only [5:0] bits are validated 314 * during write, [31:6] bits are untouched. 315 */ 316 if ((value & FRAMESZ_MASK) > FRAMESZ_MAX) { 317 qemu_log_mask(LOG_GUEST_ERROR, "%s: Incorrect size %u provided." 318 "Maximum frame size is %u\n", 319 __func__, value & FRAMESZ_MASK, FRAMESZ_MAX); 320 break; 321 } 322 s->regs[R_SPI_DFSIZE] = value; 323 break; 324 325 case R_SPI_INTCLR: 326 s->regs[R_SPI_INTCLR] = value; 327 if (value & S_TXDONE) { 328 s->regs[R_SPI_RIS] &= ~S_TXDONE; 329 } 330 if (value & S_RXRDY) { 331 s->regs[R_SPI_RIS] &= ~S_RXRDY; 332 } 333 if (value & S_RXCHOVRF) { 334 s->regs[R_SPI_RIS] &= ~S_RXCHOVRF; 335 } 336 break; 337 338 case R_SPI_MIS: 339 case R_SPI_STATUS: 340 case R_SPI_RIS: 341 qemu_log_mask(LOG_GUEST_ERROR, 342 "%s: Write to read only register 0x%" HWADDR_PRIx "\n", 343 __func__, addr * 4); 344 break; 345 346 default: 347 if (addr < ARRAY_SIZE(s->regs)) { 348 s->regs[addr] = value; 349 } else { 350 qemu_log_mask(LOG_GUEST_ERROR, 351 "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, 352 addr * 4); 353 } 354 break; 355 } 356 357 spi_update_irq(s); 358 } 359 360 static const MemoryRegionOps spi_ops = { 361 .read = spi_read, 362 .write = spi_write, 363 .endianness = DEVICE_NATIVE_ENDIAN, 364 .valid = { 365 .min_access_size = 1, 366 .max_access_size = 4 367 } 368 }; 369 370 static void mss_spi_realize(DeviceState *dev, Error **errp) 371 { 372 MSSSpiState *s = MSS_SPI(dev); 373 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 374 375 s->spi = ssi_create_bus(dev, "spi"); 376 377 sysbus_init_irq(sbd, &s->irq); 378 ssi_auto_connect_slaves(dev, &s->cs_line, s->spi); 379 sysbus_init_irq(sbd, &s->cs_line); 380 381 memory_region_init_io(&s->mmio, OBJECT(s), &spi_ops, s, 382 TYPE_MSS_SPI, R_SPI_MAX * 4); 383 sysbus_init_mmio(sbd, &s->mmio); 384 385 fifo32_create(&s->tx_fifo, FIFO_CAPACITY); 386 fifo32_create(&s->rx_fifo, FIFO_CAPACITY); 387 } 388 389 static const VMStateDescription vmstate_mss_spi = { 390 .name = TYPE_MSS_SPI, 391 .version_id = 1, 392 .minimum_version_id = 1, 393 .fields = (VMStateField[]) { 394 VMSTATE_FIFO32(tx_fifo, MSSSpiState), 395 VMSTATE_FIFO32(rx_fifo, MSSSpiState), 396 VMSTATE_UINT32_ARRAY(regs, MSSSpiState, R_SPI_MAX), 397 VMSTATE_END_OF_LIST() 398 } 399 }; 400 401 static void mss_spi_class_init(ObjectClass *klass, void *data) 402 { 403 DeviceClass *dc = DEVICE_CLASS(klass); 404 405 dc->realize = mss_spi_realize; 406 dc->reset = mss_spi_reset; 407 dc->vmsd = &vmstate_mss_spi; 408 } 409 410 static const TypeInfo mss_spi_info = { 411 .name = TYPE_MSS_SPI, 412 .parent = TYPE_SYS_BUS_DEVICE, 413 .instance_size = sizeof(MSSSpiState), 414 .class_init = mss_spi_class_init, 415 }; 416 417 static void mss_spi_register_types(void) 418 { 419 type_register_static(&mss_spi_info); 420 } 421 422 type_init(mss_spi_register_types) 423