1 /* 2 * IMX SPI Controller 3 * 4 * Copyright (c) 2016 Jean-Christophe Dubois <jcd@tribudubois.net> 5 * 6 * This work is licensed under the terms of the GNU GPL, version 2 or later. 7 * See the COPYING file in the top-level directory. 8 * 9 */ 10 11 #include "qemu/osdep.h" 12 #include "hw/ssi/imx_spi.h" 13 #include "sysemu/sysemu.h" 14 #include "qemu/log.h" 15 16 #ifndef DEBUG_IMX_SPI 17 #define DEBUG_IMX_SPI 0 18 #endif 19 20 #define DPRINTF(fmt, args...) \ 21 do { \ 22 if (DEBUG_IMX_SPI) { \ 23 fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX_SPI, \ 24 __func__, ##args); \ 25 } \ 26 } while (0) 27 28 static const char *imx_spi_reg_name(uint32_t reg) 29 { 30 static char unknown[20]; 31 32 switch (reg) { 33 case ECSPI_RXDATA: 34 return "ECSPI_RXDATA"; 35 case ECSPI_TXDATA: 36 return "ECSPI_TXDATA"; 37 case ECSPI_CONREG: 38 return "ECSPI_CONREG"; 39 case ECSPI_CONFIGREG: 40 return "ECSPI_CONFIGREG"; 41 case ECSPI_INTREG: 42 return "ECSPI_INTREG"; 43 case ECSPI_DMAREG: 44 return "ECSPI_DMAREG"; 45 case ECSPI_STATREG: 46 return "ECSPI_STATREG"; 47 case ECSPI_PERIODREG: 48 return "ECSPI_PERIODREG"; 49 case ECSPI_TESTREG: 50 return "ECSPI_TESTREG"; 51 case ECSPI_MSGDATA: 52 return "ECSPI_MSGDATA"; 53 default: 54 sprintf(unknown, "%d ?", reg); 55 return unknown; 56 } 57 } 58 59 static const VMStateDescription vmstate_imx_spi = { 60 .name = TYPE_IMX_SPI, 61 .version_id = 1, 62 .minimum_version_id = 1, 63 .fields = (VMStateField[]) { 64 VMSTATE_FIFO32(tx_fifo, IMXSPIState), 65 VMSTATE_FIFO32(rx_fifo, IMXSPIState), 66 VMSTATE_INT16(burst_length, IMXSPIState), 67 VMSTATE_UINT32_ARRAY(regs, IMXSPIState, ECSPI_MAX), 68 VMSTATE_END_OF_LIST() 69 }, 70 }; 71 72 static void imx_spi_txfifo_reset(IMXSPIState *s) 73 { 74 fifo32_reset(&s->tx_fifo); 75 s->regs[ECSPI_STATREG] |= ECSPI_STATREG_TE; 76 s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_TF; 77 } 78 79 static void imx_spi_rxfifo_reset(IMXSPIState *s) 80 { 81 fifo32_reset(&s->rx_fifo); 82 s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_RR; 83 s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_RF; 84 s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_RO; 85 } 86 87 static void imx_spi_update_irq(IMXSPIState *s) 88 { 89 int level; 90 91 if (fifo32_is_empty(&s->rx_fifo)) { 92 s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_RR; 93 } else { 94 s->regs[ECSPI_STATREG] |= ECSPI_STATREG_RR; 95 } 96 97 if (fifo32_is_full(&s->rx_fifo)) { 98 s->regs[ECSPI_STATREG] |= ECSPI_STATREG_RF; 99 } else { 100 s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_RF; 101 } 102 103 if (fifo32_is_empty(&s->tx_fifo)) { 104 s->regs[ECSPI_STATREG] |= ECSPI_STATREG_TE; 105 } else { 106 s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_TE; 107 } 108 109 if (fifo32_is_full(&s->tx_fifo)) { 110 s->regs[ECSPI_STATREG] |= ECSPI_STATREG_TF; 111 } else { 112 s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_TF; 113 } 114 115 level = s->regs[ECSPI_STATREG] & s->regs[ECSPI_INTREG] ? 1 : 0; 116 117 qemu_set_irq(s->irq, level); 118 119 DPRINTF("IRQ level is %d\n", level); 120 } 121 122 static uint8_t imx_spi_selected_channel(IMXSPIState *s) 123 { 124 return EXTRACT(s->regs[ECSPI_CONREG], ECSPI_CONREG_CHANNEL_SELECT); 125 } 126 127 static uint32_t imx_spi_burst_length(IMXSPIState *s) 128 { 129 return EXTRACT(s->regs[ECSPI_CONREG], ECSPI_CONREG_BURST_LENGTH) + 1; 130 } 131 132 static bool imx_spi_is_enabled(IMXSPIState *s) 133 { 134 return s->regs[ECSPI_CONREG] & ECSPI_CONREG_EN; 135 } 136 137 static bool imx_spi_channel_is_master(IMXSPIState *s) 138 { 139 uint8_t mode = EXTRACT(s->regs[ECSPI_CONREG], ECSPI_CONREG_CHANNEL_MODE); 140 141 return (mode & (1 << imx_spi_selected_channel(s))) ? true : false; 142 } 143 144 static bool imx_spi_is_multiple_master_burst(IMXSPIState *s) 145 { 146 uint8_t wave = EXTRACT(s->regs[ECSPI_CONFIGREG], ECSPI_CONFIGREG_SS_CTL); 147 148 return imx_spi_channel_is_master(s) && 149 !(s->regs[ECSPI_CONREG] & ECSPI_CONREG_SMC) && 150 ((wave & (1 << imx_spi_selected_channel(s))) ? true : false); 151 } 152 153 static void imx_spi_flush_txfifo(IMXSPIState *s) 154 { 155 uint32_t tx; 156 uint32_t rx; 157 158 DPRINTF("Begin: TX Fifo Size = %d, RX Fifo Size = %d\n", 159 fifo32_num_used(&s->tx_fifo), fifo32_num_used(&s->rx_fifo)); 160 161 while (!fifo32_is_empty(&s->tx_fifo)) { 162 int tx_burst = 0; 163 int index = 0; 164 165 if (s->burst_length <= 0) { 166 s->burst_length = imx_spi_burst_length(s); 167 168 DPRINTF("Burst length = %d\n", s->burst_length); 169 170 if (imx_spi_is_multiple_master_burst(s)) { 171 s->regs[ECSPI_CONREG] |= ECSPI_CONREG_XCH; 172 } 173 } 174 175 tx = fifo32_pop(&s->tx_fifo); 176 177 DPRINTF("data tx:0x%08x\n", tx); 178 179 tx_burst = MIN(s->burst_length, 32); 180 181 rx = 0; 182 183 while (tx_burst) { 184 uint8_t byte = tx & 0xff; 185 186 DPRINTF("writing 0x%02x\n", (uint32_t)byte); 187 188 /* We need to write one byte at a time */ 189 byte = ssi_transfer(s->bus, byte); 190 191 DPRINTF("0x%02x read\n", (uint32_t)byte); 192 193 tx = tx >> 8; 194 rx |= (byte << (index * 8)); 195 196 /* Remove 8 bits from the actual burst */ 197 tx_burst -= 8; 198 s->burst_length -= 8; 199 index++; 200 } 201 202 DPRINTF("data rx:0x%08x\n", rx); 203 204 if (fifo32_is_full(&s->rx_fifo)) { 205 s->regs[ECSPI_STATREG] |= ECSPI_STATREG_RO; 206 } else { 207 fifo32_push(&s->rx_fifo, (uint8_t)rx); 208 } 209 210 if (s->burst_length <= 0) { 211 if (!imx_spi_is_multiple_master_burst(s)) { 212 s->regs[ECSPI_STATREG] |= ECSPI_STATREG_TC; 213 break; 214 } 215 } 216 } 217 218 if (fifo32_is_empty(&s->tx_fifo)) { 219 s->regs[ECSPI_STATREG] |= ECSPI_STATREG_TC; 220 s->regs[ECSPI_CONREG] &= ~ECSPI_CONREG_XCH; 221 } 222 223 /* TODO: We should also use TDR and RDR bits */ 224 225 DPRINTF("End: TX Fifo Size = %d, RX Fifo Size = %d\n", 226 fifo32_num_used(&s->tx_fifo), fifo32_num_used(&s->rx_fifo)); 227 } 228 229 static void imx_spi_reset(DeviceState *dev) 230 { 231 IMXSPIState *s = IMX_SPI(dev); 232 233 DPRINTF("\n"); 234 235 memset(s->regs, 0, sizeof(s->regs)); 236 237 s->regs[ECSPI_STATREG] = 0x00000003; 238 239 imx_spi_rxfifo_reset(s); 240 imx_spi_txfifo_reset(s); 241 242 imx_spi_update_irq(s); 243 244 s->burst_length = 0; 245 } 246 247 static uint64_t imx_spi_read(void *opaque, hwaddr offset, unsigned size) 248 { 249 uint32_t value = 0; 250 IMXSPIState *s = opaque; 251 uint32_t index = offset >> 2; 252 253 if (index >= ECSPI_MAX) { 254 qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%" 255 HWADDR_PRIx "\n", TYPE_IMX_SPI, __func__, offset); 256 return 0; 257 } 258 259 switch (index) { 260 case ECSPI_RXDATA: 261 if (!imx_spi_is_enabled(s)) { 262 value = 0; 263 } else if (fifo32_is_empty(&s->rx_fifo)) { 264 /* value is undefined */ 265 value = 0xdeadbeef; 266 } else { 267 /* read from the RX FIFO */ 268 value = fifo32_pop(&s->rx_fifo); 269 } 270 271 break; 272 case ECSPI_TXDATA: 273 qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Trying to read from TX FIFO\n", 274 TYPE_IMX_SPI, __func__); 275 276 /* Reading from TXDATA gives 0 */ 277 278 break; 279 case ECSPI_MSGDATA: 280 qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Trying to read from MSG FIFO\n", 281 TYPE_IMX_SPI, __func__); 282 283 /* Reading from MSGDATA gives 0 */ 284 285 break; 286 default: 287 value = s->regs[index]; 288 break; 289 } 290 291 DPRINTF("reg[%s] => 0x%" PRIx32 "\n", imx_spi_reg_name(index), value); 292 293 imx_spi_update_irq(s); 294 295 return (uint64_t)value; 296 } 297 298 static void imx_spi_write(void *opaque, hwaddr offset, uint64_t value, 299 unsigned size) 300 { 301 IMXSPIState *s = opaque; 302 uint32_t index = offset >> 2; 303 uint32_t change_mask; 304 305 if (index >= ECSPI_MAX) { 306 qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%" 307 HWADDR_PRIx "\n", TYPE_IMX_SPI, __func__, offset); 308 return; 309 } 310 311 DPRINTF("reg[%s] <= 0x%" PRIx32 "\n", imx_spi_reg_name(index), 312 (uint32_t)value); 313 314 change_mask = s->regs[index] ^ value; 315 316 switch (index) { 317 case ECSPI_RXDATA: 318 qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Trying to write to RX FIFO\n", 319 TYPE_IMX_SPI, __func__); 320 break; 321 case ECSPI_TXDATA: 322 if (!imx_spi_is_enabled(s)) { 323 /* Ignore writes if device is disabled */ 324 break; 325 } else if (fifo32_is_full(&s->tx_fifo)) { 326 /* Ignore writes if queue is full */ 327 break; 328 } 329 330 fifo32_push(&s->tx_fifo, (uint32_t)value); 331 332 if (imx_spi_channel_is_master(s) && 333 (s->regs[ECSPI_CONREG] & ECSPI_CONREG_SMC)) { 334 /* 335 * Start emitting if current channel is master and SMC bit is 336 * set. 337 */ 338 imx_spi_flush_txfifo(s); 339 } 340 341 break; 342 case ECSPI_STATREG: 343 /* the RO and TC bits are write-one-to-clear */ 344 value &= ECSPI_STATREG_RO | ECSPI_STATREG_TC; 345 s->regs[ECSPI_STATREG] &= ~value; 346 347 break; 348 case ECSPI_CONREG: 349 s->regs[ECSPI_CONREG] = value; 350 351 if (!imx_spi_is_enabled(s)) { 352 /* device is disabled, so this is a reset */ 353 imx_spi_reset(DEVICE(s)); 354 return; 355 } 356 357 if (imx_spi_channel_is_master(s)) { 358 int i; 359 360 /* We are in master mode */ 361 362 for (i = 0; i < 4; i++) { 363 qemu_set_irq(s->cs_lines[i], 364 i == imx_spi_selected_channel(s) ? 0 : 1); 365 } 366 367 if ((value & change_mask & ECSPI_CONREG_SMC) && 368 !fifo32_is_empty(&s->tx_fifo)) { 369 /* SMC bit is set and TX FIFO has some slots filled in */ 370 imx_spi_flush_txfifo(s); 371 } else if ((value & change_mask & ECSPI_CONREG_XCH) && 372 !(value & ECSPI_CONREG_SMC)) { 373 /* This is a request to start emitting */ 374 imx_spi_flush_txfifo(s); 375 } 376 } 377 378 break; 379 case ECSPI_MSGDATA: 380 /* it is not clear from the spec what MSGDATA is for */ 381 /* Anyway it is not used by Linux driver */ 382 /* So for now we just ignore it */ 383 qemu_log_mask(LOG_UNIMP, 384 "[%s]%s: Trying to write to MSGDATA, ignoring\n", 385 TYPE_IMX_SPI, __func__); 386 break; 387 default: 388 s->regs[index] = value; 389 390 break; 391 } 392 393 imx_spi_update_irq(s); 394 } 395 396 static const struct MemoryRegionOps imx_spi_ops = { 397 .read = imx_spi_read, 398 .write = imx_spi_write, 399 .endianness = DEVICE_NATIVE_ENDIAN, 400 .valid = { 401 /* 402 * Our device would not work correctly if the guest was doing 403 * unaligned access. This might not be a limitation on the real 404 * device but in practice there is no reason for a guest to access 405 * this device unaligned. 406 */ 407 .min_access_size = 4, 408 .max_access_size = 4, 409 .unaligned = false, 410 }, 411 }; 412 413 static void imx_spi_realize(DeviceState *dev, Error **errp) 414 { 415 IMXSPIState *s = IMX_SPI(dev); 416 int i; 417 418 s->bus = ssi_create_bus(dev, "spi"); 419 420 memory_region_init_io(&s->iomem, OBJECT(dev), &imx_spi_ops, s, 421 TYPE_IMX_SPI, 0x1000); 422 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem); 423 sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq); 424 425 ssi_auto_connect_slaves(dev, s->cs_lines, s->bus); 426 427 for (i = 0; i < 4; ++i) { 428 sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->cs_lines[i]); 429 } 430 431 s->burst_length = 0; 432 433 fifo32_create(&s->tx_fifo, ECSPI_FIFO_SIZE); 434 fifo32_create(&s->rx_fifo, ECSPI_FIFO_SIZE); 435 } 436 437 static void imx_spi_class_init(ObjectClass *klass, void *data) 438 { 439 DeviceClass *dc = DEVICE_CLASS(klass); 440 441 dc->realize = imx_spi_realize; 442 dc->vmsd = &vmstate_imx_spi; 443 dc->reset = imx_spi_reset; 444 dc->desc = "i.MX SPI Controller"; 445 } 446 447 static const TypeInfo imx_spi_info = { 448 .name = TYPE_IMX_SPI, 449 .parent = TYPE_SYS_BUS_DEVICE, 450 .instance_size = sizeof(IMXSPIState), 451 .class_init = imx_spi_class_init, 452 }; 453 454 static void imx_spi_register_types(void) 455 { 456 type_register_static(&imx_spi_info); 457 } 458 459 type_init(imx_spi_register_types) 460