1 /* 2 * QEMU Sun4u/Sun4v System Emulator 3 * 4 * Copyright (c) 2005 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "qemu/osdep.h" 25 #include "qapi/error.h" 26 #include "qemu-common.h" 27 #include "cpu.h" 28 #include "hw/hw.h" 29 #include "hw/pci/pci.h" 30 #include "hw/pci/pci_bus.h" 31 #include "hw/pci-host/apb.h" 32 #include "hw/i386/pc.h" 33 #include "hw/char/serial.h" 34 #include "hw/timer/m48t59.h" 35 #include "hw/block/fdc.h" 36 #include "net/net.h" 37 #include "qemu/timer.h" 38 #include "sysemu/sysemu.h" 39 #include "hw/boards.h" 40 #include "hw/nvram/sun_nvram.h" 41 #include "hw/nvram/chrp_nvram.h" 42 #include "hw/sparc/sparc64.h" 43 #include "hw/nvram/fw_cfg.h" 44 #include "hw/sysbus.h" 45 #include "hw/ide.h" 46 #include "hw/ide/pci.h" 47 #include "hw/loader.h" 48 #include "elf.h" 49 #include "qemu/cutils.h" 50 51 //#define DEBUG_EBUS 52 53 #ifdef DEBUG_EBUS 54 #define EBUS_DPRINTF(fmt, ...) \ 55 do { printf("EBUS: " fmt , ## __VA_ARGS__); } while (0) 56 #else 57 #define EBUS_DPRINTF(fmt, ...) 58 #endif 59 60 #define KERNEL_LOAD_ADDR 0x00404000 61 #define CMDLINE_ADDR 0x003ff000 62 #define PROM_SIZE_MAX (4 * 1024 * 1024) 63 #define PROM_VADDR 0x000ffd00000ULL 64 #define APB_SPECIAL_BASE 0x1fe00000000ULL 65 #define APB_MEM_BASE 0x1ff00000000ULL 66 #define APB_PCI_IO_BASE (APB_SPECIAL_BASE + 0x02000000ULL) 67 #define PROM_FILENAME "openbios-sparc64" 68 #define NVRAM_SIZE 0x2000 69 #define MAX_IDE_BUS 2 70 #define BIOS_CFG_IOPORT 0x510 71 #define FW_CFG_SPARC64_WIDTH (FW_CFG_ARCH_LOCAL + 0x00) 72 #define FW_CFG_SPARC64_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01) 73 #define FW_CFG_SPARC64_DEPTH (FW_CFG_ARCH_LOCAL + 0x02) 74 75 #define IVEC_MAX 0x40 76 77 struct hwdef { 78 uint16_t machine_id; 79 uint64_t prom_addr; 80 uint64_t console_serial_base; 81 }; 82 83 typedef struct EbusState { 84 /*< private >*/ 85 PCIDevice parent_obj; 86 87 ISABus *isa_bus; 88 MemoryRegion bar0; 89 MemoryRegion bar1; 90 } EbusState; 91 92 #define TYPE_EBUS "ebus" 93 #define EBUS(obj) OBJECT_CHECK(EbusState, (obj), TYPE_EBUS) 94 95 void DMA_init(ISABus *bus, int high_page_enable) 96 { 97 } 98 99 static void fw_cfg_boot_set(void *opaque, const char *boot_device, 100 Error **errp) 101 { 102 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); 103 } 104 105 static int sun4u_NVRAM_set_params(Nvram *nvram, uint16_t NVRAM_size, 106 const char *arch, ram_addr_t RAM_size, 107 const char *boot_devices, 108 uint32_t kernel_image, uint32_t kernel_size, 109 const char *cmdline, 110 uint32_t initrd_image, uint32_t initrd_size, 111 uint32_t NVRAM_image, 112 int width, int height, int depth, 113 const uint8_t *macaddr) 114 { 115 unsigned int i; 116 int sysp_end; 117 uint8_t image[0x1ff0]; 118 NvramClass *k = NVRAM_GET_CLASS(nvram); 119 120 memset(image, '\0', sizeof(image)); 121 122 /* OpenBIOS nvram variables partition */ 123 sysp_end = chrp_nvram_create_system_partition(image, 0); 124 125 /* Free space partition */ 126 chrp_nvram_create_free_partition(&image[sysp_end], 0x1fd0 - sysp_end); 127 128 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80); 129 130 for (i = 0; i < sizeof(image); i++) { 131 (k->write)(nvram, i, image[i]); 132 } 133 134 return 0; 135 } 136 137 static uint64_t sun4u_load_kernel(const char *kernel_filename, 138 const char *initrd_filename, 139 ram_addr_t RAM_size, uint64_t *initrd_size, 140 uint64_t *initrd_addr, uint64_t *kernel_addr, 141 uint64_t *kernel_entry) 142 { 143 int linux_boot; 144 unsigned int i; 145 long kernel_size; 146 uint8_t *ptr; 147 uint64_t kernel_top; 148 149 linux_boot = (kernel_filename != NULL); 150 151 kernel_size = 0; 152 if (linux_boot) { 153 int bswap_needed; 154 155 #ifdef BSWAP_NEEDED 156 bswap_needed = 1; 157 #else 158 bswap_needed = 0; 159 #endif 160 kernel_size = load_elf(kernel_filename, NULL, NULL, kernel_entry, 161 kernel_addr, &kernel_top, 1, EM_SPARCV9, 0, 0); 162 if (kernel_size < 0) { 163 *kernel_addr = KERNEL_LOAD_ADDR; 164 *kernel_entry = KERNEL_LOAD_ADDR; 165 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR, 166 RAM_size - KERNEL_LOAD_ADDR, bswap_needed, 167 TARGET_PAGE_SIZE); 168 } 169 if (kernel_size < 0) { 170 kernel_size = load_image_targphys(kernel_filename, 171 KERNEL_LOAD_ADDR, 172 RAM_size - KERNEL_LOAD_ADDR); 173 } 174 if (kernel_size < 0) { 175 fprintf(stderr, "qemu: could not load kernel '%s'\n", 176 kernel_filename); 177 exit(1); 178 } 179 /* load initrd above kernel */ 180 *initrd_size = 0; 181 if (initrd_filename) { 182 *initrd_addr = TARGET_PAGE_ALIGN(kernel_top); 183 184 *initrd_size = load_image_targphys(initrd_filename, 185 *initrd_addr, 186 RAM_size - *initrd_addr); 187 if ((int)*initrd_size < 0) { 188 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", 189 initrd_filename); 190 exit(1); 191 } 192 } 193 if (*initrd_size > 0) { 194 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { 195 ptr = rom_ptr(*kernel_addr + i); 196 if (ldl_p(ptr + 8) == 0x48647253) { /* HdrS */ 197 stl_p(ptr + 24, *initrd_addr + *kernel_addr); 198 stl_p(ptr + 28, *initrd_size); 199 break; 200 } 201 } 202 } 203 } 204 return kernel_size; 205 } 206 207 typedef struct ResetData { 208 SPARCCPU *cpu; 209 uint64_t prom_addr; 210 } ResetData; 211 212 static void isa_irq_handler(void *opaque, int n, int level) 213 { 214 static const int isa_irq_to_ivec[16] = { 215 [1] = 0x29, /* keyboard */ 216 [4] = 0x2b, /* serial */ 217 [6] = 0x27, /* floppy */ 218 [7] = 0x22, /* parallel */ 219 [12] = 0x2a, /* mouse */ 220 }; 221 qemu_irq *irqs = opaque; 222 int ivec; 223 224 assert(n < ARRAY_SIZE(isa_irq_to_ivec)); 225 ivec = isa_irq_to_ivec[n]; 226 EBUS_DPRINTF("Set ISA IRQ %d level %d -> ivec 0x%x\n", n, level, ivec); 227 if (ivec) { 228 qemu_set_irq(irqs[ivec], level); 229 } 230 } 231 232 /* EBUS (Eight bit bus) bridge */ 233 static void ebus_realize(PCIDevice *pci_dev, Error **errp) 234 { 235 EbusState *s = EBUS(pci_dev); 236 APBState *apb; 237 qemu_irq *isa_irq; 238 239 s->isa_bus = isa_bus_new(DEVICE(pci_dev), get_system_memory(), 240 pci_address_space_io(pci_dev), errp); 241 if (!s->isa_bus) { 242 error_setg(errp, "unable to instantiate EBUS ISA bus"); 243 return; 244 } 245 246 apb = APB_DEVICE(object_resolve_path_type("", TYPE_APB, NULL)); 247 if (!apb) { 248 error_setg(errp, "unable to locate APB PCI host bridge"); 249 return; 250 } 251 252 isa_irq = qemu_allocate_irqs(isa_irq_handler, apb->pbm_irqs, 16); 253 isa_bus_irqs(s->isa_bus, isa_irq); 254 255 pci_dev->config[0x04] = 0x06; // command = bus master, pci mem 256 pci_dev->config[0x05] = 0x00; 257 pci_dev->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error 258 pci_dev->config[0x07] = 0x03; // status = medium devsel 259 pci_dev->config[0x09] = 0x00; // programming i/f 260 pci_dev->config[0x0D] = 0x0a; // latency_timer 261 262 memory_region_init_alias(&s->bar0, OBJECT(s), "bar0", get_system_io(), 263 0, 0x1000000); 264 pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0); 265 memory_region_init_alias(&s->bar1, OBJECT(s), "bar1", get_system_io(), 266 0, 0x4000); 267 pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->bar1); 268 } 269 270 static void ebus_class_init(ObjectClass *klass, void *data) 271 { 272 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 273 274 k->realize = ebus_realize; 275 k->vendor_id = PCI_VENDOR_ID_SUN; 276 k->device_id = PCI_DEVICE_ID_SUN_EBUS; 277 k->revision = 0x01; 278 k->class_id = PCI_CLASS_BRIDGE_OTHER; 279 } 280 281 static const TypeInfo ebus_info = { 282 .name = TYPE_EBUS, 283 .parent = TYPE_PCI_DEVICE, 284 .class_init = ebus_class_init, 285 .instance_size = sizeof(EbusState), 286 .interfaces = (InterfaceInfo[]) { 287 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 288 { }, 289 }, 290 }; 291 292 #define TYPE_OPENPROM "openprom" 293 #define OPENPROM(obj) OBJECT_CHECK(PROMState, (obj), TYPE_OPENPROM) 294 295 typedef struct PROMState { 296 SysBusDevice parent_obj; 297 298 MemoryRegion prom; 299 } PROMState; 300 301 static uint64_t translate_prom_address(void *opaque, uint64_t addr) 302 { 303 hwaddr *base_addr = (hwaddr *)opaque; 304 return addr + *base_addr - PROM_VADDR; 305 } 306 307 /* Boot PROM (OpenBIOS) */ 308 static void prom_init(hwaddr addr, const char *bios_name) 309 { 310 DeviceState *dev; 311 SysBusDevice *s; 312 char *filename; 313 int ret; 314 315 dev = qdev_create(NULL, TYPE_OPENPROM); 316 qdev_init_nofail(dev); 317 s = SYS_BUS_DEVICE(dev); 318 319 sysbus_mmio_map(s, 0, addr); 320 321 /* load boot prom */ 322 if (bios_name == NULL) { 323 bios_name = PROM_FILENAME; 324 } 325 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 326 if (filename) { 327 ret = load_elf(filename, translate_prom_address, &addr, 328 NULL, NULL, NULL, 1, EM_SPARCV9, 0, 0); 329 if (ret < 0 || ret > PROM_SIZE_MAX) { 330 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX); 331 } 332 g_free(filename); 333 } else { 334 ret = -1; 335 } 336 if (ret < 0 || ret > PROM_SIZE_MAX) { 337 fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name); 338 exit(1); 339 } 340 } 341 342 static void prom_init1(Object *obj) 343 { 344 PROMState *s = OPENPROM(obj); 345 SysBusDevice *dev = SYS_BUS_DEVICE(obj); 346 347 memory_region_init_ram_nomigrate(&s->prom, obj, "sun4u.prom", PROM_SIZE_MAX, 348 &error_fatal); 349 vmstate_register_ram_global(&s->prom); 350 memory_region_set_readonly(&s->prom, true); 351 sysbus_init_mmio(dev, &s->prom); 352 } 353 354 static Property prom_properties[] = { 355 {/* end of property list */}, 356 }; 357 358 static void prom_class_init(ObjectClass *klass, void *data) 359 { 360 DeviceClass *dc = DEVICE_CLASS(klass); 361 362 dc->props = prom_properties; 363 } 364 365 static const TypeInfo prom_info = { 366 .name = TYPE_OPENPROM, 367 .parent = TYPE_SYS_BUS_DEVICE, 368 .instance_size = sizeof(PROMState), 369 .class_init = prom_class_init, 370 .instance_init = prom_init1, 371 }; 372 373 374 #define TYPE_SUN4U_MEMORY "memory" 375 #define SUN4U_RAM(obj) OBJECT_CHECK(RamDevice, (obj), TYPE_SUN4U_MEMORY) 376 377 typedef struct RamDevice { 378 SysBusDevice parent_obj; 379 380 MemoryRegion ram; 381 uint64_t size; 382 } RamDevice; 383 384 /* System RAM */ 385 static void ram_realize(DeviceState *dev, Error **errp) 386 { 387 RamDevice *d = SUN4U_RAM(dev); 388 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 389 390 memory_region_init_ram_nomigrate(&d->ram, OBJECT(d), "sun4u.ram", d->size, 391 &error_fatal); 392 vmstate_register_ram_global(&d->ram); 393 sysbus_init_mmio(sbd, &d->ram); 394 } 395 396 static void ram_init(hwaddr addr, ram_addr_t RAM_size) 397 { 398 DeviceState *dev; 399 SysBusDevice *s; 400 RamDevice *d; 401 402 /* allocate RAM */ 403 dev = qdev_create(NULL, TYPE_SUN4U_MEMORY); 404 s = SYS_BUS_DEVICE(dev); 405 406 d = SUN4U_RAM(dev); 407 d->size = RAM_size; 408 qdev_init_nofail(dev); 409 410 sysbus_mmio_map(s, 0, addr); 411 } 412 413 static Property ram_properties[] = { 414 DEFINE_PROP_UINT64("size", RamDevice, size, 0), 415 DEFINE_PROP_END_OF_LIST(), 416 }; 417 418 static void ram_class_init(ObjectClass *klass, void *data) 419 { 420 DeviceClass *dc = DEVICE_CLASS(klass); 421 422 dc->realize = ram_realize; 423 dc->props = ram_properties; 424 } 425 426 static const TypeInfo ram_info = { 427 .name = TYPE_SUN4U_MEMORY, 428 .parent = TYPE_SYS_BUS_DEVICE, 429 .instance_size = sizeof(RamDevice), 430 .class_init = ram_class_init, 431 }; 432 433 static void sun4uv_init(MemoryRegion *address_space_mem, 434 MachineState *machine, 435 const struct hwdef *hwdef) 436 { 437 SPARCCPU *cpu; 438 Nvram *nvram; 439 unsigned int i; 440 uint64_t initrd_addr, initrd_size, kernel_addr, kernel_size, kernel_entry; 441 PCIBus *pci_bus, *pci_busA, *pci_busB; 442 PCIDevice *ebus, *pci_dev; 443 ISABus *isa_bus; 444 SysBusDevice *s; 445 qemu_irq *ivec_irqs; 446 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; 447 DriveInfo *fd[MAX_FD]; 448 DeviceState *dev; 449 FWCfgState *fw_cfg; 450 NICInfo *nd; 451 MACAddr macaddr; 452 bool onboard_nic; 453 454 /* init CPUs */ 455 cpu = sparc64_cpu_devinit(machine->cpu_type, hwdef->prom_addr); 456 457 /* set up devices */ 458 ram_init(0, machine->ram_size); 459 460 prom_init(hwdef->prom_addr, bios_name); 461 462 ivec_irqs = qemu_allocate_irqs(sparc64_cpu_set_ivec_irq, cpu, IVEC_MAX); 463 pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, ivec_irqs, &pci_busA, 464 &pci_busB); 465 466 /* Only in-built Simba PBMs can exist on the root bus, slot 0 on busA is 467 reserved (leaving no slots free after on-board devices) however slots 468 0-3 are free on busB */ 469 pci_bus->slot_reserved_mask = 0xfffffffc; 470 pci_busA->slot_reserved_mask = 0xfffffff1; 471 pci_busB->slot_reserved_mask = 0xfffffff0; 472 473 ebus = pci_create_multifunction(pci_busA, PCI_DEVFN(1, 0), true, TYPE_EBUS); 474 qdev_init_nofail(DEVICE(ebus)); 475 476 isa_bus = EBUS(ebus)->isa_bus; 477 478 i = 0; 479 if (hwdef->console_serial_base) { 480 serial_mm_init(address_space_mem, hwdef->console_serial_base, 0, 481 NULL, 115200, serial_hds[i], DEVICE_BIG_ENDIAN); 482 i++; 483 } 484 485 serial_hds_isa_init(isa_bus, i, MAX_SERIAL_PORTS); 486 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); 487 488 pci_dev = pci_create_simple(pci_busA, PCI_DEVFN(2, 0), "VGA"); 489 490 memset(&macaddr, 0, sizeof(MACAddr)); 491 onboard_nic = false; 492 for (i = 0; i < nb_nics; i++) { 493 nd = &nd_table[i]; 494 495 if (!nd->model || strcmp(nd->model, "sunhme") == 0) { 496 if (!onboard_nic) { 497 pci_dev = pci_create_multifunction(pci_busA, PCI_DEVFN(1, 1), 498 true, "sunhme"); 499 memcpy(&macaddr, &nd->macaddr.a, sizeof(MACAddr)); 500 onboard_nic = true; 501 } else { 502 pci_dev = pci_create(pci_busB, -1, "sunhme"); 503 } 504 } else { 505 pci_dev = pci_create(pci_busB, -1, nd->model); 506 } 507 508 dev = &pci_dev->qdev; 509 qdev_set_nic_properties(dev, nd); 510 qdev_init_nofail(dev); 511 } 512 513 /* If we don't have an onboard NIC, grab a default MAC address so that 514 * we have a valid machine id */ 515 if (!onboard_nic) { 516 qemu_macaddr_default_if_unset(&macaddr); 517 } 518 519 ide_drive_get(hd, ARRAY_SIZE(hd)); 520 521 pci_dev = pci_create(pci_busA, PCI_DEVFN(3, 0), "cmd646-ide"); 522 qdev_prop_set_uint32(&pci_dev->qdev, "secondary", 1); 523 qdev_init_nofail(&pci_dev->qdev); 524 pci_ide_create_devs(pci_dev, hd); 525 526 isa_create_simple(isa_bus, "i8042"); 527 528 /* Floppy */ 529 for(i = 0; i < MAX_FD; i++) { 530 fd[i] = drive_get(IF_FLOPPY, 0, i); 531 } 532 dev = DEVICE(isa_create(isa_bus, TYPE_ISA_FDC)); 533 if (fd[0]) { 534 qdev_prop_set_drive(dev, "driveA", blk_by_legacy_dinfo(fd[0]), 535 &error_abort); 536 } 537 if (fd[1]) { 538 qdev_prop_set_drive(dev, "driveB", blk_by_legacy_dinfo(fd[1]), 539 &error_abort); 540 } 541 qdev_prop_set_uint32(dev, "dma", -1); 542 qdev_init_nofail(dev); 543 544 /* Map NVRAM into I/O (ebus) space */ 545 nvram = m48t59_init(NULL, 0, 0, NVRAM_SIZE, 1968, 59); 546 s = SYS_BUS_DEVICE(nvram); 547 memory_region_add_subregion(pci_address_space_io(ebus), 0x2000, 548 sysbus_mmio_get_region(s, 0)); 549 550 initrd_size = 0; 551 initrd_addr = 0; 552 kernel_size = sun4u_load_kernel(machine->kernel_filename, 553 machine->initrd_filename, 554 ram_size, &initrd_size, &initrd_addr, 555 &kernel_addr, &kernel_entry); 556 557 sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", machine->ram_size, 558 machine->boot_order, 559 kernel_addr, kernel_size, 560 machine->kernel_cmdline, 561 initrd_addr, initrd_size, 562 /* XXX: need an option to load a NVRAM image */ 563 0, 564 graphic_width, graphic_height, graphic_depth, 565 (uint8_t *)&macaddr); 566 567 dev = qdev_create(NULL, TYPE_FW_CFG_IO); 568 qdev_prop_set_bit(dev, "dma_enabled", false); 569 object_property_add_child(OBJECT(ebus), TYPE_FW_CFG, OBJECT(dev), NULL); 570 qdev_init_nofail(dev); 571 memory_region_add_subregion(pci_address_space_io(ebus), BIOS_CFG_IOPORT, 572 &FW_CFG_IO(dev)->comb_iomem); 573 574 fw_cfg = FW_CFG(dev); 575 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus); 576 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus); 577 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 578 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); 579 fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_entry); 580 fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 581 if (machine->kernel_cmdline) { 582 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 583 strlen(machine->kernel_cmdline) + 1); 584 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline); 585 } else { 586 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0); 587 } 588 fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); 589 fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 590 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]); 591 592 fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_WIDTH, graphic_width); 593 fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_HEIGHT, graphic_height); 594 fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_DEPTH, graphic_depth); 595 596 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); 597 } 598 599 enum { 600 sun4u_id = 0, 601 sun4v_id = 64, 602 }; 603 604 static const struct hwdef hwdefs[] = { 605 /* Sun4u generic PC-like machine */ 606 { 607 .machine_id = sun4u_id, 608 .prom_addr = 0x1fff0000000ULL, 609 .console_serial_base = 0, 610 }, 611 /* Sun4v generic PC-like machine */ 612 { 613 .machine_id = sun4v_id, 614 .prom_addr = 0x1fff0000000ULL, 615 .console_serial_base = 0, 616 }, 617 }; 618 619 /* Sun4u hardware initialisation */ 620 static void sun4u_init(MachineState *machine) 621 { 622 sun4uv_init(get_system_memory(), machine, &hwdefs[0]); 623 } 624 625 /* Sun4v hardware initialisation */ 626 static void sun4v_init(MachineState *machine) 627 { 628 sun4uv_init(get_system_memory(), machine, &hwdefs[1]); 629 } 630 631 static void sun4u_class_init(ObjectClass *oc, void *data) 632 { 633 MachineClass *mc = MACHINE_CLASS(oc); 634 635 mc->desc = "Sun4u platform"; 636 mc->init = sun4u_init; 637 mc->block_default_type = IF_IDE; 638 mc->max_cpus = 1; /* XXX for now */ 639 mc->is_default = 1; 640 mc->default_boot_order = "c"; 641 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-UltraSparc-IIi"); 642 } 643 644 static const TypeInfo sun4u_type = { 645 .name = MACHINE_TYPE_NAME("sun4u"), 646 .parent = TYPE_MACHINE, 647 .class_init = sun4u_class_init, 648 }; 649 650 static void sun4v_class_init(ObjectClass *oc, void *data) 651 { 652 MachineClass *mc = MACHINE_CLASS(oc); 653 654 mc->desc = "Sun4v platform"; 655 mc->init = sun4v_init; 656 mc->block_default_type = IF_IDE; 657 mc->max_cpus = 1; /* XXX for now */ 658 mc->default_boot_order = "c"; 659 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Sun-UltraSparc-T1"); 660 } 661 662 static const TypeInfo sun4v_type = { 663 .name = MACHINE_TYPE_NAME("sun4v"), 664 .parent = TYPE_MACHINE, 665 .class_init = sun4v_class_init, 666 }; 667 668 static void sun4u_register_types(void) 669 { 670 type_register_static(&ebus_info); 671 type_register_static(&prom_info); 672 type_register_static(&ram_info); 673 674 type_register_static(&sun4u_type); 675 type_register_static(&sun4v_type); 676 } 677 678 type_init(sun4u_register_types) 679