1 /* 2 * QEMU Sun4u/Sun4v System Emulator 3 * 4 * Copyright (c) 2005 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "hw/hw.h" 25 #include "hw/pci/pci.h" 26 #include "hw/apb_pci.h" 27 #include "hw/pc.h" 28 #include "hw/serial.h" 29 #include "hw/nvram.h" 30 #include "hw/fdc.h" 31 #include "net/net.h" 32 #include "qemu/timer.h" 33 #include "sysemu/sysemu.h" 34 #include "hw/boards.h" 35 #include "hw/firmware_abi.h" 36 #include "hw/fw_cfg.h" 37 #include "hw/sysbus.h" 38 #include "hw/ide.h" 39 #include "hw/loader.h" 40 #include "elf.h" 41 #include "sysemu/blockdev.h" 42 #include "exec/address-spaces.h" 43 44 //#define DEBUG_IRQ 45 //#define DEBUG_EBUS 46 //#define DEBUG_TIMER 47 48 #ifdef DEBUG_IRQ 49 #define CPUIRQ_DPRINTF(fmt, ...) \ 50 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0) 51 #else 52 #define CPUIRQ_DPRINTF(fmt, ...) 53 #endif 54 55 #ifdef DEBUG_EBUS 56 #define EBUS_DPRINTF(fmt, ...) \ 57 do { printf("EBUS: " fmt , ## __VA_ARGS__); } while (0) 58 #else 59 #define EBUS_DPRINTF(fmt, ...) 60 #endif 61 62 #ifdef DEBUG_TIMER 63 #define TIMER_DPRINTF(fmt, ...) \ 64 do { printf("TIMER: " fmt , ## __VA_ARGS__); } while (0) 65 #else 66 #define TIMER_DPRINTF(fmt, ...) 67 #endif 68 69 #define KERNEL_LOAD_ADDR 0x00404000 70 #define CMDLINE_ADDR 0x003ff000 71 #define PROM_SIZE_MAX (4 * 1024 * 1024) 72 #define PROM_VADDR 0x000ffd00000ULL 73 #define APB_SPECIAL_BASE 0x1fe00000000ULL 74 #define APB_MEM_BASE 0x1ff00000000ULL 75 #define APB_PCI_IO_BASE (APB_SPECIAL_BASE + 0x02000000ULL) 76 #define PROM_FILENAME "openbios-sparc64" 77 #define NVRAM_SIZE 0x2000 78 #define MAX_IDE_BUS 2 79 #define BIOS_CFG_IOPORT 0x510 80 #define FW_CFG_SPARC64_WIDTH (FW_CFG_ARCH_LOCAL + 0x00) 81 #define FW_CFG_SPARC64_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01) 82 #define FW_CFG_SPARC64_DEPTH (FW_CFG_ARCH_LOCAL + 0x02) 83 84 #define IVEC_MAX 0x30 85 86 #define TICK_MAX 0x7fffffffffffffffULL 87 88 struct hwdef { 89 const char * const default_cpu_model; 90 uint16_t machine_id; 91 uint64_t prom_addr; 92 uint64_t console_serial_base; 93 }; 94 95 typedef struct EbusState { 96 PCIDevice pci_dev; 97 MemoryRegion bar0; 98 MemoryRegion bar1; 99 } EbusState; 100 101 int DMA_get_channel_mode (int nchan) 102 { 103 return 0; 104 } 105 int DMA_read_memory (int nchan, void *buf, int pos, int size) 106 { 107 return 0; 108 } 109 int DMA_write_memory (int nchan, void *buf, int pos, int size) 110 { 111 return 0; 112 } 113 void DMA_hold_DREQ (int nchan) {} 114 void DMA_release_DREQ (int nchan) {} 115 void DMA_schedule(int nchan) {} 116 117 void DMA_init(int high_page_enable, qemu_irq *cpu_request_exit) 118 { 119 } 120 121 void DMA_register_channel (int nchan, 122 DMA_transfer_handler transfer_handler, 123 void *opaque) 124 { 125 } 126 127 static int fw_cfg_boot_set(void *opaque, const char *boot_device) 128 { 129 fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); 130 return 0; 131 } 132 133 static int sun4u_NVRAM_set_params(M48t59State *nvram, uint16_t NVRAM_size, 134 const char *arch, ram_addr_t RAM_size, 135 const char *boot_devices, 136 uint32_t kernel_image, uint32_t kernel_size, 137 const char *cmdline, 138 uint32_t initrd_image, uint32_t initrd_size, 139 uint32_t NVRAM_image, 140 int width, int height, int depth, 141 const uint8_t *macaddr) 142 { 143 unsigned int i; 144 uint32_t start, end; 145 uint8_t image[0x1ff0]; 146 struct OpenBIOS_nvpart_v1 *part_header; 147 148 memset(image, '\0', sizeof(image)); 149 150 start = 0; 151 152 // OpenBIOS nvram variables 153 // Variable partition 154 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start]; 155 part_header->signature = OPENBIOS_PART_SYSTEM; 156 pstrcpy(part_header->name, sizeof(part_header->name), "system"); 157 158 end = start + sizeof(struct OpenBIOS_nvpart_v1); 159 for (i = 0; i < nb_prom_envs; i++) 160 end = OpenBIOS_set_var(image, end, prom_envs[i]); 161 162 // End marker 163 image[end++] = '\0'; 164 165 end = start + ((end - start + 15) & ~15); 166 OpenBIOS_finish_partition(part_header, end - start); 167 168 // free partition 169 start = end; 170 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start]; 171 part_header->signature = OPENBIOS_PART_FREE; 172 pstrcpy(part_header->name, sizeof(part_header->name), "free"); 173 174 end = 0x1fd0; 175 OpenBIOS_finish_partition(part_header, end - start); 176 177 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80); 178 179 for (i = 0; i < sizeof(image); i++) 180 m48t59_write(nvram, i, image[i]); 181 182 return 0; 183 } 184 185 static uint64_t sun4u_load_kernel(const char *kernel_filename, 186 const char *initrd_filename, 187 ram_addr_t RAM_size, uint64_t *initrd_size, 188 uint64_t *initrd_addr, uint64_t *kernel_addr, 189 uint64_t *kernel_entry) 190 { 191 int linux_boot; 192 unsigned int i; 193 long kernel_size; 194 uint8_t *ptr; 195 uint64_t kernel_top; 196 197 linux_boot = (kernel_filename != NULL); 198 199 kernel_size = 0; 200 if (linux_boot) { 201 int bswap_needed; 202 203 #ifdef BSWAP_NEEDED 204 bswap_needed = 1; 205 #else 206 bswap_needed = 0; 207 #endif 208 kernel_size = load_elf(kernel_filename, NULL, NULL, kernel_entry, 209 kernel_addr, &kernel_top, 1, ELF_MACHINE, 0); 210 if (kernel_size < 0) { 211 *kernel_addr = KERNEL_LOAD_ADDR; 212 *kernel_entry = KERNEL_LOAD_ADDR; 213 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR, 214 RAM_size - KERNEL_LOAD_ADDR, bswap_needed, 215 TARGET_PAGE_SIZE); 216 } 217 if (kernel_size < 0) { 218 kernel_size = load_image_targphys(kernel_filename, 219 KERNEL_LOAD_ADDR, 220 RAM_size - KERNEL_LOAD_ADDR); 221 } 222 if (kernel_size < 0) { 223 fprintf(stderr, "qemu: could not load kernel '%s'\n", 224 kernel_filename); 225 exit(1); 226 } 227 /* load initrd above kernel */ 228 *initrd_size = 0; 229 if (initrd_filename) { 230 *initrd_addr = TARGET_PAGE_ALIGN(kernel_top); 231 232 *initrd_size = load_image_targphys(initrd_filename, 233 *initrd_addr, 234 RAM_size - *initrd_addr); 235 if ((int)*initrd_size < 0) { 236 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", 237 initrd_filename); 238 exit(1); 239 } 240 } 241 if (*initrd_size > 0) { 242 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { 243 ptr = rom_ptr(*kernel_addr + i); 244 if (ldl_p(ptr + 8) == 0x48647253) { /* HdrS */ 245 stl_p(ptr + 24, *initrd_addr + *kernel_addr); 246 stl_p(ptr + 28, *initrd_size); 247 break; 248 } 249 } 250 } 251 } 252 return kernel_size; 253 } 254 255 void cpu_check_irqs(CPUSPARCState *env) 256 { 257 uint32_t pil = env->pil_in | 258 (env->softint & ~(SOFTINT_TIMER | SOFTINT_STIMER)); 259 260 /* TT_IVEC has a higher priority (16) than TT_EXTINT (31..17) */ 261 if (env->ivec_status & 0x20) { 262 return; 263 } 264 /* check if TM or SM in SOFTINT are set 265 setting these also causes interrupt 14 */ 266 if (env->softint & (SOFTINT_TIMER | SOFTINT_STIMER)) { 267 pil |= 1 << 14; 268 } 269 270 /* The bit corresponding to psrpil is (1<< psrpil), the next bit 271 is (2 << psrpil). */ 272 if (pil < (2 << env->psrpil)){ 273 if (env->interrupt_request & CPU_INTERRUPT_HARD) { 274 CPUIRQ_DPRINTF("Reset CPU IRQ (current interrupt %x)\n", 275 env->interrupt_index); 276 env->interrupt_index = 0; 277 cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); 278 } 279 return; 280 } 281 282 if (cpu_interrupts_enabled(env)) { 283 284 unsigned int i; 285 286 for (i = 15; i > env->psrpil; i--) { 287 if (pil & (1 << i)) { 288 int old_interrupt = env->interrupt_index; 289 int new_interrupt = TT_EXTINT | i; 290 291 if (unlikely(env->tl > 0 && cpu_tsptr(env)->tt > new_interrupt 292 && ((cpu_tsptr(env)->tt & 0x1f0) == TT_EXTINT))) { 293 CPUIRQ_DPRINTF("Not setting CPU IRQ: TL=%d " 294 "current %x >= pending %x\n", 295 env->tl, cpu_tsptr(env)->tt, new_interrupt); 296 } else if (old_interrupt != new_interrupt) { 297 env->interrupt_index = new_interrupt; 298 CPUIRQ_DPRINTF("Set CPU IRQ %d old=%x new=%x\n", i, 299 old_interrupt, new_interrupt); 300 cpu_interrupt(env, CPU_INTERRUPT_HARD); 301 } 302 break; 303 } 304 } 305 } else if (env->interrupt_request & CPU_INTERRUPT_HARD) { 306 CPUIRQ_DPRINTF("Interrupts disabled, pil=%08x pil_in=%08x softint=%08x " 307 "current interrupt %x\n", 308 pil, env->pil_in, env->softint, env->interrupt_index); 309 env->interrupt_index = 0; 310 cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); 311 } 312 } 313 314 static void cpu_kick_irq(SPARCCPU *cpu) 315 { 316 CPUSPARCState *env = &cpu->env; 317 318 env->halted = 0; 319 cpu_check_irqs(env); 320 qemu_cpu_kick(CPU(cpu)); 321 } 322 323 static void cpu_set_ivec_irq(void *opaque, int irq, int level) 324 { 325 SPARCCPU *cpu = opaque; 326 CPUSPARCState *env = &cpu->env; 327 328 if (level) { 329 if (!(env->ivec_status & 0x20)) { 330 CPUIRQ_DPRINTF("Raise IVEC IRQ %d\n", irq); 331 env->halted = 0; 332 env->interrupt_index = TT_IVEC; 333 env->ivec_status |= 0x20; 334 env->ivec_data[0] = (0x1f << 6) | irq; 335 env->ivec_data[1] = 0; 336 env->ivec_data[2] = 0; 337 cpu_interrupt(env, CPU_INTERRUPT_HARD); 338 } 339 } else { 340 if (env->ivec_status & 0x20) { 341 CPUIRQ_DPRINTF("Lower IVEC IRQ %d\n", irq); 342 env->ivec_status &= ~0x20; 343 cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); 344 } 345 } 346 } 347 348 typedef struct ResetData { 349 SPARCCPU *cpu; 350 uint64_t prom_addr; 351 } ResetData; 352 353 void cpu_put_timer(QEMUFile *f, CPUTimer *s) 354 { 355 qemu_put_be32s(f, &s->frequency); 356 qemu_put_be32s(f, &s->disabled); 357 qemu_put_be64s(f, &s->disabled_mask); 358 qemu_put_sbe64s(f, &s->clock_offset); 359 360 qemu_put_timer(f, s->qtimer); 361 } 362 363 void cpu_get_timer(QEMUFile *f, CPUTimer *s) 364 { 365 qemu_get_be32s(f, &s->frequency); 366 qemu_get_be32s(f, &s->disabled); 367 qemu_get_be64s(f, &s->disabled_mask); 368 qemu_get_sbe64s(f, &s->clock_offset); 369 370 qemu_get_timer(f, s->qtimer); 371 } 372 373 static CPUTimer *cpu_timer_create(const char *name, SPARCCPU *cpu, 374 QEMUBHFunc *cb, uint32_t frequency, 375 uint64_t disabled_mask) 376 { 377 CPUTimer *timer = g_malloc0(sizeof (CPUTimer)); 378 379 timer->name = name; 380 timer->frequency = frequency; 381 timer->disabled_mask = disabled_mask; 382 383 timer->disabled = 1; 384 timer->clock_offset = qemu_get_clock_ns(vm_clock); 385 386 timer->qtimer = qemu_new_timer_ns(vm_clock, cb, cpu); 387 388 return timer; 389 } 390 391 static void cpu_timer_reset(CPUTimer *timer) 392 { 393 timer->disabled = 1; 394 timer->clock_offset = qemu_get_clock_ns(vm_clock); 395 396 qemu_del_timer(timer->qtimer); 397 } 398 399 static void main_cpu_reset(void *opaque) 400 { 401 ResetData *s = (ResetData *)opaque; 402 CPUSPARCState *env = &s->cpu->env; 403 static unsigned int nr_resets; 404 405 cpu_reset(CPU(s->cpu)); 406 407 cpu_timer_reset(env->tick); 408 cpu_timer_reset(env->stick); 409 cpu_timer_reset(env->hstick); 410 411 env->gregs[1] = 0; // Memory start 412 env->gregs[2] = ram_size; // Memory size 413 env->gregs[3] = 0; // Machine description XXX 414 if (nr_resets++ == 0) { 415 /* Power on reset */ 416 env->pc = s->prom_addr + 0x20ULL; 417 } else { 418 env->pc = s->prom_addr + 0x40ULL; 419 } 420 env->npc = env->pc + 4; 421 } 422 423 static void tick_irq(void *opaque) 424 { 425 SPARCCPU *cpu = opaque; 426 CPUSPARCState *env = &cpu->env; 427 428 CPUTimer* timer = env->tick; 429 430 if (timer->disabled) { 431 CPUIRQ_DPRINTF("tick_irq: softint disabled\n"); 432 return; 433 } else { 434 CPUIRQ_DPRINTF("tick: fire\n"); 435 } 436 437 env->softint |= SOFTINT_TIMER; 438 cpu_kick_irq(cpu); 439 } 440 441 static void stick_irq(void *opaque) 442 { 443 SPARCCPU *cpu = opaque; 444 CPUSPARCState *env = &cpu->env; 445 446 CPUTimer* timer = env->stick; 447 448 if (timer->disabled) { 449 CPUIRQ_DPRINTF("stick_irq: softint disabled\n"); 450 return; 451 } else { 452 CPUIRQ_DPRINTF("stick: fire\n"); 453 } 454 455 env->softint |= SOFTINT_STIMER; 456 cpu_kick_irq(cpu); 457 } 458 459 static void hstick_irq(void *opaque) 460 { 461 SPARCCPU *cpu = opaque; 462 CPUSPARCState *env = &cpu->env; 463 464 CPUTimer* timer = env->hstick; 465 466 if (timer->disabled) { 467 CPUIRQ_DPRINTF("hstick_irq: softint disabled\n"); 468 return; 469 } else { 470 CPUIRQ_DPRINTF("hstick: fire\n"); 471 } 472 473 env->softint |= SOFTINT_STIMER; 474 cpu_kick_irq(cpu); 475 } 476 477 static int64_t cpu_to_timer_ticks(int64_t cpu_ticks, uint32_t frequency) 478 { 479 return muldiv64(cpu_ticks, get_ticks_per_sec(), frequency); 480 } 481 482 static uint64_t timer_to_cpu_ticks(int64_t timer_ticks, uint32_t frequency) 483 { 484 return muldiv64(timer_ticks, frequency, get_ticks_per_sec()); 485 } 486 487 void cpu_tick_set_count(CPUTimer *timer, uint64_t count) 488 { 489 uint64_t real_count = count & ~timer->disabled_mask; 490 uint64_t disabled_bit = count & timer->disabled_mask; 491 492 int64_t vm_clock_offset = qemu_get_clock_ns(vm_clock) - 493 cpu_to_timer_ticks(real_count, timer->frequency); 494 495 TIMER_DPRINTF("%s set_count count=0x%016lx (%s) p=%p\n", 496 timer->name, real_count, 497 timer->disabled?"disabled":"enabled", timer); 498 499 timer->disabled = disabled_bit ? 1 : 0; 500 timer->clock_offset = vm_clock_offset; 501 } 502 503 uint64_t cpu_tick_get_count(CPUTimer *timer) 504 { 505 uint64_t real_count = timer_to_cpu_ticks( 506 qemu_get_clock_ns(vm_clock) - timer->clock_offset, 507 timer->frequency); 508 509 TIMER_DPRINTF("%s get_count count=0x%016lx (%s) p=%p\n", 510 timer->name, real_count, 511 timer->disabled?"disabled":"enabled", timer); 512 513 if (timer->disabled) 514 real_count |= timer->disabled_mask; 515 516 return real_count; 517 } 518 519 void cpu_tick_set_limit(CPUTimer *timer, uint64_t limit) 520 { 521 int64_t now = qemu_get_clock_ns(vm_clock); 522 523 uint64_t real_limit = limit & ~timer->disabled_mask; 524 timer->disabled = (limit & timer->disabled_mask) ? 1 : 0; 525 526 int64_t expires = cpu_to_timer_ticks(real_limit, timer->frequency) + 527 timer->clock_offset; 528 529 if (expires < now) { 530 expires = now + 1; 531 } 532 533 TIMER_DPRINTF("%s set_limit limit=0x%016lx (%s) p=%p " 534 "called with limit=0x%016lx at 0x%016lx (delta=0x%016lx)\n", 535 timer->name, real_limit, 536 timer->disabled?"disabled":"enabled", 537 timer, limit, 538 timer_to_cpu_ticks(now - timer->clock_offset, 539 timer->frequency), 540 timer_to_cpu_ticks(expires - now, timer->frequency)); 541 542 if (!real_limit) { 543 TIMER_DPRINTF("%s set_limit limit=ZERO - not starting timer\n", 544 timer->name); 545 qemu_del_timer(timer->qtimer); 546 } else if (timer->disabled) { 547 qemu_del_timer(timer->qtimer); 548 } else { 549 qemu_mod_timer(timer->qtimer, expires); 550 } 551 } 552 553 static void isa_irq_handler(void *opaque, int n, int level) 554 { 555 static const int isa_irq_to_ivec[16] = { 556 [1] = 0x29, /* keyboard */ 557 [4] = 0x2b, /* serial */ 558 [6] = 0x27, /* floppy */ 559 [7] = 0x22, /* parallel */ 560 [12] = 0x2a, /* mouse */ 561 }; 562 qemu_irq *irqs = opaque; 563 int ivec; 564 565 assert(n < 16); 566 ivec = isa_irq_to_ivec[n]; 567 EBUS_DPRINTF("Set ISA IRQ %d level %d -> ivec 0x%x\n", n, level, ivec); 568 if (ivec) { 569 qemu_set_irq(irqs[ivec], level); 570 } 571 } 572 573 /* EBUS (Eight bit bus) bridge */ 574 static ISABus * 575 pci_ebus_init(PCIBus *bus, int devfn, qemu_irq *irqs) 576 { 577 qemu_irq *isa_irq; 578 PCIDevice *pci_dev; 579 ISABus *isa_bus; 580 581 pci_dev = pci_create_simple(bus, devfn, "ebus"); 582 isa_bus = DO_UPCAST(ISABus, qbus, 583 qdev_get_child_bus(&pci_dev->qdev, "isa.0")); 584 isa_irq = qemu_allocate_irqs(isa_irq_handler, irqs, 16); 585 isa_bus_irqs(isa_bus, isa_irq); 586 return isa_bus; 587 } 588 589 static int 590 pci_ebus_init1(PCIDevice *pci_dev) 591 { 592 EbusState *s = DO_UPCAST(EbusState, pci_dev, pci_dev); 593 594 isa_bus_new(&pci_dev->qdev, pci_address_space_io(pci_dev)); 595 596 pci_dev->config[0x04] = 0x06; // command = bus master, pci mem 597 pci_dev->config[0x05] = 0x00; 598 pci_dev->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error 599 pci_dev->config[0x07] = 0x03; // status = medium devsel 600 pci_dev->config[0x09] = 0x00; // programming i/f 601 pci_dev->config[0x0D] = 0x0a; // latency_timer 602 603 isa_mmio_setup(&s->bar0, 0x1000000); 604 pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0); 605 isa_mmio_setup(&s->bar1, 0x800000); 606 pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar1); 607 return 0; 608 } 609 610 static void ebus_class_init(ObjectClass *klass, void *data) 611 { 612 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 613 614 k->init = pci_ebus_init1; 615 k->vendor_id = PCI_VENDOR_ID_SUN; 616 k->device_id = PCI_DEVICE_ID_SUN_EBUS; 617 k->revision = 0x01; 618 k->class_id = PCI_CLASS_BRIDGE_OTHER; 619 } 620 621 static const TypeInfo ebus_info = { 622 .name = "ebus", 623 .parent = TYPE_PCI_DEVICE, 624 .instance_size = sizeof(EbusState), 625 .class_init = ebus_class_init, 626 }; 627 628 typedef struct PROMState { 629 SysBusDevice busdev; 630 MemoryRegion prom; 631 } PROMState; 632 633 static uint64_t translate_prom_address(void *opaque, uint64_t addr) 634 { 635 hwaddr *base_addr = (hwaddr *)opaque; 636 return addr + *base_addr - PROM_VADDR; 637 } 638 639 /* Boot PROM (OpenBIOS) */ 640 static void prom_init(hwaddr addr, const char *bios_name) 641 { 642 DeviceState *dev; 643 SysBusDevice *s; 644 char *filename; 645 int ret; 646 647 dev = qdev_create(NULL, "openprom"); 648 qdev_init_nofail(dev); 649 s = SYS_BUS_DEVICE(dev); 650 651 sysbus_mmio_map(s, 0, addr); 652 653 /* load boot prom */ 654 if (bios_name == NULL) { 655 bios_name = PROM_FILENAME; 656 } 657 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 658 if (filename) { 659 ret = load_elf(filename, translate_prom_address, &addr, 660 NULL, NULL, NULL, 1, ELF_MACHINE, 0); 661 if (ret < 0 || ret > PROM_SIZE_MAX) { 662 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX); 663 } 664 g_free(filename); 665 } else { 666 ret = -1; 667 } 668 if (ret < 0 || ret > PROM_SIZE_MAX) { 669 fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name); 670 exit(1); 671 } 672 } 673 674 static int prom_init1(SysBusDevice *dev) 675 { 676 PROMState *s = FROM_SYSBUS(PROMState, dev); 677 678 memory_region_init_ram(&s->prom, "sun4u.prom", PROM_SIZE_MAX); 679 vmstate_register_ram_global(&s->prom); 680 memory_region_set_readonly(&s->prom, true); 681 sysbus_init_mmio(dev, &s->prom); 682 return 0; 683 } 684 685 static Property prom_properties[] = { 686 {/* end of property list */}, 687 }; 688 689 static void prom_class_init(ObjectClass *klass, void *data) 690 { 691 DeviceClass *dc = DEVICE_CLASS(klass); 692 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 693 694 k->init = prom_init1; 695 dc->props = prom_properties; 696 } 697 698 static const TypeInfo prom_info = { 699 .name = "openprom", 700 .parent = TYPE_SYS_BUS_DEVICE, 701 .instance_size = sizeof(PROMState), 702 .class_init = prom_class_init, 703 }; 704 705 706 typedef struct RamDevice 707 { 708 SysBusDevice busdev; 709 MemoryRegion ram; 710 uint64_t size; 711 } RamDevice; 712 713 /* System RAM */ 714 static int ram_init1(SysBusDevice *dev) 715 { 716 RamDevice *d = FROM_SYSBUS(RamDevice, dev); 717 718 memory_region_init_ram(&d->ram, "sun4u.ram", d->size); 719 vmstate_register_ram_global(&d->ram); 720 sysbus_init_mmio(dev, &d->ram); 721 return 0; 722 } 723 724 static void ram_init(hwaddr addr, ram_addr_t RAM_size) 725 { 726 DeviceState *dev; 727 SysBusDevice *s; 728 RamDevice *d; 729 730 /* allocate RAM */ 731 dev = qdev_create(NULL, "memory"); 732 s = SYS_BUS_DEVICE(dev); 733 734 d = FROM_SYSBUS(RamDevice, s); 735 d->size = RAM_size; 736 qdev_init_nofail(dev); 737 738 sysbus_mmio_map(s, 0, addr); 739 } 740 741 static Property ram_properties[] = { 742 DEFINE_PROP_UINT64("size", RamDevice, size, 0), 743 DEFINE_PROP_END_OF_LIST(), 744 }; 745 746 static void ram_class_init(ObjectClass *klass, void *data) 747 { 748 DeviceClass *dc = DEVICE_CLASS(klass); 749 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 750 751 k->init = ram_init1; 752 dc->props = ram_properties; 753 } 754 755 static const TypeInfo ram_info = { 756 .name = "memory", 757 .parent = TYPE_SYS_BUS_DEVICE, 758 .instance_size = sizeof(RamDevice), 759 .class_init = ram_class_init, 760 }; 761 762 static SPARCCPU *cpu_devinit(const char *cpu_model, const struct hwdef *hwdef) 763 { 764 SPARCCPU *cpu; 765 CPUSPARCState *env; 766 ResetData *reset_info; 767 768 uint32_t tick_frequency = 100*1000000; 769 uint32_t stick_frequency = 100*1000000; 770 uint32_t hstick_frequency = 100*1000000; 771 772 if (cpu_model == NULL) { 773 cpu_model = hwdef->default_cpu_model; 774 } 775 cpu = cpu_sparc_init(cpu_model); 776 if (cpu == NULL) { 777 fprintf(stderr, "Unable to find Sparc CPU definition\n"); 778 exit(1); 779 } 780 env = &cpu->env; 781 782 env->tick = cpu_timer_create("tick", cpu, tick_irq, 783 tick_frequency, TICK_NPT_MASK); 784 785 env->stick = cpu_timer_create("stick", cpu, stick_irq, 786 stick_frequency, TICK_INT_DIS); 787 788 env->hstick = cpu_timer_create("hstick", cpu, hstick_irq, 789 hstick_frequency, TICK_INT_DIS); 790 791 reset_info = g_malloc0(sizeof(ResetData)); 792 reset_info->cpu = cpu; 793 reset_info->prom_addr = hwdef->prom_addr; 794 qemu_register_reset(main_cpu_reset, reset_info); 795 796 return cpu; 797 } 798 799 static void sun4uv_init(MemoryRegion *address_space_mem, 800 ram_addr_t RAM_size, 801 const char *boot_devices, 802 const char *kernel_filename, const char *kernel_cmdline, 803 const char *initrd_filename, const char *cpu_model, 804 const struct hwdef *hwdef) 805 { 806 SPARCCPU *cpu; 807 M48t59State *nvram; 808 unsigned int i; 809 uint64_t initrd_addr, initrd_size, kernel_addr, kernel_size, kernel_entry; 810 PCIBus *pci_bus, *pci_bus2, *pci_bus3; 811 ISABus *isa_bus; 812 qemu_irq *ivec_irqs, *pbm_irqs; 813 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; 814 DriveInfo *fd[MAX_FD]; 815 void *fw_cfg; 816 817 /* init CPUs */ 818 cpu = cpu_devinit(cpu_model, hwdef); 819 820 /* set up devices */ 821 ram_init(0, RAM_size); 822 823 prom_init(hwdef->prom_addr, bios_name); 824 825 ivec_irqs = qemu_allocate_irqs(cpu_set_ivec_irq, cpu, IVEC_MAX); 826 pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, ivec_irqs, &pci_bus2, 827 &pci_bus3, &pbm_irqs); 828 pci_vga_init(pci_bus); 829 830 // XXX Should be pci_bus3 831 isa_bus = pci_ebus_init(pci_bus, -1, pbm_irqs); 832 833 i = 0; 834 if (hwdef->console_serial_base) { 835 serial_mm_init(address_space_mem, hwdef->console_serial_base, 0, 836 NULL, 115200, serial_hds[i], DEVICE_BIG_ENDIAN); 837 i++; 838 } 839 for(; i < MAX_SERIAL_PORTS; i++) { 840 if (serial_hds[i]) { 841 serial_isa_init(isa_bus, i, serial_hds[i]); 842 } 843 } 844 845 for(i = 0; i < MAX_PARALLEL_PORTS; i++) { 846 if (parallel_hds[i]) { 847 parallel_init(isa_bus, i, parallel_hds[i]); 848 } 849 } 850 851 for(i = 0; i < nb_nics; i++) 852 pci_nic_init_nofail(&nd_table[i], "ne2k_pci", NULL); 853 854 ide_drive_get(hd, MAX_IDE_BUS); 855 856 pci_cmd646_ide_init(pci_bus, hd, 1); 857 858 isa_create_simple(isa_bus, "i8042"); 859 for(i = 0; i < MAX_FD; i++) { 860 fd[i] = drive_get(IF_FLOPPY, 0, i); 861 } 862 fdctrl_init_isa(isa_bus, fd); 863 nvram = m48t59_init_isa(isa_bus, 0x0074, NVRAM_SIZE, 59); 864 865 initrd_size = 0; 866 initrd_addr = 0; 867 kernel_size = sun4u_load_kernel(kernel_filename, initrd_filename, 868 ram_size, &initrd_size, &initrd_addr, 869 &kernel_addr, &kernel_entry); 870 871 sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", RAM_size, boot_devices, 872 kernel_addr, kernel_size, 873 kernel_cmdline, 874 initrd_addr, initrd_size, 875 /* XXX: need an option to load a NVRAM image */ 876 0, 877 graphic_width, graphic_height, graphic_depth, 878 (uint8_t *)&nd_table[0].macaddr); 879 880 fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0); 881 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus); 882 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1); 883 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 884 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); 885 fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_entry); 886 fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 887 if (kernel_cmdline) { 888 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 889 strlen(kernel_cmdline) + 1); 890 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline); 891 } else { 892 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0); 893 } 894 fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); 895 fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 896 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_devices[0]); 897 898 fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_WIDTH, graphic_width); 899 fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_HEIGHT, graphic_height); 900 fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_DEPTH, graphic_depth); 901 902 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); 903 } 904 905 enum { 906 sun4u_id = 0, 907 sun4v_id = 64, 908 niagara_id, 909 }; 910 911 static const struct hwdef hwdefs[] = { 912 /* Sun4u generic PC-like machine */ 913 { 914 .default_cpu_model = "TI UltraSparc IIi", 915 .machine_id = sun4u_id, 916 .prom_addr = 0x1fff0000000ULL, 917 .console_serial_base = 0, 918 }, 919 /* Sun4v generic PC-like machine */ 920 { 921 .default_cpu_model = "Sun UltraSparc T1", 922 .machine_id = sun4v_id, 923 .prom_addr = 0x1fff0000000ULL, 924 .console_serial_base = 0, 925 }, 926 /* Sun4v generic Niagara machine */ 927 { 928 .default_cpu_model = "Sun UltraSparc T1", 929 .machine_id = niagara_id, 930 .prom_addr = 0xfff0000000ULL, 931 .console_serial_base = 0xfff0c2c000ULL, 932 }, 933 }; 934 935 /* Sun4u hardware initialisation */ 936 static void sun4u_init(QEMUMachineInitArgs *args) 937 { 938 ram_addr_t RAM_size = args->ram_size; 939 const char *cpu_model = args->cpu_model; 940 const char *kernel_filename = args->kernel_filename; 941 const char *kernel_cmdline = args->kernel_cmdline; 942 const char *initrd_filename = args->initrd_filename; 943 const char *boot_devices = args->boot_device; 944 sun4uv_init(get_system_memory(), RAM_size, boot_devices, kernel_filename, 945 kernel_cmdline, initrd_filename, cpu_model, &hwdefs[0]); 946 } 947 948 /* Sun4v hardware initialisation */ 949 static void sun4v_init(QEMUMachineInitArgs *args) 950 { 951 ram_addr_t RAM_size = args->ram_size; 952 const char *cpu_model = args->cpu_model; 953 const char *kernel_filename = args->kernel_filename; 954 const char *kernel_cmdline = args->kernel_cmdline; 955 const char *initrd_filename = args->initrd_filename; 956 const char *boot_devices = args->boot_device; 957 sun4uv_init(get_system_memory(), RAM_size, boot_devices, kernel_filename, 958 kernel_cmdline, initrd_filename, cpu_model, &hwdefs[1]); 959 } 960 961 /* Niagara hardware initialisation */ 962 static void niagara_init(QEMUMachineInitArgs *args) 963 { 964 ram_addr_t RAM_size = args->ram_size; 965 const char *cpu_model = args->cpu_model; 966 const char *kernel_filename = args->kernel_filename; 967 const char *kernel_cmdline = args->kernel_cmdline; 968 const char *initrd_filename = args->initrd_filename; 969 const char *boot_devices = args->boot_device; 970 sun4uv_init(get_system_memory(), RAM_size, boot_devices, kernel_filename, 971 kernel_cmdline, initrd_filename, cpu_model, &hwdefs[2]); 972 } 973 974 static QEMUMachine sun4u_machine = { 975 .name = "sun4u", 976 .desc = "Sun4u platform", 977 .init = sun4u_init, 978 .max_cpus = 1, // XXX for now 979 .is_default = 1, 980 DEFAULT_MACHINE_OPTIONS, 981 }; 982 983 static QEMUMachine sun4v_machine = { 984 .name = "sun4v", 985 .desc = "Sun4v platform", 986 .init = sun4v_init, 987 .max_cpus = 1, // XXX for now 988 DEFAULT_MACHINE_OPTIONS, 989 }; 990 991 static QEMUMachine niagara_machine = { 992 .name = "Niagara", 993 .desc = "Sun4v platform, Niagara", 994 .init = niagara_init, 995 .max_cpus = 1, // XXX for now 996 DEFAULT_MACHINE_OPTIONS, 997 }; 998 999 static void sun4u_register_types(void) 1000 { 1001 type_register_static(&ebus_info); 1002 type_register_static(&prom_info); 1003 type_register_static(&ram_info); 1004 } 1005 1006 static void sun4u_machine_init(void) 1007 { 1008 qemu_register_machine(&sun4u_machine); 1009 qemu_register_machine(&sun4v_machine); 1010 qemu_register_machine(&niagara_machine); 1011 } 1012 1013 type_init(sun4u_register_types) 1014 machine_init(sun4u_machine_init); 1015