1 /* 2 * QEMU Sun4u/Sun4v System Emulator 3 * 4 * Copyright (c) 2005 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "qemu/osdep.h" 25 #include "hw/hw.h" 26 #include "hw/pci/pci.h" 27 #include "hw/pci-host/apb.h" 28 #include "hw/i386/pc.h" 29 #include "hw/char/serial.h" 30 #include "hw/timer/m48t59.h" 31 #include "hw/block/fdc.h" 32 #include "net/net.h" 33 #include "qemu/timer.h" 34 #include "sysemu/sysemu.h" 35 #include "hw/boards.h" 36 #include "hw/nvram/openbios_firmware_abi.h" 37 #include "hw/nvram/fw_cfg.h" 38 #include "hw/sysbus.h" 39 #include "hw/ide.h" 40 #include "hw/loader.h" 41 #include "elf.h" 42 #include "sysemu/block-backend.h" 43 #include "exec/address-spaces.h" 44 45 //#define DEBUG_IRQ 46 //#define DEBUG_EBUS 47 //#define DEBUG_TIMER 48 49 #ifdef DEBUG_IRQ 50 #define CPUIRQ_DPRINTF(fmt, ...) \ 51 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0) 52 #else 53 #define CPUIRQ_DPRINTF(fmt, ...) 54 #endif 55 56 #ifdef DEBUG_EBUS 57 #define EBUS_DPRINTF(fmt, ...) \ 58 do { printf("EBUS: " fmt , ## __VA_ARGS__); } while (0) 59 #else 60 #define EBUS_DPRINTF(fmt, ...) 61 #endif 62 63 #ifdef DEBUG_TIMER 64 #define TIMER_DPRINTF(fmt, ...) \ 65 do { printf("TIMER: " fmt , ## __VA_ARGS__); } while (0) 66 #else 67 #define TIMER_DPRINTF(fmt, ...) 68 #endif 69 70 #define KERNEL_LOAD_ADDR 0x00404000 71 #define CMDLINE_ADDR 0x003ff000 72 #define PROM_SIZE_MAX (4 * 1024 * 1024) 73 #define PROM_VADDR 0x000ffd00000ULL 74 #define APB_SPECIAL_BASE 0x1fe00000000ULL 75 #define APB_MEM_BASE 0x1ff00000000ULL 76 #define APB_PCI_IO_BASE (APB_SPECIAL_BASE + 0x02000000ULL) 77 #define PROM_FILENAME "openbios-sparc64" 78 #define NVRAM_SIZE 0x2000 79 #define MAX_IDE_BUS 2 80 #define BIOS_CFG_IOPORT 0x510 81 #define FW_CFG_SPARC64_WIDTH (FW_CFG_ARCH_LOCAL + 0x00) 82 #define FW_CFG_SPARC64_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01) 83 #define FW_CFG_SPARC64_DEPTH (FW_CFG_ARCH_LOCAL + 0x02) 84 85 #define IVEC_MAX 0x40 86 87 #define TICK_MAX 0x7fffffffffffffffULL 88 89 struct hwdef { 90 const char * const default_cpu_model; 91 uint16_t machine_id; 92 uint64_t prom_addr; 93 uint64_t console_serial_base; 94 }; 95 96 typedef struct EbusState { 97 PCIDevice pci_dev; 98 MemoryRegion bar0; 99 MemoryRegion bar1; 100 } EbusState; 101 102 int DMA_get_channel_mode (int nchan) 103 { 104 return 0; 105 } 106 int DMA_read_memory (int nchan, void *buf, int pos, int size) 107 { 108 return 0; 109 } 110 int DMA_write_memory (int nchan, void *buf, int pos, int size) 111 { 112 return 0; 113 } 114 void DMA_hold_DREQ (int nchan) {} 115 void DMA_release_DREQ (int nchan) {} 116 void DMA_schedule(void) {} 117 118 void DMA_init(ISABus *bus, int high_page_enable) 119 { 120 } 121 122 void DMA_register_channel (int nchan, 123 DMA_transfer_handler transfer_handler, 124 void *opaque) 125 { 126 } 127 128 static void fw_cfg_boot_set(void *opaque, const char *boot_device, 129 Error **errp) 130 { 131 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); 132 } 133 134 static int sun4u_NVRAM_set_params(Nvram *nvram, uint16_t NVRAM_size, 135 const char *arch, ram_addr_t RAM_size, 136 const char *boot_devices, 137 uint32_t kernel_image, uint32_t kernel_size, 138 const char *cmdline, 139 uint32_t initrd_image, uint32_t initrd_size, 140 uint32_t NVRAM_image, 141 int width, int height, int depth, 142 const uint8_t *macaddr) 143 { 144 unsigned int i; 145 uint32_t start, end; 146 uint8_t image[0x1ff0]; 147 struct OpenBIOS_nvpart_v1 *part_header; 148 NvramClass *k = NVRAM_GET_CLASS(nvram); 149 150 memset(image, '\0', sizeof(image)); 151 152 start = 0; 153 154 // OpenBIOS nvram variables 155 // Variable partition 156 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start]; 157 part_header->signature = OPENBIOS_PART_SYSTEM; 158 pstrcpy(part_header->name, sizeof(part_header->name), "system"); 159 160 end = start + sizeof(struct OpenBIOS_nvpart_v1); 161 for (i = 0; i < nb_prom_envs; i++) 162 end = OpenBIOS_set_var(image, end, prom_envs[i]); 163 164 // End marker 165 image[end++] = '\0'; 166 167 end = start + ((end - start + 15) & ~15); 168 OpenBIOS_finish_partition(part_header, end - start); 169 170 // free partition 171 start = end; 172 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start]; 173 part_header->signature = OPENBIOS_PART_FREE; 174 pstrcpy(part_header->name, sizeof(part_header->name), "free"); 175 176 end = 0x1fd0; 177 OpenBIOS_finish_partition(part_header, end - start); 178 179 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80); 180 181 for (i = 0; i < sizeof(image); i++) { 182 (k->write)(nvram, i, image[i]); 183 } 184 185 return 0; 186 } 187 188 static uint64_t sun4u_load_kernel(const char *kernel_filename, 189 const char *initrd_filename, 190 ram_addr_t RAM_size, uint64_t *initrd_size, 191 uint64_t *initrd_addr, uint64_t *kernel_addr, 192 uint64_t *kernel_entry) 193 { 194 int linux_boot; 195 unsigned int i; 196 long kernel_size; 197 uint8_t *ptr; 198 uint64_t kernel_top; 199 200 linux_boot = (kernel_filename != NULL); 201 202 kernel_size = 0; 203 if (linux_boot) { 204 int bswap_needed; 205 206 #ifdef BSWAP_NEEDED 207 bswap_needed = 1; 208 #else 209 bswap_needed = 0; 210 #endif 211 kernel_size = load_elf(kernel_filename, NULL, NULL, kernel_entry, 212 kernel_addr, &kernel_top, 1, EM_SPARCV9, 0); 213 if (kernel_size < 0) { 214 *kernel_addr = KERNEL_LOAD_ADDR; 215 *kernel_entry = KERNEL_LOAD_ADDR; 216 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR, 217 RAM_size - KERNEL_LOAD_ADDR, bswap_needed, 218 TARGET_PAGE_SIZE); 219 } 220 if (kernel_size < 0) { 221 kernel_size = load_image_targphys(kernel_filename, 222 KERNEL_LOAD_ADDR, 223 RAM_size - KERNEL_LOAD_ADDR); 224 } 225 if (kernel_size < 0) { 226 fprintf(stderr, "qemu: could not load kernel '%s'\n", 227 kernel_filename); 228 exit(1); 229 } 230 /* load initrd above kernel */ 231 *initrd_size = 0; 232 if (initrd_filename) { 233 *initrd_addr = TARGET_PAGE_ALIGN(kernel_top); 234 235 *initrd_size = load_image_targphys(initrd_filename, 236 *initrd_addr, 237 RAM_size - *initrd_addr); 238 if ((int)*initrd_size < 0) { 239 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", 240 initrd_filename); 241 exit(1); 242 } 243 } 244 if (*initrd_size > 0) { 245 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { 246 ptr = rom_ptr(*kernel_addr + i); 247 if (ldl_p(ptr + 8) == 0x48647253) { /* HdrS */ 248 stl_p(ptr + 24, *initrd_addr + *kernel_addr); 249 stl_p(ptr + 28, *initrd_size); 250 break; 251 } 252 } 253 } 254 } 255 return kernel_size; 256 } 257 258 void cpu_check_irqs(CPUSPARCState *env) 259 { 260 CPUState *cs; 261 uint32_t pil = env->pil_in | 262 (env->softint & ~(SOFTINT_TIMER | SOFTINT_STIMER)); 263 264 /* TT_IVEC has a higher priority (16) than TT_EXTINT (31..17) */ 265 if (env->ivec_status & 0x20) { 266 return; 267 } 268 cs = CPU(sparc_env_get_cpu(env)); 269 /* check if TM or SM in SOFTINT are set 270 setting these also causes interrupt 14 */ 271 if (env->softint & (SOFTINT_TIMER | SOFTINT_STIMER)) { 272 pil |= 1 << 14; 273 } 274 275 /* The bit corresponding to psrpil is (1<< psrpil), the next bit 276 is (2 << psrpil). */ 277 if (pil < (2 << env->psrpil)){ 278 if (cs->interrupt_request & CPU_INTERRUPT_HARD) { 279 CPUIRQ_DPRINTF("Reset CPU IRQ (current interrupt %x)\n", 280 env->interrupt_index); 281 env->interrupt_index = 0; 282 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 283 } 284 return; 285 } 286 287 if (cpu_interrupts_enabled(env)) { 288 289 unsigned int i; 290 291 for (i = 15; i > env->psrpil; i--) { 292 if (pil & (1 << i)) { 293 int old_interrupt = env->interrupt_index; 294 int new_interrupt = TT_EXTINT | i; 295 296 if (unlikely(env->tl > 0 && cpu_tsptr(env)->tt > new_interrupt 297 && ((cpu_tsptr(env)->tt & 0x1f0) == TT_EXTINT))) { 298 CPUIRQ_DPRINTF("Not setting CPU IRQ: TL=%d " 299 "current %x >= pending %x\n", 300 env->tl, cpu_tsptr(env)->tt, new_interrupt); 301 } else if (old_interrupt != new_interrupt) { 302 env->interrupt_index = new_interrupt; 303 CPUIRQ_DPRINTF("Set CPU IRQ %d old=%x new=%x\n", i, 304 old_interrupt, new_interrupt); 305 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 306 } 307 break; 308 } 309 } 310 } else if (cs->interrupt_request & CPU_INTERRUPT_HARD) { 311 CPUIRQ_DPRINTF("Interrupts disabled, pil=%08x pil_in=%08x softint=%08x " 312 "current interrupt %x\n", 313 pil, env->pil_in, env->softint, env->interrupt_index); 314 env->interrupt_index = 0; 315 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 316 } 317 } 318 319 static void cpu_kick_irq(SPARCCPU *cpu) 320 { 321 CPUState *cs = CPU(cpu); 322 CPUSPARCState *env = &cpu->env; 323 324 cs->halted = 0; 325 cpu_check_irqs(env); 326 qemu_cpu_kick(cs); 327 } 328 329 static void cpu_set_ivec_irq(void *opaque, int irq, int level) 330 { 331 SPARCCPU *cpu = opaque; 332 CPUSPARCState *env = &cpu->env; 333 CPUState *cs; 334 335 if (level) { 336 if (!(env->ivec_status & 0x20)) { 337 CPUIRQ_DPRINTF("Raise IVEC IRQ %d\n", irq); 338 cs = CPU(cpu); 339 cs->halted = 0; 340 env->interrupt_index = TT_IVEC; 341 env->ivec_status |= 0x20; 342 env->ivec_data[0] = (0x1f << 6) | irq; 343 env->ivec_data[1] = 0; 344 env->ivec_data[2] = 0; 345 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 346 } 347 } else { 348 if (env->ivec_status & 0x20) { 349 CPUIRQ_DPRINTF("Lower IVEC IRQ %d\n", irq); 350 cs = CPU(cpu); 351 env->ivec_status &= ~0x20; 352 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 353 } 354 } 355 } 356 357 typedef struct ResetData { 358 SPARCCPU *cpu; 359 uint64_t prom_addr; 360 } ResetData; 361 362 static CPUTimer *cpu_timer_create(const char *name, SPARCCPU *cpu, 363 QEMUBHFunc *cb, uint32_t frequency, 364 uint64_t disabled_mask, uint64_t npt_mask) 365 { 366 CPUTimer *timer = g_malloc0(sizeof (CPUTimer)); 367 368 timer->name = name; 369 timer->frequency = frequency; 370 timer->disabled_mask = disabled_mask; 371 timer->npt_mask = npt_mask; 372 373 timer->disabled = 1; 374 timer->npt = 1; 375 timer->clock_offset = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 376 377 timer->qtimer = timer_new_ns(QEMU_CLOCK_VIRTUAL, cb, cpu); 378 379 return timer; 380 } 381 382 static void cpu_timer_reset(CPUTimer *timer) 383 { 384 timer->disabled = 1; 385 timer->clock_offset = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 386 387 timer_del(timer->qtimer); 388 } 389 390 static void main_cpu_reset(void *opaque) 391 { 392 ResetData *s = (ResetData *)opaque; 393 CPUSPARCState *env = &s->cpu->env; 394 static unsigned int nr_resets; 395 396 cpu_reset(CPU(s->cpu)); 397 398 cpu_timer_reset(env->tick); 399 cpu_timer_reset(env->stick); 400 cpu_timer_reset(env->hstick); 401 402 env->gregs[1] = 0; // Memory start 403 env->gregs[2] = ram_size; // Memory size 404 env->gregs[3] = 0; // Machine description XXX 405 if (nr_resets++ == 0) { 406 /* Power on reset */ 407 env->pc = s->prom_addr + 0x20ULL; 408 } else { 409 env->pc = s->prom_addr + 0x40ULL; 410 } 411 env->npc = env->pc + 4; 412 } 413 414 static void tick_irq(void *opaque) 415 { 416 SPARCCPU *cpu = opaque; 417 CPUSPARCState *env = &cpu->env; 418 419 CPUTimer* timer = env->tick; 420 421 if (timer->disabled) { 422 CPUIRQ_DPRINTF("tick_irq: softint disabled\n"); 423 return; 424 } else { 425 CPUIRQ_DPRINTF("tick: fire\n"); 426 } 427 428 env->softint |= SOFTINT_TIMER; 429 cpu_kick_irq(cpu); 430 } 431 432 static void stick_irq(void *opaque) 433 { 434 SPARCCPU *cpu = opaque; 435 CPUSPARCState *env = &cpu->env; 436 437 CPUTimer* timer = env->stick; 438 439 if (timer->disabled) { 440 CPUIRQ_DPRINTF("stick_irq: softint disabled\n"); 441 return; 442 } else { 443 CPUIRQ_DPRINTF("stick: fire\n"); 444 } 445 446 env->softint |= SOFTINT_STIMER; 447 cpu_kick_irq(cpu); 448 } 449 450 static void hstick_irq(void *opaque) 451 { 452 SPARCCPU *cpu = opaque; 453 CPUSPARCState *env = &cpu->env; 454 455 CPUTimer* timer = env->hstick; 456 457 if (timer->disabled) { 458 CPUIRQ_DPRINTF("hstick_irq: softint disabled\n"); 459 return; 460 } else { 461 CPUIRQ_DPRINTF("hstick: fire\n"); 462 } 463 464 env->softint |= SOFTINT_STIMER; 465 cpu_kick_irq(cpu); 466 } 467 468 static int64_t cpu_to_timer_ticks(int64_t cpu_ticks, uint32_t frequency) 469 { 470 return muldiv64(cpu_ticks, get_ticks_per_sec(), frequency); 471 } 472 473 static uint64_t timer_to_cpu_ticks(int64_t timer_ticks, uint32_t frequency) 474 { 475 return muldiv64(timer_ticks, frequency, get_ticks_per_sec()); 476 } 477 478 void cpu_tick_set_count(CPUTimer *timer, uint64_t count) 479 { 480 uint64_t real_count = count & ~timer->npt_mask; 481 uint64_t npt_bit = count & timer->npt_mask; 482 483 int64_t vm_clock_offset = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - 484 cpu_to_timer_ticks(real_count, timer->frequency); 485 486 TIMER_DPRINTF("%s set_count count=0x%016lx (npt %s) p=%p\n", 487 timer->name, real_count, 488 timer->npt ? "disabled" : "enabled", timer); 489 490 timer->npt = npt_bit ? 1 : 0; 491 timer->clock_offset = vm_clock_offset; 492 } 493 494 uint64_t cpu_tick_get_count(CPUTimer *timer) 495 { 496 uint64_t real_count = timer_to_cpu_ticks( 497 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - timer->clock_offset, 498 timer->frequency); 499 500 TIMER_DPRINTF("%s get_count count=0x%016lx (npt %s) p=%p\n", 501 timer->name, real_count, 502 timer->npt ? "disabled" : "enabled", timer); 503 504 if (timer->npt) { 505 real_count |= timer->npt_mask; 506 } 507 508 return real_count; 509 } 510 511 void cpu_tick_set_limit(CPUTimer *timer, uint64_t limit) 512 { 513 int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 514 515 uint64_t real_limit = limit & ~timer->disabled_mask; 516 timer->disabled = (limit & timer->disabled_mask) ? 1 : 0; 517 518 int64_t expires = cpu_to_timer_ticks(real_limit, timer->frequency) + 519 timer->clock_offset; 520 521 if (expires < now) { 522 expires = now + 1; 523 } 524 525 TIMER_DPRINTF("%s set_limit limit=0x%016lx (%s) p=%p " 526 "called with limit=0x%016lx at 0x%016lx (delta=0x%016lx)\n", 527 timer->name, real_limit, 528 timer->disabled?"disabled":"enabled", 529 timer, limit, 530 timer_to_cpu_ticks(now - timer->clock_offset, 531 timer->frequency), 532 timer_to_cpu_ticks(expires - now, timer->frequency)); 533 534 if (!real_limit) { 535 TIMER_DPRINTF("%s set_limit limit=ZERO - not starting timer\n", 536 timer->name); 537 timer_del(timer->qtimer); 538 } else if (timer->disabled) { 539 timer_del(timer->qtimer); 540 } else { 541 timer_mod(timer->qtimer, expires); 542 } 543 } 544 545 static void isa_irq_handler(void *opaque, int n, int level) 546 { 547 static const int isa_irq_to_ivec[16] = { 548 [1] = 0x29, /* keyboard */ 549 [4] = 0x2b, /* serial */ 550 [6] = 0x27, /* floppy */ 551 [7] = 0x22, /* parallel */ 552 [12] = 0x2a, /* mouse */ 553 }; 554 qemu_irq *irqs = opaque; 555 int ivec; 556 557 assert(n < 16); 558 ivec = isa_irq_to_ivec[n]; 559 EBUS_DPRINTF("Set ISA IRQ %d level %d -> ivec 0x%x\n", n, level, ivec); 560 if (ivec) { 561 qemu_set_irq(irqs[ivec], level); 562 } 563 } 564 565 /* EBUS (Eight bit bus) bridge */ 566 static ISABus * 567 pci_ebus_init(PCIBus *bus, int devfn, qemu_irq *irqs) 568 { 569 qemu_irq *isa_irq; 570 PCIDevice *pci_dev; 571 ISABus *isa_bus; 572 573 pci_dev = pci_create_simple(bus, devfn, "ebus"); 574 isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(pci_dev), "isa.0")); 575 isa_irq = qemu_allocate_irqs(isa_irq_handler, irqs, 16); 576 isa_bus_irqs(isa_bus, isa_irq); 577 return isa_bus; 578 } 579 580 static void pci_ebus_realize(PCIDevice *pci_dev, Error **errp) 581 { 582 EbusState *s = DO_UPCAST(EbusState, pci_dev, pci_dev); 583 584 if (!isa_bus_new(DEVICE(pci_dev), get_system_memory(), 585 pci_address_space_io(pci_dev), errp)) { 586 return; 587 } 588 589 pci_dev->config[0x04] = 0x06; // command = bus master, pci mem 590 pci_dev->config[0x05] = 0x00; 591 pci_dev->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error 592 pci_dev->config[0x07] = 0x03; // status = medium devsel 593 pci_dev->config[0x09] = 0x00; // programming i/f 594 pci_dev->config[0x0D] = 0x0a; // latency_timer 595 596 memory_region_init_alias(&s->bar0, OBJECT(s), "bar0", get_system_io(), 597 0, 0x1000000); 598 pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0); 599 memory_region_init_alias(&s->bar1, OBJECT(s), "bar1", get_system_io(), 600 0, 0x4000); 601 pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->bar1); 602 } 603 604 static void ebus_class_init(ObjectClass *klass, void *data) 605 { 606 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 607 608 k->realize = pci_ebus_realize; 609 k->vendor_id = PCI_VENDOR_ID_SUN; 610 k->device_id = PCI_DEVICE_ID_SUN_EBUS; 611 k->revision = 0x01; 612 k->class_id = PCI_CLASS_BRIDGE_OTHER; 613 } 614 615 static const TypeInfo ebus_info = { 616 .name = "ebus", 617 .parent = TYPE_PCI_DEVICE, 618 .instance_size = sizeof(EbusState), 619 .class_init = ebus_class_init, 620 }; 621 622 #define TYPE_OPENPROM "openprom" 623 #define OPENPROM(obj) OBJECT_CHECK(PROMState, (obj), TYPE_OPENPROM) 624 625 typedef struct PROMState { 626 SysBusDevice parent_obj; 627 628 MemoryRegion prom; 629 } PROMState; 630 631 static uint64_t translate_prom_address(void *opaque, uint64_t addr) 632 { 633 hwaddr *base_addr = (hwaddr *)opaque; 634 return addr + *base_addr - PROM_VADDR; 635 } 636 637 /* Boot PROM (OpenBIOS) */ 638 static void prom_init(hwaddr addr, const char *bios_name) 639 { 640 DeviceState *dev; 641 SysBusDevice *s; 642 char *filename; 643 int ret; 644 645 dev = qdev_create(NULL, TYPE_OPENPROM); 646 qdev_init_nofail(dev); 647 s = SYS_BUS_DEVICE(dev); 648 649 sysbus_mmio_map(s, 0, addr); 650 651 /* load boot prom */ 652 if (bios_name == NULL) { 653 bios_name = PROM_FILENAME; 654 } 655 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 656 if (filename) { 657 ret = load_elf(filename, translate_prom_address, &addr, 658 NULL, NULL, NULL, 1, EM_SPARCV9, 0); 659 if (ret < 0 || ret > PROM_SIZE_MAX) { 660 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX); 661 } 662 g_free(filename); 663 } else { 664 ret = -1; 665 } 666 if (ret < 0 || ret > PROM_SIZE_MAX) { 667 fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name); 668 exit(1); 669 } 670 } 671 672 static int prom_init1(SysBusDevice *dev) 673 { 674 PROMState *s = OPENPROM(dev); 675 676 memory_region_init_ram(&s->prom, OBJECT(s), "sun4u.prom", PROM_SIZE_MAX, 677 &error_fatal); 678 vmstate_register_ram_global(&s->prom); 679 memory_region_set_readonly(&s->prom, true); 680 sysbus_init_mmio(dev, &s->prom); 681 return 0; 682 } 683 684 static Property prom_properties[] = { 685 {/* end of property list */}, 686 }; 687 688 static void prom_class_init(ObjectClass *klass, void *data) 689 { 690 DeviceClass *dc = DEVICE_CLASS(klass); 691 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 692 693 k->init = prom_init1; 694 dc->props = prom_properties; 695 } 696 697 static const TypeInfo prom_info = { 698 .name = TYPE_OPENPROM, 699 .parent = TYPE_SYS_BUS_DEVICE, 700 .instance_size = sizeof(PROMState), 701 .class_init = prom_class_init, 702 }; 703 704 705 #define TYPE_SUN4U_MEMORY "memory" 706 #define SUN4U_RAM(obj) OBJECT_CHECK(RamDevice, (obj), TYPE_SUN4U_MEMORY) 707 708 typedef struct RamDevice { 709 SysBusDevice parent_obj; 710 711 MemoryRegion ram; 712 uint64_t size; 713 } RamDevice; 714 715 /* System RAM */ 716 static int ram_init1(SysBusDevice *dev) 717 { 718 RamDevice *d = SUN4U_RAM(dev); 719 720 memory_region_init_ram(&d->ram, OBJECT(d), "sun4u.ram", d->size, 721 &error_fatal); 722 vmstate_register_ram_global(&d->ram); 723 sysbus_init_mmio(dev, &d->ram); 724 return 0; 725 } 726 727 static void ram_init(hwaddr addr, ram_addr_t RAM_size) 728 { 729 DeviceState *dev; 730 SysBusDevice *s; 731 RamDevice *d; 732 733 /* allocate RAM */ 734 dev = qdev_create(NULL, TYPE_SUN4U_MEMORY); 735 s = SYS_BUS_DEVICE(dev); 736 737 d = SUN4U_RAM(dev); 738 d->size = RAM_size; 739 qdev_init_nofail(dev); 740 741 sysbus_mmio_map(s, 0, addr); 742 } 743 744 static Property ram_properties[] = { 745 DEFINE_PROP_UINT64("size", RamDevice, size, 0), 746 DEFINE_PROP_END_OF_LIST(), 747 }; 748 749 static void ram_class_init(ObjectClass *klass, void *data) 750 { 751 DeviceClass *dc = DEVICE_CLASS(klass); 752 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 753 754 k->init = ram_init1; 755 dc->props = ram_properties; 756 } 757 758 static const TypeInfo ram_info = { 759 .name = TYPE_SUN4U_MEMORY, 760 .parent = TYPE_SYS_BUS_DEVICE, 761 .instance_size = sizeof(RamDevice), 762 .class_init = ram_class_init, 763 }; 764 765 static SPARCCPU *cpu_devinit(const char *cpu_model, const struct hwdef *hwdef) 766 { 767 SPARCCPU *cpu; 768 CPUSPARCState *env; 769 ResetData *reset_info; 770 771 uint32_t tick_frequency = 100*1000000; 772 uint32_t stick_frequency = 100*1000000; 773 uint32_t hstick_frequency = 100*1000000; 774 775 if (cpu_model == NULL) { 776 cpu_model = hwdef->default_cpu_model; 777 } 778 cpu = cpu_sparc_init(cpu_model); 779 if (cpu == NULL) { 780 fprintf(stderr, "Unable to find Sparc CPU definition\n"); 781 exit(1); 782 } 783 env = &cpu->env; 784 785 env->tick = cpu_timer_create("tick", cpu, tick_irq, 786 tick_frequency, TICK_INT_DIS, 787 TICK_NPT_MASK); 788 789 env->stick = cpu_timer_create("stick", cpu, stick_irq, 790 stick_frequency, TICK_INT_DIS, 791 TICK_NPT_MASK); 792 793 env->hstick = cpu_timer_create("hstick", cpu, hstick_irq, 794 hstick_frequency, TICK_INT_DIS, 795 TICK_NPT_MASK); 796 797 reset_info = g_malloc0(sizeof(ResetData)); 798 reset_info->cpu = cpu; 799 reset_info->prom_addr = hwdef->prom_addr; 800 qemu_register_reset(main_cpu_reset, reset_info); 801 802 return cpu; 803 } 804 805 static void sun4uv_init(MemoryRegion *address_space_mem, 806 MachineState *machine, 807 const struct hwdef *hwdef) 808 { 809 SPARCCPU *cpu; 810 Nvram *nvram; 811 unsigned int i; 812 uint64_t initrd_addr, initrd_size, kernel_addr, kernel_size, kernel_entry; 813 PCIBus *pci_bus, *pci_bus2, *pci_bus3; 814 ISABus *isa_bus; 815 SysBusDevice *s; 816 qemu_irq *ivec_irqs, *pbm_irqs; 817 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; 818 DriveInfo *fd[MAX_FD]; 819 DeviceState *dev; 820 FWCfgState *fw_cfg; 821 822 /* init CPUs */ 823 cpu = cpu_devinit(machine->cpu_model, hwdef); 824 825 /* set up devices */ 826 ram_init(0, machine->ram_size); 827 828 prom_init(hwdef->prom_addr, bios_name); 829 830 ivec_irqs = qemu_allocate_irqs(cpu_set_ivec_irq, cpu, IVEC_MAX); 831 pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, ivec_irqs, &pci_bus2, 832 &pci_bus3, &pbm_irqs); 833 pci_vga_init(pci_bus); 834 835 // XXX Should be pci_bus3 836 isa_bus = pci_ebus_init(pci_bus, -1, pbm_irqs); 837 838 i = 0; 839 if (hwdef->console_serial_base) { 840 serial_mm_init(address_space_mem, hwdef->console_serial_base, 0, 841 NULL, 115200, serial_hds[i], DEVICE_BIG_ENDIAN); 842 i++; 843 } 844 845 serial_hds_isa_init(isa_bus, MAX_SERIAL_PORTS); 846 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); 847 848 for(i = 0; i < nb_nics; i++) 849 pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL); 850 851 ide_drive_get(hd, ARRAY_SIZE(hd)); 852 853 pci_cmd646_ide_init(pci_bus, hd, 1); 854 855 isa_create_simple(isa_bus, "i8042"); 856 857 /* Floppy */ 858 for(i = 0; i < MAX_FD; i++) { 859 fd[i] = drive_get(IF_FLOPPY, 0, i); 860 } 861 dev = DEVICE(isa_create(isa_bus, TYPE_ISA_FDC)); 862 if (fd[0]) { 863 qdev_prop_set_drive(dev, "driveA", blk_by_legacy_dinfo(fd[0]), 864 &error_abort); 865 } 866 if (fd[1]) { 867 qdev_prop_set_drive(dev, "driveB", blk_by_legacy_dinfo(fd[1]), 868 &error_abort); 869 } 870 qdev_prop_set_uint32(dev, "dma", -1); 871 qdev_init_nofail(dev); 872 873 /* Map NVRAM into I/O (ebus) space */ 874 nvram = m48t59_init(NULL, 0, 0, NVRAM_SIZE, 1968, 59); 875 s = SYS_BUS_DEVICE(nvram); 876 memory_region_add_subregion(get_system_io(), 0x2000, 877 sysbus_mmio_get_region(s, 0)); 878 879 initrd_size = 0; 880 initrd_addr = 0; 881 kernel_size = sun4u_load_kernel(machine->kernel_filename, 882 machine->initrd_filename, 883 ram_size, &initrd_size, &initrd_addr, 884 &kernel_addr, &kernel_entry); 885 886 sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", machine->ram_size, 887 machine->boot_order, 888 kernel_addr, kernel_size, 889 machine->kernel_cmdline, 890 initrd_addr, initrd_size, 891 /* XXX: need an option to load a NVRAM image */ 892 0, 893 graphic_width, graphic_height, graphic_depth, 894 (uint8_t *)&nd_table[0].macaddr); 895 896 fw_cfg = fw_cfg_init_io(BIOS_CFG_IOPORT); 897 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus); 898 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 899 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); 900 fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_entry); 901 fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 902 if (machine->kernel_cmdline) { 903 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 904 strlen(machine->kernel_cmdline) + 1); 905 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline); 906 } else { 907 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0); 908 } 909 fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); 910 fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 911 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]); 912 913 fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_WIDTH, graphic_width); 914 fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_HEIGHT, graphic_height); 915 fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_DEPTH, graphic_depth); 916 917 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); 918 } 919 920 enum { 921 sun4u_id = 0, 922 sun4v_id = 64, 923 niagara_id, 924 }; 925 926 static const struct hwdef hwdefs[] = { 927 /* Sun4u generic PC-like machine */ 928 { 929 .default_cpu_model = "TI UltraSparc IIi", 930 .machine_id = sun4u_id, 931 .prom_addr = 0x1fff0000000ULL, 932 .console_serial_base = 0, 933 }, 934 /* Sun4v generic PC-like machine */ 935 { 936 .default_cpu_model = "Sun UltraSparc T1", 937 .machine_id = sun4v_id, 938 .prom_addr = 0x1fff0000000ULL, 939 .console_serial_base = 0, 940 }, 941 /* Sun4v generic Niagara machine */ 942 { 943 .default_cpu_model = "Sun UltraSparc T1", 944 .machine_id = niagara_id, 945 .prom_addr = 0xfff0000000ULL, 946 .console_serial_base = 0xfff0c2c000ULL, 947 }, 948 }; 949 950 /* Sun4u hardware initialisation */ 951 static void sun4u_init(MachineState *machine) 952 { 953 sun4uv_init(get_system_memory(), machine, &hwdefs[0]); 954 } 955 956 /* Sun4v hardware initialisation */ 957 static void sun4v_init(MachineState *machine) 958 { 959 sun4uv_init(get_system_memory(), machine, &hwdefs[1]); 960 } 961 962 /* Niagara hardware initialisation */ 963 static void niagara_init(MachineState *machine) 964 { 965 sun4uv_init(get_system_memory(), machine, &hwdefs[2]); 966 } 967 968 static void sun4u_class_init(ObjectClass *oc, void *data) 969 { 970 MachineClass *mc = MACHINE_CLASS(oc); 971 972 mc->desc = "Sun4u platform"; 973 mc->init = sun4u_init; 974 mc->max_cpus = 1; /* XXX for now */ 975 mc->is_default = 1; 976 mc->default_boot_order = "c"; 977 } 978 979 static const TypeInfo sun4u_type = { 980 .name = MACHINE_TYPE_NAME("sun4u"), 981 .parent = TYPE_MACHINE, 982 .class_init = sun4u_class_init, 983 }; 984 985 static void sun4v_class_init(ObjectClass *oc, void *data) 986 { 987 MachineClass *mc = MACHINE_CLASS(oc); 988 989 mc->desc = "Sun4v platform"; 990 mc->init = sun4v_init; 991 mc->max_cpus = 1; /* XXX for now */ 992 mc->default_boot_order = "c"; 993 } 994 995 static const TypeInfo sun4v_type = { 996 .name = MACHINE_TYPE_NAME("sun4v"), 997 .parent = TYPE_MACHINE, 998 .class_init = sun4v_class_init, 999 }; 1000 1001 static void niagara_class_init(ObjectClass *oc, void *data) 1002 { 1003 MachineClass *mc = MACHINE_CLASS(oc); 1004 1005 mc->desc = "Sun4v platform, Niagara"; 1006 mc->init = niagara_init; 1007 mc->max_cpus = 1; /* XXX for now */ 1008 mc->default_boot_order = "c"; 1009 } 1010 1011 static const TypeInfo niagara_type = { 1012 .name = MACHINE_TYPE_NAME("Niagara"), 1013 .parent = TYPE_MACHINE, 1014 .class_init = niagara_class_init, 1015 }; 1016 1017 static void sun4u_register_types(void) 1018 { 1019 type_register_static(&ebus_info); 1020 type_register_static(&prom_info); 1021 type_register_static(&ram_info); 1022 } 1023 1024 static void sun4u_machine_init(void) 1025 { 1026 type_register_static(&sun4u_type); 1027 type_register_static(&sun4v_type); 1028 type_register_static(&niagara_type); 1029 } 1030 1031 type_init(sun4u_register_types) 1032 machine_init(sun4u_machine_init) 1033