1 /* 2 * QEMU Sun4u/Sun4v System Emulator 3 * 4 * Copyright (c) 2005 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "qemu/osdep.h" 25 #include "qapi/error.h" 26 #include "qemu-common.h" 27 #include "cpu.h" 28 #include "hw/hw.h" 29 #include "hw/pci/pci.h" 30 #include "hw/pci/pci_bus.h" 31 #include "hw/pci-host/apb.h" 32 #include "hw/i386/pc.h" 33 #include "hw/char/serial.h" 34 #include "hw/timer/m48t59.h" 35 #include "hw/block/fdc.h" 36 #include "net/net.h" 37 #include "qemu/timer.h" 38 #include "sysemu/sysemu.h" 39 #include "hw/boards.h" 40 #include "hw/nvram/sun_nvram.h" 41 #include "hw/nvram/chrp_nvram.h" 42 #include "hw/sparc/sparc64.h" 43 #include "hw/nvram/fw_cfg.h" 44 #include "hw/sysbus.h" 45 #include "hw/ide.h" 46 #include "hw/ide/pci.h" 47 #include "hw/loader.h" 48 #include "elf.h" 49 #include "qemu/cutils.h" 50 51 //#define DEBUG_EBUS 52 53 #ifdef DEBUG_EBUS 54 #define EBUS_DPRINTF(fmt, ...) \ 55 do { printf("EBUS: " fmt , ## __VA_ARGS__); } while (0) 56 #else 57 #define EBUS_DPRINTF(fmt, ...) 58 #endif 59 60 #define KERNEL_LOAD_ADDR 0x00404000 61 #define CMDLINE_ADDR 0x003ff000 62 #define PROM_SIZE_MAX (4 * 1024 * 1024) 63 #define PROM_VADDR 0x000ffd00000ULL 64 #define APB_SPECIAL_BASE 0x1fe00000000ULL 65 #define APB_MEM_BASE 0x1ff00000000ULL 66 #define APB_PCI_IO_BASE (APB_SPECIAL_BASE + 0x02000000ULL) 67 #define PROM_FILENAME "openbios-sparc64" 68 #define NVRAM_SIZE 0x2000 69 #define MAX_IDE_BUS 2 70 #define BIOS_CFG_IOPORT 0x510 71 #define FW_CFG_SPARC64_WIDTH (FW_CFG_ARCH_LOCAL + 0x00) 72 #define FW_CFG_SPARC64_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01) 73 #define FW_CFG_SPARC64_DEPTH (FW_CFG_ARCH_LOCAL + 0x02) 74 75 #define IVEC_MAX 0x40 76 77 struct hwdef { 78 const char * const default_cpu_model; 79 uint16_t machine_id; 80 uint64_t prom_addr; 81 uint64_t console_serial_base; 82 }; 83 84 typedef struct EbusState { 85 PCIDevice pci_dev; 86 MemoryRegion bar0; 87 MemoryRegion bar1; 88 } EbusState; 89 90 void DMA_init(ISABus *bus, int high_page_enable) 91 { 92 } 93 94 static void fw_cfg_boot_set(void *opaque, const char *boot_device, 95 Error **errp) 96 { 97 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); 98 } 99 100 static int sun4u_NVRAM_set_params(Nvram *nvram, uint16_t NVRAM_size, 101 const char *arch, ram_addr_t RAM_size, 102 const char *boot_devices, 103 uint32_t kernel_image, uint32_t kernel_size, 104 const char *cmdline, 105 uint32_t initrd_image, uint32_t initrd_size, 106 uint32_t NVRAM_image, 107 int width, int height, int depth, 108 const uint8_t *macaddr) 109 { 110 unsigned int i; 111 int sysp_end; 112 uint8_t image[0x1ff0]; 113 NvramClass *k = NVRAM_GET_CLASS(nvram); 114 115 memset(image, '\0', sizeof(image)); 116 117 /* OpenBIOS nvram variables partition */ 118 sysp_end = chrp_nvram_create_system_partition(image, 0); 119 120 /* Free space partition */ 121 chrp_nvram_create_free_partition(&image[sysp_end], 0x1fd0 - sysp_end); 122 123 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80); 124 125 for (i = 0; i < sizeof(image); i++) { 126 (k->write)(nvram, i, image[i]); 127 } 128 129 return 0; 130 } 131 132 static uint64_t sun4u_load_kernel(const char *kernel_filename, 133 const char *initrd_filename, 134 ram_addr_t RAM_size, uint64_t *initrd_size, 135 uint64_t *initrd_addr, uint64_t *kernel_addr, 136 uint64_t *kernel_entry) 137 { 138 int linux_boot; 139 unsigned int i; 140 long kernel_size; 141 uint8_t *ptr; 142 uint64_t kernel_top; 143 144 linux_boot = (kernel_filename != NULL); 145 146 kernel_size = 0; 147 if (linux_boot) { 148 int bswap_needed; 149 150 #ifdef BSWAP_NEEDED 151 bswap_needed = 1; 152 #else 153 bswap_needed = 0; 154 #endif 155 kernel_size = load_elf(kernel_filename, NULL, NULL, kernel_entry, 156 kernel_addr, &kernel_top, 1, EM_SPARCV9, 0, 0); 157 if (kernel_size < 0) { 158 *kernel_addr = KERNEL_LOAD_ADDR; 159 *kernel_entry = KERNEL_LOAD_ADDR; 160 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR, 161 RAM_size - KERNEL_LOAD_ADDR, bswap_needed, 162 TARGET_PAGE_SIZE); 163 } 164 if (kernel_size < 0) { 165 kernel_size = load_image_targphys(kernel_filename, 166 KERNEL_LOAD_ADDR, 167 RAM_size - KERNEL_LOAD_ADDR); 168 } 169 if (kernel_size < 0) { 170 fprintf(stderr, "qemu: could not load kernel '%s'\n", 171 kernel_filename); 172 exit(1); 173 } 174 /* load initrd above kernel */ 175 *initrd_size = 0; 176 if (initrd_filename) { 177 *initrd_addr = TARGET_PAGE_ALIGN(kernel_top); 178 179 *initrd_size = load_image_targphys(initrd_filename, 180 *initrd_addr, 181 RAM_size - *initrd_addr); 182 if ((int)*initrd_size < 0) { 183 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", 184 initrd_filename); 185 exit(1); 186 } 187 } 188 if (*initrd_size > 0) { 189 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { 190 ptr = rom_ptr(*kernel_addr + i); 191 if (ldl_p(ptr + 8) == 0x48647253) { /* HdrS */ 192 stl_p(ptr + 24, *initrd_addr + *kernel_addr); 193 stl_p(ptr + 28, *initrd_size); 194 break; 195 } 196 } 197 } 198 } 199 return kernel_size; 200 } 201 202 typedef struct ResetData { 203 SPARCCPU *cpu; 204 uint64_t prom_addr; 205 } ResetData; 206 207 static void isa_irq_handler(void *opaque, int n, int level) 208 { 209 static const int isa_irq_to_ivec[16] = { 210 [1] = 0x29, /* keyboard */ 211 [4] = 0x2b, /* serial */ 212 [6] = 0x27, /* floppy */ 213 [7] = 0x22, /* parallel */ 214 [12] = 0x2a, /* mouse */ 215 }; 216 qemu_irq *irqs = opaque; 217 int ivec; 218 219 assert(n < ARRAY_SIZE(isa_irq_to_ivec)); 220 ivec = isa_irq_to_ivec[n]; 221 EBUS_DPRINTF("Set ISA IRQ %d level %d -> ivec 0x%x\n", n, level, ivec); 222 if (ivec) { 223 qemu_set_irq(irqs[ivec], level); 224 } 225 } 226 227 /* EBUS (Eight bit bus) bridge */ 228 static ISABus * 229 pci_ebus_init(PCIDevice *pci_dev, qemu_irq *irqs) 230 { 231 qemu_irq *isa_irq; 232 ISABus *isa_bus; 233 234 isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(pci_dev), "isa.0")); 235 isa_irq = qemu_allocate_irqs(isa_irq_handler, irqs, 16); 236 isa_bus_irqs(isa_bus, isa_irq); 237 return isa_bus; 238 } 239 240 static void pci_ebus_realize(PCIDevice *pci_dev, Error **errp) 241 { 242 EbusState *s = DO_UPCAST(EbusState, pci_dev, pci_dev); 243 244 if (!isa_bus_new(DEVICE(pci_dev), get_system_memory(), 245 pci_address_space_io(pci_dev), errp)) { 246 return; 247 } 248 249 pci_dev->config[0x04] = 0x06; // command = bus master, pci mem 250 pci_dev->config[0x05] = 0x00; 251 pci_dev->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error 252 pci_dev->config[0x07] = 0x03; // status = medium devsel 253 pci_dev->config[0x09] = 0x00; // programming i/f 254 pci_dev->config[0x0D] = 0x0a; // latency_timer 255 256 memory_region_init_alias(&s->bar0, OBJECT(s), "bar0", get_system_io(), 257 0, 0x1000000); 258 pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0); 259 memory_region_init_alias(&s->bar1, OBJECT(s), "bar1", get_system_io(), 260 0, 0x4000); 261 pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->bar1); 262 } 263 264 static void ebus_class_init(ObjectClass *klass, void *data) 265 { 266 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 267 268 k->realize = pci_ebus_realize; 269 k->vendor_id = PCI_VENDOR_ID_SUN; 270 k->device_id = PCI_DEVICE_ID_SUN_EBUS; 271 k->revision = 0x01; 272 k->class_id = PCI_CLASS_BRIDGE_OTHER; 273 } 274 275 static const TypeInfo ebus_info = { 276 .name = "ebus", 277 .parent = TYPE_PCI_DEVICE, 278 .instance_size = sizeof(EbusState), 279 .class_init = ebus_class_init, 280 .interfaces = (InterfaceInfo[]) { 281 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 282 { }, 283 }, 284 }; 285 286 #define TYPE_OPENPROM "openprom" 287 #define OPENPROM(obj) OBJECT_CHECK(PROMState, (obj), TYPE_OPENPROM) 288 289 typedef struct PROMState { 290 SysBusDevice parent_obj; 291 292 MemoryRegion prom; 293 } PROMState; 294 295 static uint64_t translate_prom_address(void *opaque, uint64_t addr) 296 { 297 hwaddr *base_addr = (hwaddr *)opaque; 298 return addr + *base_addr - PROM_VADDR; 299 } 300 301 /* Boot PROM (OpenBIOS) */ 302 static void prom_init(hwaddr addr, const char *bios_name) 303 { 304 DeviceState *dev; 305 SysBusDevice *s; 306 char *filename; 307 int ret; 308 309 dev = qdev_create(NULL, TYPE_OPENPROM); 310 qdev_init_nofail(dev); 311 s = SYS_BUS_DEVICE(dev); 312 313 sysbus_mmio_map(s, 0, addr); 314 315 /* load boot prom */ 316 if (bios_name == NULL) { 317 bios_name = PROM_FILENAME; 318 } 319 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 320 if (filename) { 321 ret = load_elf(filename, translate_prom_address, &addr, 322 NULL, NULL, NULL, 1, EM_SPARCV9, 0, 0); 323 if (ret < 0 || ret > PROM_SIZE_MAX) { 324 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX); 325 } 326 g_free(filename); 327 } else { 328 ret = -1; 329 } 330 if (ret < 0 || ret > PROM_SIZE_MAX) { 331 fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name); 332 exit(1); 333 } 334 } 335 336 static void prom_init1(Object *obj) 337 { 338 PROMState *s = OPENPROM(obj); 339 SysBusDevice *dev = SYS_BUS_DEVICE(obj); 340 341 memory_region_init_ram_nomigrate(&s->prom, obj, "sun4u.prom", PROM_SIZE_MAX, 342 &error_fatal); 343 vmstate_register_ram_global(&s->prom); 344 memory_region_set_readonly(&s->prom, true); 345 sysbus_init_mmio(dev, &s->prom); 346 } 347 348 static Property prom_properties[] = { 349 {/* end of property list */}, 350 }; 351 352 static void prom_class_init(ObjectClass *klass, void *data) 353 { 354 DeviceClass *dc = DEVICE_CLASS(klass); 355 356 dc->props = prom_properties; 357 } 358 359 static const TypeInfo prom_info = { 360 .name = TYPE_OPENPROM, 361 .parent = TYPE_SYS_BUS_DEVICE, 362 .instance_size = sizeof(PROMState), 363 .class_init = prom_class_init, 364 .instance_init = prom_init1, 365 }; 366 367 368 #define TYPE_SUN4U_MEMORY "memory" 369 #define SUN4U_RAM(obj) OBJECT_CHECK(RamDevice, (obj), TYPE_SUN4U_MEMORY) 370 371 typedef struct RamDevice { 372 SysBusDevice parent_obj; 373 374 MemoryRegion ram; 375 uint64_t size; 376 } RamDevice; 377 378 /* System RAM */ 379 static void ram_realize(DeviceState *dev, Error **errp) 380 { 381 RamDevice *d = SUN4U_RAM(dev); 382 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 383 384 memory_region_init_ram_nomigrate(&d->ram, OBJECT(d), "sun4u.ram", d->size, 385 &error_fatal); 386 vmstate_register_ram_global(&d->ram); 387 sysbus_init_mmio(sbd, &d->ram); 388 } 389 390 static void ram_init(hwaddr addr, ram_addr_t RAM_size) 391 { 392 DeviceState *dev; 393 SysBusDevice *s; 394 RamDevice *d; 395 396 /* allocate RAM */ 397 dev = qdev_create(NULL, TYPE_SUN4U_MEMORY); 398 s = SYS_BUS_DEVICE(dev); 399 400 d = SUN4U_RAM(dev); 401 d->size = RAM_size; 402 qdev_init_nofail(dev); 403 404 sysbus_mmio_map(s, 0, addr); 405 } 406 407 static Property ram_properties[] = { 408 DEFINE_PROP_UINT64("size", RamDevice, size, 0), 409 DEFINE_PROP_END_OF_LIST(), 410 }; 411 412 static void ram_class_init(ObjectClass *klass, void *data) 413 { 414 DeviceClass *dc = DEVICE_CLASS(klass); 415 416 dc->realize = ram_realize; 417 dc->props = ram_properties; 418 } 419 420 static const TypeInfo ram_info = { 421 .name = TYPE_SUN4U_MEMORY, 422 .parent = TYPE_SYS_BUS_DEVICE, 423 .instance_size = sizeof(RamDevice), 424 .class_init = ram_class_init, 425 }; 426 427 static void sun4uv_init(MemoryRegion *address_space_mem, 428 MachineState *machine, 429 const struct hwdef *hwdef) 430 { 431 SPARCCPU *cpu; 432 Nvram *nvram; 433 unsigned int i; 434 uint64_t initrd_addr, initrd_size, kernel_addr, kernel_size, kernel_entry; 435 PCIBus *pci_bus, *pci_busA, *pci_busB; 436 PCIDevice *ebus, *pci_dev; 437 ISABus *isa_bus; 438 SysBusDevice *s; 439 qemu_irq *ivec_irqs, *pbm_irqs; 440 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; 441 DriveInfo *fd[MAX_FD]; 442 DeviceState *dev; 443 FWCfgState *fw_cfg; 444 NICInfo *nd; 445 MACAddr macaddr; 446 bool onboard_nic; 447 448 /* init CPUs */ 449 cpu = sparc64_cpu_devinit(machine->cpu_model, hwdef->default_cpu_model, 450 hwdef->prom_addr); 451 452 /* set up devices */ 453 ram_init(0, machine->ram_size); 454 455 prom_init(hwdef->prom_addr, bios_name); 456 457 ivec_irqs = qemu_allocate_irqs(sparc64_cpu_set_ivec_irq, cpu, IVEC_MAX); 458 pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, ivec_irqs, &pci_busA, 459 &pci_busB, &pbm_irqs); 460 461 /* Only in-built Simba PBMs can exist on the root bus, slot 0 on busA is 462 reserved (leaving no slots free after on-board devices) however slots 463 0-3 are free on busB */ 464 pci_bus->slot_reserved_mask = 0xfffffffc; 465 pci_busA->slot_reserved_mask = 0xfffffff1; 466 pci_busB->slot_reserved_mask = 0xfffffff0; 467 468 ebus = pci_create_multifunction(pci_busA, PCI_DEVFN(1, 0), true, "ebus"); 469 qdev_init_nofail(DEVICE(ebus)); 470 471 isa_bus = pci_ebus_init(ebus, pbm_irqs); 472 473 i = 0; 474 if (hwdef->console_serial_base) { 475 serial_mm_init(address_space_mem, hwdef->console_serial_base, 0, 476 NULL, 115200, serial_hds[i], DEVICE_BIG_ENDIAN); 477 i++; 478 } 479 480 serial_hds_isa_init(isa_bus, i, MAX_SERIAL_PORTS); 481 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); 482 483 pci_dev = pci_create_simple(pci_busA, PCI_DEVFN(2, 0), "VGA"); 484 485 memset(&macaddr, 0, sizeof(MACAddr)); 486 onboard_nic = false; 487 for (i = 0; i < nb_nics; i++) { 488 nd = &nd_table[i]; 489 490 if (!nd->model || strcmp(nd->model, "sunhme") == 0) { 491 if (!onboard_nic) { 492 pci_dev = pci_create_multifunction(pci_busA, PCI_DEVFN(1, 1), 493 true, "sunhme"); 494 memcpy(&macaddr, &nd->macaddr.a, sizeof(MACAddr)); 495 onboard_nic = true; 496 } else { 497 pci_dev = pci_create(pci_busB, -1, "sunhme"); 498 } 499 } else { 500 pci_dev = pci_create(pci_busB, -1, nd->model); 501 } 502 503 dev = &pci_dev->qdev; 504 qdev_set_nic_properties(dev, nd); 505 qdev_init_nofail(dev); 506 } 507 508 /* If we don't have an onboard NIC, grab a default MAC address so that 509 * we have a valid machine id */ 510 if (!onboard_nic) { 511 qemu_macaddr_default_if_unset(&macaddr); 512 } 513 514 ide_drive_get(hd, ARRAY_SIZE(hd)); 515 516 pci_dev = pci_create(pci_busA, PCI_DEVFN(3, 0), "cmd646-ide"); 517 qdev_prop_set_uint32(&pci_dev->qdev, "secondary", 1); 518 qdev_init_nofail(&pci_dev->qdev); 519 pci_ide_create_devs(pci_dev, hd); 520 521 isa_create_simple(isa_bus, "i8042"); 522 523 /* Floppy */ 524 for(i = 0; i < MAX_FD; i++) { 525 fd[i] = drive_get(IF_FLOPPY, 0, i); 526 } 527 dev = DEVICE(isa_create(isa_bus, TYPE_ISA_FDC)); 528 if (fd[0]) { 529 qdev_prop_set_drive(dev, "driveA", blk_by_legacy_dinfo(fd[0]), 530 &error_abort); 531 } 532 if (fd[1]) { 533 qdev_prop_set_drive(dev, "driveB", blk_by_legacy_dinfo(fd[1]), 534 &error_abort); 535 } 536 qdev_prop_set_uint32(dev, "dma", -1); 537 qdev_init_nofail(dev); 538 539 /* Map NVRAM into I/O (ebus) space */ 540 nvram = m48t59_init(NULL, 0, 0, NVRAM_SIZE, 1968, 59); 541 s = SYS_BUS_DEVICE(nvram); 542 memory_region_add_subregion(pci_address_space_io(ebus), 0x2000, 543 sysbus_mmio_get_region(s, 0)); 544 545 initrd_size = 0; 546 initrd_addr = 0; 547 kernel_size = sun4u_load_kernel(machine->kernel_filename, 548 machine->initrd_filename, 549 ram_size, &initrd_size, &initrd_addr, 550 &kernel_addr, &kernel_entry); 551 552 sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", machine->ram_size, 553 machine->boot_order, 554 kernel_addr, kernel_size, 555 machine->kernel_cmdline, 556 initrd_addr, initrd_size, 557 /* XXX: need an option to load a NVRAM image */ 558 0, 559 graphic_width, graphic_height, graphic_depth, 560 (uint8_t *)&macaddr); 561 562 dev = qdev_create(NULL, TYPE_FW_CFG_IO); 563 qdev_prop_set_bit(dev, "dma_enabled", false); 564 object_property_add_child(OBJECT(ebus), TYPE_FW_CFG, OBJECT(dev), NULL); 565 qdev_init_nofail(dev); 566 memory_region_add_subregion(pci_address_space_io(ebus), BIOS_CFG_IOPORT, 567 &FW_CFG_IO(dev)->comb_iomem); 568 569 fw_cfg = FW_CFG(dev); 570 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus); 571 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus); 572 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 573 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); 574 fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_entry); 575 fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 576 if (machine->kernel_cmdline) { 577 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 578 strlen(machine->kernel_cmdline) + 1); 579 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline); 580 } else { 581 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0); 582 } 583 fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); 584 fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 585 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]); 586 587 fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_WIDTH, graphic_width); 588 fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_HEIGHT, graphic_height); 589 fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_DEPTH, graphic_depth); 590 591 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); 592 } 593 594 enum { 595 sun4u_id = 0, 596 sun4v_id = 64, 597 }; 598 599 static const struct hwdef hwdefs[] = { 600 /* Sun4u generic PC-like machine */ 601 { 602 .default_cpu_model = "TI UltraSparc IIi", 603 .machine_id = sun4u_id, 604 .prom_addr = 0x1fff0000000ULL, 605 .console_serial_base = 0, 606 }, 607 /* Sun4v generic PC-like machine */ 608 { 609 .default_cpu_model = "Sun UltraSparc T1", 610 .machine_id = sun4v_id, 611 .prom_addr = 0x1fff0000000ULL, 612 .console_serial_base = 0, 613 }, 614 }; 615 616 /* Sun4u hardware initialisation */ 617 static void sun4u_init(MachineState *machine) 618 { 619 sun4uv_init(get_system_memory(), machine, &hwdefs[0]); 620 } 621 622 /* Sun4v hardware initialisation */ 623 static void sun4v_init(MachineState *machine) 624 { 625 sun4uv_init(get_system_memory(), machine, &hwdefs[1]); 626 } 627 628 static void sun4u_class_init(ObjectClass *oc, void *data) 629 { 630 MachineClass *mc = MACHINE_CLASS(oc); 631 632 mc->desc = "Sun4u platform"; 633 mc->init = sun4u_init; 634 mc->block_default_type = IF_IDE; 635 mc->max_cpus = 1; /* XXX for now */ 636 mc->is_default = 1; 637 mc->default_boot_order = "c"; 638 } 639 640 static const TypeInfo sun4u_type = { 641 .name = MACHINE_TYPE_NAME("sun4u"), 642 .parent = TYPE_MACHINE, 643 .class_init = sun4u_class_init, 644 }; 645 646 static void sun4v_class_init(ObjectClass *oc, void *data) 647 { 648 MachineClass *mc = MACHINE_CLASS(oc); 649 650 mc->desc = "Sun4v platform"; 651 mc->init = sun4v_init; 652 mc->block_default_type = IF_IDE; 653 mc->max_cpus = 1; /* XXX for now */ 654 mc->default_boot_order = "c"; 655 } 656 657 static const TypeInfo sun4v_type = { 658 .name = MACHINE_TYPE_NAME("sun4v"), 659 .parent = TYPE_MACHINE, 660 .class_init = sun4v_class_init, 661 }; 662 663 static void sun4u_register_types(void) 664 { 665 type_register_static(&ebus_info); 666 type_register_static(&prom_info); 667 type_register_static(&ram_info); 668 669 type_register_static(&sun4u_type); 670 type_register_static(&sun4v_type); 671 } 672 673 type_init(sun4u_register_types) 674