1 /* 2 * QEMU Sun4u/Sun4v System Emulator 3 * 4 * Copyright (c) 2005 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "qemu/osdep.h" 25 #include "qapi/error.h" 26 #include "qemu-common.h" 27 #include "cpu.h" 28 #include "hw/hw.h" 29 #include "hw/pci/pci.h" 30 #include "hw/pci/pci_bus.h" 31 #include "hw/pci-host/apb.h" 32 #include "hw/i386/pc.h" 33 #include "hw/char/serial.h" 34 #include "hw/timer/m48t59.h" 35 #include "hw/block/fdc.h" 36 #include "net/net.h" 37 #include "qemu/timer.h" 38 #include "sysemu/sysemu.h" 39 #include "hw/boards.h" 40 #include "hw/nvram/sun_nvram.h" 41 #include "hw/nvram/chrp_nvram.h" 42 #include "hw/sparc/sparc64.h" 43 #include "hw/nvram/fw_cfg.h" 44 #include "hw/sysbus.h" 45 #include "hw/ide.h" 46 #include "hw/ide/pci.h" 47 #include "hw/loader.h" 48 #include "elf.h" 49 #include "qemu/cutils.h" 50 51 //#define DEBUG_EBUS 52 53 #ifdef DEBUG_EBUS 54 #define EBUS_DPRINTF(fmt, ...) \ 55 do { printf("EBUS: " fmt , ## __VA_ARGS__); } while (0) 56 #else 57 #define EBUS_DPRINTF(fmt, ...) 58 #endif 59 60 #define KERNEL_LOAD_ADDR 0x00404000 61 #define CMDLINE_ADDR 0x003ff000 62 #define PROM_SIZE_MAX (4 * 1024 * 1024) 63 #define PROM_VADDR 0x000ffd00000ULL 64 #define APB_SPECIAL_BASE 0x1fe00000000ULL 65 #define APB_MEM_BASE 0x1ff00000000ULL 66 #define APB_PCI_IO_BASE (APB_SPECIAL_BASE + 0x02000000ULL) 67 #define PROM_FILENAME "openbios-sparc64" 68 #define NVRAM_SIZE 0x2000 69 #define MAX_IDE_BUS 2 70 #define BIOS_CFG_IOPORT 0x510 71 #define FW_CFG_SPARC64_WIDTH (FW_CFG_ARCH_LOCAL + 0x00) 72 #define FW_CFG_SPARC64_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01) 73 #define FW_CFG_SPARC64_DEPTH (FW_CFG_ARCH_LOCAL + 0x02) 74 75 #define IVEC_MAX 0x40 76 77 struct hwdef { 78 uint16_t machine_id; 79 uint64_t prom_addr; 80 uint64_t console_serial_base; 81 }; 82 83 typedef struct EbusState { 84 /*< private >*/ 85 PCIDevice parent_obj; 86 87 MemoryRegion bar0; 88 MemoryRegion bar1; 89 } EbusState; 90 91 #define TYPE_EBUS "ebus" 92 #define EBUS(obj) OBJECT_CHECK(EbusState, (obj), TYPE_EBUS) 93 94 void DMA_init(ISABus *bus, int high_page_enable) 95 { 96 } 97 98 static void fw_cfg_boot_set(void *opaque, const char *boot_device, 99 Error **errp) 100 { 101 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); 102 } 103 104 static int sun4u_NVRAM_set_params(Nvram *nvram, uint16_t NVRAM_size, 105 const char *arch, ram_addr_t RAM_size, 106 const char *boot_devices, 107 uint32_t kernel_image, uint32_t kernel_size, 108 const char *cmdline, 109 uint32_t initrd_image, uint32_t initrd_size, 110 uint32_t NVRAM_image, 111 int width, int height, int depth, 112 const uint8_t *macaddr) 113 { 114 unsigned int i; 115 int sysp_end; 116 uint8_t image[0x1ff0]; 117 NvramClass *k = NVRAM_GET_CLASS(nvram); 118 119 memset(image, '\0', sizeof(image)); 120 121 /* OpenBIOS nvram variables partition */ 122 sysp_end = chrp_nvram_create_system_partition(image, 0); 123 124 /* Free space partition */ 125 chrp_nvram_create_free_partition(&image[sysp_end], 0x1fd0 - sysp_end); 126 127 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80); 128 129 for (i = 0; i < sizeof(image); i++) { 130 (k->write)(nvram, i, image[i]); 131 } 132 133 return 0; 134 } 135 136 static uint64_t sun4u_load_kernel(const char *kernel_filename, 137 const char *initrd_filename, 138 ram_addr_t RAM_size, uint64_t *initrd_size, 139 uint64_t *initrd_addr, uint64_t *kernel_addr, 140 uint64_t *kernel_entry) 141 { 142 int linux_boot; 143 unsigned int i; 144 long kernel_size; 145 uint8_t *ptr; 146 uint64_t kernel_top; 147 148 linux_boot = (kernel_filename != NULL); 149 150 kernel_size = 0; 151 if (linux_boot) { 152 int bswap_needed; 153 154 #ifdef BSWAP_NEEDED 155 bswap_needed = 1; 156 #else 157 bswap_needed = 0; 158 #endif 159 kernel_size = load_elf(kernel_filename, NULL, NULL, kernel_entry, 160 kernel_addr, &kernel_top, 1, EM_SPARCV9, 0, 0); 161 if (kernel_size < 0) { 162 *kernel_addr = KERNEL_LOAD_ADDR; 163 *kernel_entry = KERNEL_LOAD_ADDR; 164 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR, 165 RAM_size - KERNEL_LOAD_ADDR, bswap_needed, 166 TARGET_PAGE_SIZE); 167 } 168 if (kernel_size < 0) { 169 kernel_size = load_image_targphys(kernel_filename, 170 KERNEL_LOAD_ADDR, 171 RAM_size - KERNEL_LOAD_ADDR); 172 } 173 if (kernel_size < 0) { 174 fprintf(stderr, "qemu: could not load kernel '%s'\n", 175 kernel_filename); 176 exit(1); 177 } 178 /* load initrd above kernel */ 179 *initrd_size = 0; 180 if (initrd_filename) { 181 *initrd_addr = TARGET_PAGE_ALIGN(kernel_top); 182 183 *initrd_size = load_image_targphys(initrd_filename, 184 *initrd_addr, 185 RAM_size - *initrd_addr); 186 if ((int)*initrd_size < 0) { 187 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", 188 initrd_filename); 189 exit(1); 190 } 191 } 192 if (*initrd_size > 0) { 193 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { 194 ptr = rom_ptr(*kernel_addr + i); 195 if (ldl_p(ptr + 8) == 0x48647253) { /* HdrS */ 196 stl_p(ptr + 24, *initrd_addr + *kernel_addr); 197 stl_p(ptr + 28, *initrd_size); 198 break; 199 } 200 } 201 } 202 } 203 return kernel_size; 204 } 205 206 typedef struct ResetData { 207 SPARCCPU *cpu; 208 uint64_t prom_addr; 209 } ResetData; 210 211 static void isa_irq_handler(void *opaque, int n, int level) 212 { 213 static const int isa_irq_to_ivec[16] = { 214 [1] = 0x29, /* keyboard */ 215 [4] = 0x2b, /* serial */ 216 [6] = 0x27, /* floppy */ 217 [7] = 0x22, /* parallel */ 218 [12] = 0x2a, /* mouse */ 219 }; 220 qemu_irq *irqs = opaque; 221 int ivec; 222 223 assert(n < ARRAY_SIZE(isa_irq_to_ivec)); 224 ivec = isa_irq_to_ivec[n]; 225 EBUS_DPRINTF("Set ISA IRQ %d level %d -> ivec 0x%x\n", n, level, ivec); 226 if (ivec) { 227 qemu_set_irq(irqs[ivec], level); 228 } 229 } 230 231 /* EBUS (Eight bit bus) bridge */ 232 static ISABus * 233 pci_ebus_init(PCIDevice *pci_dev, qemu_irq *irqs) 234 { 235 qemu_irq *isa_irq; 236 ISABus *isa_bus; 237 238 isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(pci_dev), "isa.0")); 239 isa_irq = qemu_allocate_irqs(isa_irq_handler, irqs, 16); 240 isa_bus_irqs(isa_bus, isa_irq); 241 return isa_bus; 242 } 243 244 static void ebus_realize(PCIDevice *pci_dev, Error **errp) 245 { 246 EbusState *s = EBUS(pci_dev); 247 248 if (!isa_bus_new(DEVICE(pci_dev), get_system_memory(), 249 pci_address_space_io(pci_dev), errp)) { 250 return; 251 } 252 253 pci_dev->config[0x04] = 0x06; // command = bus master, pci mem 254 pci_dev->config[0x05] = 0x00; 255 pci_dev->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error 256 pci_dev->config[0x07] = 0x03; // status = medium devsel 257 pci_dev->config[0x09] = 0x00; // programming i/f 258 pci_dev->config[0x0D] = 0x0a; // latency_timer 259 260 memory_region_init_alias(&s->bar0, OBJECT(s), "bar0", get_system_io(), 261 0, 0x1000000); 262 pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0); 263 memory_region_init_alias(&s->bar1, OBJECT(s), "bar1", get_system_io(), 264 0, 0x4000); 265 pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->bar1); 266 } 267 268 static void ebus_class_init(ObjectClass *klass, void *data) 269 { 270 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 271 272 k->realize = ebus_realize; 273 k->vendor_id = PCI_VENDOR_ID_SUN; 274 k->device_id = PCI_DEVICE_ID_SUN_EBUS; 275 k->revision = 0x01; 276 k->class_id = PCI_CLASS_BRIDGE_OTHER; 277 } 278 279 static const TypeInfo ebus_info = { 280 .name = TYPE_EBUS, 281 .parent = TYPE_PCI_DEVICE, 282 .class_init = ebus_class_init, 283 .instance_size = sizeof(EbusState), 284 .interfaces = (InterfaceInfo[]) { 285 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 286 { }, 287 }, 288 }; 289 290 #define TYPE_OPENPROM "openprom" 291 #define OPENPROM(obj) OBJECT_CHECK(PROMState, (obj), TYPE_OPENPROM) 292 293 typedef struct PROMState { 294 SysBusDevice parent_obj; 295 296 MemoryRegion prom; 297 } PROMState; 298 299 static uint64_t translate_prom_address(void *opaque, uint64_t addr) 300 { 301 hwaddr *base_addr = (hwaddr *)opaque; 302 return addr + *base_addr - PROM_VADDR; 303 } 304 305 /* Boot PROM (OpenBIOS) */ 306 static void prom_init(hwaddr addr, const char *bios_name) 307 { 308 DeviceState *dev; 309 SysBusDevice *s; 310 char *filename; 311 int ret; 312 313 dev = qdev_create(NULL, TYPE_OPENPROM); 314 qdev_init_nofail(dev); 315 s = SYS_BUS_DEVICE(dev); 316 317 sysbus_mmio_map(s, 0, addr); 318 319 /* load boot prom */ 320 if (bios_name == NULL) { 321 bios_name = PROM_FILENAME; 322 } 323 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 324 if (filename) { 325 ret = load_elf(filename, translate_prom_address, &addr, 326 NULL, NULL, NULL, 1, EM_SPARCV9, 0, 0); 327 if (ret < 0 || ret > PROM_SIZE_MAX) { 328 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX); 329 } 330 g_free(filename); 331 } else { 332 ret = -1; 333 } 334 if (ret < 0 || ret > PROM_SIZE_MAX) { 335 fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name); 336 exit(1); 337 } 338 } 339 340 static void prom_init1(Object *obj) 341 { 342 PROMState *s = OPENPROM(obj); 343 SysBusDevice *dev = SYS_BUS_DEVICE(obj); 344 345 memory_region_init_ram_nomigrate(&s->prom, obj, "sun4u.prom", PROM_SIZE_MAX, 346 &error_fatal); 347 vmstate_register_ram_global(&s->prom); 348 memory_region_set_readonly(&s->prom, true); 349 sysbus_init_mmio(dev, &s->prom); 350 } 351 352 static Property prom_properties[] = { 353 {/* end of property list */}, 354 }; 355 356 static void prom_class_init(ObjectClass *klass, void *data) 357 { 358 DeviceClass *dc = DEVICE_CLASS(klass); 359 360 dc->props = prom_properties; 361 } 362 363 static const TypeInfo prom_info = { 364 .name = TYPE_OPENPROM, 365 .parent = TYPE_SYS_BUS_DEVICE, 366 .instance_size = sizeof(PROMState), 367 .class_init = prom_class_init, 368 .instance_init = prom_init1, 369 }; 370 371 372 #define TYPE_SUN4U_MEMORY "memory" 373 #define SUN4U_RAM(obj) OBJECT_CHECK(RamDevice, (obj), TYPE_SUN4U_MEMORY) 374 375 typedef struct RamDevice { 376 SysBusDevice parent_obj; 377 378 MemoryRegion ram; 379 uint64_t size; 380 } RamDevice; 381 382 /* System RAM */ 383 static void ram_realize(DeviceState *dev, Error **errp) 384 { 385 RamDevice *d = SUN4U_RAM(dev); 386 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 387 388 memory_region_init_ram_nomigrate(&d->ram, OBJECT(d), "sun4u.ram", d->size, 389 &error_fatal); 390 vmstate_register_ram_global(&d->ram); 391 sysbus_init_mmio(sbd, &d->ram); 392 } 393 394 static void ram_init(hwaddr addr, ram_addr_t RAM_size) 395 { 396 DeviceState *dev; 397 SysBusDevice *s; 398 RamDevice *d; 399 400 /* allocate RAM */ 401 dev = qdev_create(NULL, TYPE_SUN4U_MEMORY); 402 s = SYS_BUS_DEVICE(dev); 403 404 d = SUN4U_RAM(dev); 405 d->size = RAM_size; 406 qdev_init_nofail(dev); 407 408 sysbus_mmio_map(s, 0, addr); 409 } 410 411 static Property ram_properties[] = { 412 DEFINE_PROP_UINT64("size", RamDevice, size, 0), 413 DEFINE_PROP_END_OF_LIST(), 414 }; 415 416 static void ram_class_init(ObjectClass *klass, void *data) 417 { 418 DeviceClass *dc = DEVICE_CLASS(klass); 419 420 dc->realize = ram_realize; 421 dc->props = ram_properties; 422 } 423 424 static const TypeInfo ram_info = { 425 .name = TYPE_SUN4U_MEMORY, 426 .parent = TYPE_SYS_BUS_DEVICE, 427 .instance_size = sizeof(RamDevice), 428 .class_init = ram_class_init, 429 }; 430 431 static void sun4uv_init(MemoryRegion *address_space_mem, 432 MachineState *machine, 433 const struct hwdef *hwdef) 434 { 435 SPARCCPU *cpu; 436 Nvram *nvram; 437 unsigned int i; 438 uint64_t initrd_addr, initrd_size, kernel_addr, kernel_size, kernel_entry; 439 PCIBus *pci_bus, *pci_busA, *pci_busB; 440 PCIDevice *ebus, *pci_dev; 441 ISABus *isa_bus; 442 SysBusDevice *s; 443 qemu_irq *ivec_irqs, *pbm_irqs; 444 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; 445 DriveInfo *fd[MAX_FD]; 446 DeviceState *dev; 447 FWCfgState *fw_cfg; 448 NICInfo *nd; 449 MACAddr macaddr; 450 bool onboard_nic; 451 452 /* init CPUs */ 453 cpu = sparc64_cpu_devinit(machine->cpu_type, hwdef->prom_addr); 454 455 /* set up devices */ 456 ram_init(0, machine->ram_size); 457 458 prom_init(hwdef->prom_addr, bios_name); 459 460 ivec_irqs = qemu_allocate_irqs(sparc64_cpu_set_ivec_irq, cpu, IVEC_MAX); 461 pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, ivec_irqs, &pci_busA, 462 &pci_busB, &pbm_irqs); 463 464 /* Only in-built Simba PBMs can exist on the root bus, slot 0 on busA is 465 reserved (leaving no slots free after on-board devices) however slots 466 0-3 are free on busB */ 467 pci_bus->slot_reserved_mask = 0xfffffffc; 468 pci_busA->slot_reserved_mask = 0xfffffff1; 469 pci_busB->slot_reserved_mask = 0xfffffff0; 470 471 ebus = pci_create_multifunction(pci_busA, PCI_DEVFN(1, 0), true, TYPE_EBUS); 472 qdev_init_nofail(DEVICE(ebus)); 473 474 isa_bus = pci_ebus_init(ebus, pbm_irqs); 475 476 i = 0; 477 if (hwdef->console_serial_base) { 478 serial_mm_init(address_space_mem, hwdef->console_serial_base, 0, 479 NULL, 115200, serial_hds[i], DEVICE_BIG_ENDIAN); 480 i++; 481 } 482 483 serial_hds_isa_init(isa_bus, i, MAX_SERIAL_PORTS); 484 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); 485 486 pci_dev = pci_create_simple(pci_busA, PCI_DEVFN(2, 0), "VGA"); 487 488 memset(&macaddr, 0, sizeof(MACAddr)); 489 onboard_nic = false; 490 for (i = 0; i < nb_nics; i++) { 491 nd = &nd_table[i]; 492 493 if (!nd->model || strcmp(nd->model, "sunhme") == 0) { 494 if (!onboard_nic) { 495 pci_dev = pci_create_multifunction(pci_busA, PCI_DEVFN(1, 1), 496 true, "sunhme"); 497 memcpy(&macaddr, &nd->macaddr.a, sizeof(MACAddr)); 498 onboard_nic = true; 499 } else { 500 pci_dev = pci_create(pci_busB, -1, "sunhme"); 501 } 502 } else { 503 pci_dev = pci_create(pci_busB, -1, nd->model); 504 } 505 506 dev = &pci_dev->qdev; 507 qdev_set_nic_properties(dev, nd); 508 qdev_init_nofail(dev); 509 } 510 511 /* If we don't have an onboard NIC, grab a default MAC address so that 512 * we have a valid machine id */ 513 if (!onboard_nic) { 514 qemu_macaddr_default_if_unset(&macaddr); 515 } 516 517 ide_drive_get(hd, ARRAY_SIZE(hd)); 518 519 pci_dev = pci_create(pci_busA, PCI_DEVFN(3, 0), "cmd646-ide"); 520 qdev_prop_set_uint32(&pci_dev->qdev, "secondary", 1); 521 qdev_init_nofail(&pci_dev->qdev); 522 pci_ide_create_devs(pci_dev, hd); 523 524 isa_create_simple(isa_bus, "i8042"); 525 526 /* Floppy */ 527 for(i = 0; i < MAX_FD; i++) { 528 fd[i] = drive_get(IF_FLOPPY, 0, i); 529 } 530 dev = DEVICE(isa_create(isa_bus, TYPE_ISA_FDC)); 531 if (fd[0]) { 532 qdev_prop_set_drive(dev, "driveA", blk_by_legacy_dinfo(fd[0]), 533 &error_abort); 534 } 535 if (fd[1]) { 536 qdev_prop_set_drive(dev, "driveB", blk_by_legacy_dinfo(fd[1]), 537 &error_abort); 538 } 539 qdev_prop_set_uint32(dev, "dma", -1); 540 qdev_init_nofail(dev); 541 542 /* Map NVRAM into I/O (ebus) space */ 543 nvram = m48t59_init(NULL, 0, 0, NVRAM_SIZE, 1968, 59); 544 s = SYS_BUS_DEVICE(nvram); 545 memory_region_add_subregion(pci_address_space_io(ebus), 0x2000, 546 sysbus_mmio_get_region(s, 0)); 547 548 initrd_size = 0; 549 initrd_addr = 0; 550 kernel_size = sun4u_load_kernel(machine->kernel_filename, 551 machine->initrd_filename, 552 ram_size, &initrd_size, &initrd_addr, 553 &kernel_addr, &kernel_entry); 554 555 sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", machine->ram_size, 556 machine->boot_order, 557 kernel_addr, kernel_size, 558 machine->kernel_cmdline, 559 initrd_addr, initrd_size, 560 /* XXX: need an option to load a NVRAM image */ 561 0, 562 graphic_width, graphic_height, graphic_depth, 563 (uint8_t *)&macaddr); 564 565 dev = qdev_create(NULL, TYPE_FW_CFG_IO); 566 qdev_prop_set_bit(dev, "dma_enabled", false); 567 object_property_add_child(OBJECT(ebus), TYPE_FW_CFG, OBJECT(dev), NULL); 568 qdev_init_nofail(dev); 569 memory_region_add_subregion(pci_address_space_io(ebus), BIOS_CFG_IOPORT, 570 &FW_CFG_IO(dev)->comb_iomem); 571 572 fw_cfg = FW_CFG(dev); 573 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus); 574 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus); 575 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 576 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); 577 fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_entry); 578 fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 579 if (machine->kernel_cmdline) { 580 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 581 strlen(machine->kernel_cmdline) + 1); 582 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline); 583 } else { 584 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0); 585 } 586 fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); 587 fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 588 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]); 589 590 fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_WIDTH, graphic_width); 591 fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_HEIGHT, graphic_height); 592 fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_DEPTH, graphic_depth); 593 594 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); 595 } 596 597 enum { 598 sun4u_id = 0, 599 sun4v_id = 64, 600 }; 601 602 static const struct hwdef hwdefs[] = { 603 /* Sun4u generic PC-like machine */ 604 { 605 .machine_id = sun4u_id, 606 .prom_addr = 0x1fff0000000ULL, 607 .console_serial_base = 0, 608 }, 609 /* Sun4v generic PC-like machine */ 610 { 611 .machine_id = sun4v_id, 612 .prom_addr = 0x1fff0000000ULL, 613 .console_serial_base = 0, 614 }, 615 }; 616 617 /* Sun4u hardware initialisation */ 618 static void sun4u_init(MachineState *machine) 619 { 620 sun4uv_init(get_system_memory(), machine, &hwdefs[0]); 621 } 622 623 /* Sun4v hardware initialisation */ 624 static void sun4v_init(MachineState *machine) 625 { 626 sun4uv_init(get_system_memory(), machine, &hwdefs[1]); 627 } 628 629 static void sun4u_class_init(ObjectClass *oc, void *data) 630 { 631 MachineClass *mc = MACHINE_CLASS(oc); 632 633 mc->desc = "Sun4u platform"; 634 mc->init = sun4u_init; 635 mc->block_default_type = IF_IDE; 636 mc->max_cpus = 1; /* XXX for now */ 637 mc->is_default = 1; 638 mc->default_boot_order = "c"; 639 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-UltraSparc-IIi"); 640 } 641 642 static const TypeInfo sun4u_type = { 643 .name = MACHINE_TYPE_NAME("sun4u"), 644 .parent = TYPE_MACHINE, 645 .class_init = sun4u_class_init, 646 }; 647 648 static void sun4v_class_init(ObjectClass *oc, void *data) 649 { 650 MachineClass *mc = MACHINE_CLASS(oc); 651 652 mc->desc = "Sun4v platform"; 653 mc->init = sun4v_init; 654 mc->block_default_type = IF_IDE; 655 mc->max_cpus = 1; /* XXX for now */ 656 mc->default_boot_order = "c"; 657 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Sun-UltraSparc-T1"); 658 } 659 660 static const TypeInfo sun4v_type = { 661 .name = MACHINE_TYPE_NAME("sun4v"), 662 .parent = TYPE_MACHINE, 663 .class_init = sun4v_class_init, 664 }; 665 666 static void sun4u_register_types(void) 667 { 668 type_register_static(&ebus_info); 669 type_register_static(&prom_info); 670 type_register_static(&ram_info); 671 672 type_register_static(&sun4u_type); 673 type_register_static(&sun4v_type); 674 } 675 676 type_init(sun4u_register_types) 677