1 /* 2 * QEMU Sun4u/Sun4v System Emulator 3 * 4 * Copyright (c) 2005 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "qemu/error-report.h" 28 #include "qapi/error.h" 29 #include "qemu-common.h" 30 #include "cpu.h" 31 #include "hw/pci/pci.h" 32 #include "hw/pci/pci_bridge.h" 33 #include "hw/pci/pci_bus.h" 34 #include "hw/pci/pci_host.h" 35 #include "hw/qdev-properties.h" 36 #include "hw/pci-host/sabre.h" 37 #include "hw/char/serial.h" 38 #include "hw/char/parallel.h" 39 #include "hw/rtc/m48t59.h" 40 #include "migration/vmstate.h" 41 #include "hw/input/i8042.h" 42 #include "hw/block/fdc.h" 43 #include "net/net.h" 44 #include "qemu/timer.h" 45 #include "sysemu/runstate.h" 46 #include "sysemu/sysemu.h" 47 #include "hw/boards.h" 48 #include "hw/nvram/sun_nvram.h" 49 #include "hw/nvram/chrp_nvram.h" 50 #include "hw/sparc/sparc64.h" 51 #include "hw/nvram/fw_cfg.h" 52 #include "hw/sysbus.h" 53 #include "hw/ide.h" 54 #include "hw/ide/pci.h" 55 #include "hw/loader.h" 56 #include "hw/fw-path-provider.h" 57 #include "elf.h" 58 #include "trace.h" 59 60 #define KERNEL_LOAD_ADDR 0x00404000 61 #define CMDLINE_ADDR 0x003ff000 62 #define PROM_SIZE_MAX (4 * MiB) 63 #define PROM_VADDR 0x000ffd00000ULL 64 #define PBM_SPECIAL_BASE 0x1fe00000000ULL 65 #define PBM_MEM_BASE 0x1ff00000000ULL 66 #define PBM_PCI_IO_BASE (PBM_SPECIAL_BASE + 0x02000000ULL) 67 #define PROM_FILENAME "openbios-sparc64" 68 #define NVRAM_SIZE 0x2000 69 #define MAX_IDE_BUS 2 70 #define BIOS_CFG_IOPORT 0x510 71 #define FW_CFG_SPARC64_WIDTH (FW_CFG_ARCH_LOCAL + 0x00) 72 #define FW_CFG_SPARC64_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01) 73 #define FW_CFG_SPARC64_DEPTH (FW_CFG_ARCH_LOCAL + 0x02) 74 75 #define IVEC_MAX 0x40 76 77 struct hwdef { 78 uint16_t machine_id; 79 uint64_t prom_addr; 80 uint64_t console_serial_base; 81 }; 82 83 typedef struct EbusState { 84 /*< private >*/ 85 PCIDevice parent_obj; 86 87 ISABus *isa_bus; 88 qemu_irq isa_bus_irqs[ISA_NUM_IRQS]; 89 uint64_t console_serial_base; 90 MemoryRegion bar0; 91 MemoryRegion bar1; 92 } EbusState; 93 94 #define TYPE_EBUS "ebus" 95 #define EBUS(obj) OBJECT_CHECK(EbusState, (obj), TYPE_EBUS) 96 97 const char *fw_cfg_arch_key_name(uint16_t key) 98 { 99 static const struct { 100 uint16_t key; 101 const char *name; 102 } fw_cfg_arch_wellknown_keys[] = { 103 {FW_CFG_SPARC64_WIDTH, "width"}, 104 {FW_CFG_SPARC64_HEIGHT, "height"}, 105 {FW_CFG_SPARC64_DEPTH, "depth"}, 106 }; 107 108 for (size_t i = 0; i < ARRAY_SIZE(fw_cfg_arch_wellknown_keys); i++) { 109 if (fw_cfg_arch_wellknown_keys[i].key == key) { 110 return fw_cfg_arch_wellknown_keys[i].name; 111 } 112 } 113 return NULL; 114 } 115 116 static void fw_cfg_boot_set(void *opaque, const char *boot_device, 117 Error **errp) 118 { 119 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); 120 } 121 122 static int sun4u_NVRAM_set_params(Nvram *nvram, uint16_t NVRAM_size, 123 const char *arch, ram_addr_t RAM_size, 124 const char *boot_devices, 125 uint32_t kernel_image, uint32_t kernel_size, 126 const char *cmdline, 127 uint32_t initrd_image, uint32_t initrd_size, 128 uint32_t NVRAM_image, 129 int width, int height, int depth, 130 const uint8_t *macaddr) 131 { 132 unsigned int i; 133 int sysp_end; 134 uint8_t image[0x1ff0]; 135 NvramClass *k = NVRAM_GET_CLASS(nvram); 136 137 memset(image, '\0', sizeof(image)); 138 139 /* OpenBIOS nvram variables partition */ 140 sysp_end = chrp_nvram_create_system_partition(image, 0); 141 142 /* Free space partition */ 143 chrp_nvram_create_free_partition(&image[sysp_end], 0x1fd0 - sysp_end); 144 145 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80); 146 147 for (i = 0; i < sizeof(image); i++) { 148 (k->write)(nvram, i, image[i]); 149 } 150 151 return 0; 152 } 153 154 static uint64_t sun4u_load_kernel(const char *kernel_filename, 155 const char *initrd_filename, 156 ram_addr_t RAM_size, uint64_t *initrd_size, 157 uint64_t *initrd_addr, uint64_t *kernel_addr, 158 uint64_t *kernel_entry) 159 { 160 int linux_boot; 161 unsigned int i; 162 long kernel_size; 163 uint8_t *ptr; 164 uint64_t kernel_top = 0; 165 166 linux_boot = (kernel_filename != NULL); 167 168 kernel_size = 0; 169 if (linux_boot) { 170 int bswap_needed; 171 172 #ifdef BSWAP_NEEDED 173 bswap_needed = 1; 174 #else 175 bswap_needed = 0; 176 #endif 177 kernel_size = load_elf(kernel_filename, NULL, NULL, NULL, kernel_entry, 178 kernel_addr, &kernel_top, NULL, 1, EM_SPARCV9, 0, 179 0); 180 if (kernel_size < 0) { 181 *kernel_addr = KERNEL_LOAD_ADDR; 182 *kernel_entry = KERNEL_LOAD_ADDR; 183 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR, 184 RAM_size - KERNEL_LOAD_ADDR, bswap_needed, 185 TARGET_PAGE_SIZE); 186 } 187 if (kernel_size < 0) { 188 kernel_size = load_image_targphys(kernel_filename, 189 KERNEL_LOAD_ADDR, 190 RAM_size - KERNEL_LOAD_ADDR); 191 } 192 if (kernel_size < 0) { 193 error_report("could not load kernel '%s'", kernel_filename); 194 exit(1); 195 } 196 /* load initrd above kernel */ 197 *initrd_size = 0; 198 if (initrd_filename && kernel_top) { 199 *initrd_addr = TARGET_PAGE_ALIGN(kernel_top); 200 201 *initrd_size = load_image_targphys(initrd_filename, 202 *initrd_addr, 203 RAM_size - *initrd_addr); 204 if ((int)*initrd_size < 0) { 205 error_report("could not load initial ram disk '%s'", 206 initrd_filename); 207 exit(1); 208 } 209 } 210 if (*initrd_size > 0) { 211 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { 212 ptr = rom_ptr(*kernel_addr + i, 32); 213 if (ptr && ldl_p(ptr + 8) == 0x48647253) { /* HdrS */ 214 stl_p(ptr + 24, *initrd_addr + *kernel_addr); 215 stl_p(ptr + 28, *initrd_size); 216 break; 217 } 218 } 219 } 220 } 221 return kernel_size; 222 } 223 224 typedef struct ResetData { 225 SPARCCPU *cpu; 226 uint64_t prom_addr; 227 } ResetData; 228 229 #define TYPE_SUN4U_POWER "power" 230 #define SUN4U_POWER(obj) OBJECT_CHECK(PowerDevice, (obj), TYPE_SUN4U_POWER) 231 232 typedef struct PowerDevice { 233 SysBusDevice parent_obj; 234 235 MemoryRegion power_mmio; 236 } PowerDevice; 237 238 /* Power */ 239 static uint64_t power_mem_read(void *opaque, hwaddr addr, unsigned size) 240 { 241 return 0; 242 } 243 244 static void power_mem_write(void *opaque, hwaddr addr, 245 uint64_t val, unsigned size) 246 { 247 /* According to a real Ultra 5, bit 24 controls the power */ 248 if (val & 0x1000000) { 249 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); 250 } 251 } 252 253 static const MemoryRegionOps power_mem_ops = { 254 .read = power_mem_read, 255 .write = power_mem_write, 256 .endianness = DEVICE_NATIVE_ENDIAN, 257 .valid = { 258 .min_access_size = 4, 259 .max_access_size = 4, 260 }, 261 }; 262 263 static void power_realize(DeviceState *dev, Error **errp) 264 { 265 PowerDevice *d = SUN4U_POWER(dev); 266 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 267 268 memory_region_init_io(&d->power_mmio, OBJECT(dev), &power_mem_ops, d, 269 "power", sizeof(uint32_t)); 270 271 sysbus_init_mmio(sbd, &d->power_mmio); 272 } 273 274 static void power_class_init(ObjectClass *klass, void *data) 275 { 276 DeviceClass *dc = DEVICE_CLASS(klass); 277 278 dc->realize = power_realize; 279 } 280 281 static const TypeInfo power_info = { 282 .name = TYPE_SUN4U_POWER, 283 .parent = TYPE_SYS_BUS_DEVICE, 284 .instance_size = sizeof(PowerDevice), 285 .class_init = power_class_init, 286 }; 287 288 static void ebus_isa_irq_handler(void *opaque, int n, int level) 289 { 290 EbusState *s = EBUS(opaque); 291 qemu_irq irq = s->isa_bus_irqs[n]; 292 293 /* Pass ISA bus IRQs onto their gpio equivalent */ 294 trace_ebus_isa_irq_handler(n, level); 295 if (irq) { 296 qemu_set_irq(irq, level); 297 } 298 } 299 300 /* EBUS (Eight bit bus) bridge */ 301 static void ebus_realize(PCIDevice *pci_dev, Error **errp) 302 { 303 EbusState *s = EBUS(pci_dev); 304 SysBusDevice *sbd; 305 DeviceState *dev; 306 qemu_irq *isa_irq; 307 DriveInfo *fd[MAX_FD]; 308 int i; 309 310 s->isa_bus = isa_bus_new(DEVICE(pci_dev), get_system_memory(), 311 pci_address_space_io(pci_dev), errp); 312 if (!s->isa_bus) { 313 error_setg(errp, "unable to instantiate EBUS ISA bus"); 314 return; 315 } 316 317 /* ISA bus */ 318 isa_irq = qemu_allocate_irqs(ebus_isa_irq_handler, s, ISA_NUM_IRQS); 319 isa_bus_irqs(s->isa_bus, isa_irq); 320 qdev_init_gpio_out_named(DEVICE(s), s->isa_bus_irqs, "isa-irq", 321 ISA_NUM_IRQS); 322 323 /* Serial ports */ 324 i = 0; 325 if (s->console_serial_base) { 326 serial_mm_init(pci_address_space(pci_dev), s->console_serial_base, 327 0, NULL, 115200, serial_hd(i), DEVICE_BIG_ENDIAN); 328 i++; 329 } 330 serial_hds_isa_init(s->isa_bus, i, MAX_ISA_SERIAL_PORTS); 331 332 /* Parallel ports */ 333 parallel_hds_isa_init(s->isa_bus, MAX_PARALLEL_PORTS); 334 335 /* Keyboard */ 336 isa_create_simple(s->isa_bus, "i8042"); 337 338 /* Floppy */ 339 for (i = 0; i < MAX_FD; i++) { 340 fd[i] = drive_get(IF_FLOPPY, 0, i); 341 } 342 dev = DEVICE(isa_create(s->isa_bus, TYPE_ISA_FDC)); 343 if (fd[0]) { 344 qdev_prop_set_drive(dev, "driveA", blk_by_legacy_dinfo(fd[0]), 345 &error_abort); 346 } 347 if (fd[1]) { 348 qdev_prop_set_drive(dev, "driveB", blk_by_legacy_dinfo(fd[1]), 349 &error_abort); 350 } 351 qdev_prop_set_uint32(dev, "dma", -1); 352 qdev_init_nofail(dev); 353 354 /* Power */ 355 dev = qdev_create(NULL, TYPE_SUN4U_POWER); 356 qdev_init_nofail(dev); 357 sbd = SYS_BUS_DEVICE(dev); 358 memory_region_add_subregion(pci_address_space_io(pci_dev), 0x7240, 359 sysbus_mmio_get_region(sbd, 0)); 360 361 /* PCI */ 362 pci_dev->config[0x04] = 0x06; // command = bus master, pci mem 363 pci_dev->config[0x05] = 0x00; 364 pci_dev->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error 365 pci_dev->config[0x07] = 0x03; // status = medium devsel 366 pci_dev->config[0x09] = 0x00; // programming i/f 367 pci_dev->config[0x0D] = 0x0a; // latency_timer 368 369 memory_region_init_alias(&s->bar0, OBJECT(s), "bar0", get_system_io(), 370 0, 0x1000000); 371 pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0); 372 memory_region_init_alias(&s->bar1, OBJECT(s), "bar1", get_system_io(), 373 0, 0x8000); 374 pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->bar1); 375 } 376 377 static Property ebus_properties[] = { 378 DEFINE_PROP_UINT64("console-serial-base", EbusState, 379 console_serial_base, 0), 380 DEFINE_PROP_END_OF_LIST(), 381 }; 382 383 static void ebus_class_init(ObjectClass *klass, void *data) 384 { 385 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 386 DeviceClass *dc = DEVICE_CLASS(klass); 387 388 k->realize = ebus_realize; 389 k->vendor_id = PCI_VENDOR_ID_SUN; 390 k->device_id = PCI_DEVICE_ID_SUN_EBUS; 391 k->revision = 0x01; 392 k->class_id = PCI_CLASS_BRIDGE_OTHER; 393 device_class_set_props(dc, ebus_properties); 394 } 395 396 static const TypeInfo ebus_info = { 397 .name = TYPE_EBUS, 398 .parent = TYPE_PCI_DEVICE, 399 .class_init = ebus_class_init, 400 .instance_size = sizeof(EbusState), 401 .interfaces = (InterfaceInfo[]) { 402 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 403 { }, 404 }, 405 }; 406 407 #define TYPE_OPENPROM "openprom" 408 #define OPENPROM(obj) OBJECT_CHECK(PROMState, (obj), TYPE_OPENPROM) 409 410 typedef struct PROMState { 411 SysBusDevice parent_obj; 412 413 MemoryRegion prom; 414 } PROMState; 415 416 static uint64_t translate_prom_address(void *opaque, uint64_t addr) 417 { 418 hwaddr *base_addr = (hwaddr *)opaque; 419 return addr + *base_addr - PROM_VADDR; 420 } 421 422 /* Boot PROM (OpenBIOS) */ 423 static void prom_init(hwaddr addr, const char *bios_name) 424 { 425 DeviceState *dev; 426 SysBusDevice *s; 427 char *filename; 428 int ret; 429 430 dev = qdev_create(NULL, TYPE_OPENPROM); 431 qdev_init_nofail(dev); 432 s = SYS_BUS_DEVICE(dev); 433 434 sysbus_mmio_map(s, 0, addr); 435 436 /* load boot prom */ 437 if (bios_name == NULL) { 438 bios_name = PROM_FILENAME; 439 } 440 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 441 if (filename) { 442 ret = load_elf(filename, NULL, translate_prom_address, &addr, 443 NULL, NULL, NULL, NULL, 1, EM_SPARCV9, 0, 0); 444 if (ret < 0 || ret > PROM_SIZE_MAX) { 445 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX); 446 } 447 g_free(filename); 448 } else { 449 ret = -1; 450 } 451 if (ret < 0 || ret > PROM_SIZE_MAX) { 452 error_report("could not load prom '%s'", bios_name); 453 exit(1); 454 } 455 } 456 457 static void prom_realize(DeviceState *ds, Error **errp) 458 { 459 PROMState *s = OPENPROM(ds); 460 SysBusDevice *dev = SYS_BUS_DEVICE(ds); 461 Error *local_err = NULL; 462 463 memory_region_init_ram_nomigrate(&s->prom, OBJECT(ds), "sun4u.prom", 464 PROM_SIZE_MAX, &local_err); 465 if (local_err) { 466 error_propagate(errp, local_err); 467 return; 468 } 469 470 vmstate_register_ram_global(&s->prom); 471 memory_region_set_readonly(&s->prom, true); 472 sysbus_init_mmio(dev, &s->prom); 473 } 474 475 static Property prom_properties[] = { 476 {/* end of property list */}, 477 }; 478 479 static void prom_class_init(ObjectClass *klass, void *data) 480 { 481 DeviceClass *dc = DEVICE_CLASS(klass); 482 483 device_class_set_props(dc, prom_properties); 484 dc->realize = prom_realize; 485 } 486 487 static const TypeInfo prom_info = { 488 .name = TYPE_OPENPROM, 489 .parent = TYPE_SYS_BUS_DEVICE, 490 .instance_size = sizeof(PROMState), 491 .class_init = prom_class_init, 492 }; 493 494 495 #define TYPE_SUN4U_MEMORY "memory" 496 #define SUN4U_RAM(obj) OBJECT_CHECK(RamDevice, (obj), TYPE_SUN4U_MEMORY) 497 498 typedef struct RamDevice { 499 SysBusDevice parent_obj; 500 501 MemoryRegion ram; 502 uint64_t size; 503 } RamDevice; 504 505 /* System RAM */ 506 static void ram_realize(DeviceState *dev, Error **errp) 507 { 508 RamDevice *d = SUN4U_RAM(dev); 509 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 510 511 memory_region_init_ram_nomigrate(&d->ram, OBJECT(d), "sun4u.ram", d->size, 512 &error_fatal); 513 vmstate_register_ram_global(&d->ram); 514 sysbus_init_mmio(sbd, &d->ram); 515 } 516 517 static void ram_init(hwaddr addr, ram_addr_t RAM_size) 518 { 519 DeviceState *dev; 520 SysBusDevice *s; 521 RamDevice *d; 522 523 /* allocate RAM */ 524 dev = qdev_create(NULL, TYPE_SUN4U_MEMORY); 525 s = SYS_BUS_DEVICE(dev); 526 527 d = SUN4U_RAM(dev); 528 d->size = RAM_size; 529 qdev_init_nofail(dev); 530 531 sysbus_mmio_map(s, 0, addr); 532 } 533 534 static Property ram_properties[] = { 535 DEFINE_PROP_UINT64("size", RamDevice, size, 0), 536 DEFINE_PROP_END_OF_LIST(), 537 }; 538 539 static void ram_class_init(ObjectClass *klass, void *data) 540 { 541 DeviceClass *dc = DEVICE_CLASS(klass); 542 543 dc->realize = ram_realize; 544 device_class_set_props(dc, ram_properties); 545 } 546 547 static const TypeInfo ram_info = { 548 .name = TYPE_SUN4U_MEMORY, 549 .parent = TYPE_SYS_BUS_DEVICE, 550 .instance_size = sizeof(RamDevice), 551 .class_init = ram_class_init, 552 }; 553 554 static void sun4uv_init(MemoryRegion *address_space_mem, 555 MachineState *machine, 556 const struct hwdef *hwdef) 557 { 558 SPARCCPU *cpu; 559 Nvram *nvram; 560 unsigned int i; 561 uint64_t initrd_addr, initrd_size, kernel_addr, kernel_size, kernel_entry; 562 SabreState *sabre; 563 PCIBus *pci_bus, *pci_busA, *pci_busB; 564 PCIDevice *ebus, *pci_dev; 565 SysBusDevice *s; 566 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; 567 DeviceState *iommu, *dev; 568 FWCfgState *fw_cfg; 569 NICInfo *nd; 570 MACAddr macaddr; 571 bool onboard_nic; 572 573 /* init CPUs */ 574 cpu = sparc64_cpu_devinit(machine->cpu_type, hwdef->prom_addr); 575 576 /* IOMMU */ 577 iommu = qdev_create(NULL, TYPE_SUN4U_IOMMU); 578 qdev_init_nofail(iommu); 579 580 /* set up devices */ 581 ram_init(0, machine->ram_size); 582 583 prom_init(hwdef->prom_addr, bios_name); 584 585 /* Init sabre (PCI host bridge) */ 586 sabre = SABRE_DEVICE(qdev_create(NULL, TYPE_SABRE)); 587 qdev_prop_set_uint64(DEVICE(sabre), "special-base", PBM_SPECIAL_BASE); 588 qdev_prop_set_uint64(DEVICE(sabre), "mem-base", PBM_MEM_BASE); 589 object_property_set_link(OBJECT(sabre), OBJECT(iommu), "iommu", 590 &error_abort); 591 qdev_init_nofail(DEVICE(sabre)); 592 593 /* Wire up PCI interrupts to CPU */ 594 for (i = 0; i < IVEC_MAX; i++) { 595 qdev_connect_gpio_out_named(DEVICE(sabre), "ivec-irq", i, 596 qdev_get_gpio_in_named(DEVICE(cpu), "ivec-irq", i)); 597 } 598 599 pci_bus = PCI_HOST_BRIDGE(sabre)->bus; 600 pci_busA = pci_bridge_get_sec_bus(sabre->bridgeA); 601 pci_busB = pci_bridge_get_sec_bus(sabre->bridgeB); 602 603 /* Only in-built Simba APBs can exist on the root bus, slot 0 on busA is 604 reserved (leaving no slots free after on-board devices) however slots 605 0-3 are free on busB */ 606 pci_bus->slot_reserved_mask = 0xfffffffc; 607 pci_busA->slot_reserved_mask = 0xfffffff1; 608 pci_busB->slot_reserved_mask = 0xfffffff0; 609 610 ebus = pci_create_multifunction(pci_busA, PCI_DEVFN(1, 0), true, TYPE_EBUS); 611 qdev_prop_set_uint64(DEVICE(ebus), "console-serial-base", 612 hwdef->console_serial_base); 613 qdev_init_nofail(DEVICE(ebus)); 614 615 /* Wire up "well-known" ISA IRQs to PBM legacy obio IRQs */ 616 qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 7, 617 qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_LPT_IRQ)); 618 qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 6, 619 qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_FDD_IRQ)); 620 qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 1, 621 qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_KBD_IRQ)); 622 qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 12, 623 qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_MSE_IRQ)); 624 qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 4, 625 qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_SER_IRQ)); 626 627 switch (vga_interface_type) { 628 case VGA_STD: 629 pci_create_simple(pci_busA, PCI_DEVFN(2, 0), "VGA"); 630 break; 631 case VGA_NONE: 632 break; 633 default: 634 abort(); /* Should not happen - types are checked in vl.c already */ 635 } 636 637 memset(&macaddr, 0, sizeof(MACAddr)); 638 onboard_nic = false; 639 for (i = 0; i < nb_nics; i++) { 640 nd = &nd_table[i]; 641 642 if (!nd->model || strcmp(nd->model, "sunhme") == 0) { 643 if (!onboard_nic) { 644 pci_dev = pci_create_multifunction(pci_busA, PCI_DEVFN(1, 1), 645 true, "sunhme"); 646 memcpy(&macaddr, &nd->macaddr.a, sizeof(MACAddr)); 647 onboard_nic = true; 648 } else { 649 pci_dev = pci_create(pci_busB, -1, "sunhme"); 650 } 651 } else { 652 pci_dev = pci_create(pci_busB, -1, nd->model); 653 } 654 655 dev = &pci_dev->qdev; 656 qdev_set_nic_properties(dev, nd); 657 qdev_init_nofail(dev); 658 } 659 660 /* If we don't have an onboard NIC, grab a default MAC address so that 661 * we have a valid machine id */ 662 if (!onboard_nic) { 663 qemu_macaddr_default_if_unset(&macaddr); 664 } 665 666 ide_drive_get(hd, ARRAY_SIZE(hd)); 667 668 pci_dev = pci_create(pci_busA, PCI_DEVFN(3, 0), "cmd646-ide"); 669 qdev_prop_set_uint32(&pci_dev->qdev, "secondary", 1); 670 qdev_init_nofail(&pci_dev->qdev); 671 pci_ide_create_devs(pci_dev, hd); 672 673 /* Map NVRAM into I/O (ebus) space */ 674 nvram = m48t59_init(NULL, 0, 0, NVRAM_SIZE, 1968, 59); 675 s = SYS_BUS_DEVICE(nvram); 676 memory_region_add_subregion(pci_address_space_io(ebus), 0x2000, 677 sysbus_mmio_get_region(s, 0)); 678 679 initrd_size = 0; 680 initrd_addr = 0; 681 kernel_size = sun4u_load_kernel(machine->kernel_filename, 682 machine->initrd_filename, 683 ram_size, &initrd_size, &initrd_addr, 684 &kernel_addr, &kernel_entry); 685 686 sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", machine->ram_size, 687 machine->boot_order, 688 kernel_addr, kernel_size, 689 machine->kernel_cmdline, 690 initrd_addr, initrd_size, 691 /* XXX: need an option to load a NVRAM image */ 692 0, 693 graphic_width, graphic_height, graphic_depth, 694 (uint8_t *)&macaddr); 695 696 dev = qdev_create(NULL, TYPE_FW_CFG_IO); 697 qdev_prop_set_bit(dev, "dma_enabled", false); 698 object_property_add_child(OBJECT(ebus), TYPE_FW_CFG, OBJECT(dev), NULL); 699 qdev_init_nofail(dev); 700 memory_region_add_subregion(pci_address_space_io(ebus), BIOS_CFG_IOPORT, 701 &FW_CFG_IO(dev)->comb_iomem); 702 703 fw_cfg = FW_CFG(dev); 704 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)machine->smp.cpus); 705 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)machine->smp.max_cpus); 706 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 707 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); 708 fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_entry); 709 fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 710 if (machine->kernel_cmdline) { 711 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 712 strlen(machine->kernel_cmdline) + 1); 713 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline); 714 } else { 715 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0); 716 } 717 fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); 718 fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 719 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]); 720 721 fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_WIDTH, graphic_width); 722 fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_HEIGHT, graphic_height); 723 fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_DEPTH, graphic_depth); 724 725 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); 726 } 727 728 enum { 729 sun4u_id = 0, 730 sun4v_id = 64, 731 }; 732 733 /* 734 * Implementation of an interface to adjust firmware path 735 * for the bootindex property handling. 736 */ 737 static char *sun4u_fw_dev_path(FWPathProvider *p, BusState *bus, 738 DeviceState *dev) 739 { 740 PCIDevice *pci; 741 IDEBus *ide_bus; 742 IDEState *ide_s; 743 int bus_id; 744 745 if (!strcmp(object_get_typename(OBJECT(dev)), "pbm-bridge")) { 746 pci = PCI_DEVICE(dev); 747 748 if (PCI_FUNC(pci->devfn)) { 749 return g_strdup_printf("pci@%x,%x", PCI_SLOT(pci->devfn), 750 PCI_FUNC(pci->devfn)); 751 } else { 752 return g_strdup_printf("pci@%x", PCI_SLOT(pci->devfn)); 753 } 754 } 755 756 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-drive")) { 757 ide_bus = IDE_BUS(qdev_get_parent_bus(dev)); 758 ide_s = idebus_active_if(ide_bus); 759 bus_id = ide_bus->bus_id; 760 761 if (ide_s->drive_kind == IDE_CD) { 762 return g_strdup_printf("ide@%x/cdrom", bus_id); 763 } 764 765 return g_strdup_printf("ide@%x/disk", bus_id); 766 } 767 768 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-hd")) { 769 return g_strdup("disk"); 770 } 771 772 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-cd")) { 773 return g_strdup("cdrom"); 774 } 775 776 if (!strcmp(object_get_typename(OBJECT(dev)), "virtio-blk-device")) { 777 return g_strdup("disk"); 778 } 779 780 return NULL; 781 } 782 783 static const struct hwdef hwdefs[] = { 784 /* Sun4u generic PC-like machine */ 785 { 786 .machine_id = sun4u_id, 787 .prom_addr = 0x1fff0000000ULL, 788 .console_serial_base = 0, 789 }, 790 /* Sun4v generic PC-like machine */ 791 { 792 .machine_id = sun4v_id, 793 .prom_addr = 0x1fff0000000ULL, 794 .console_serial_base = 0, 795 }, 796 }; 797 798 /* Sun4u hardware initialisation */ 799 static void sun4u_init(MachineState *machine) 800 { 801 sun4uv_init(get_system_memory(), machine, &hwdefs[0]); 802 } 803 804 /* Sun4v hardware initialisation */ 805 static void sun4v_init(MachineState *machine) 806 { 807 sun4uv_init(get_system_memory(), machine, &hwdefs[1]); 808 } 809 810 static void sun4u_class_init(ObjectClass *oc, void *data) 811 { 812 MachineClass *mc = MACHINE_CLASS(oc); 813 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 814 815 mc->desc = "Sun4u platform"; 816 mc->init = sun4u_init; 817 mc->block_default_type = IF_IDE; 818 mc->max_cpus = 1; /* XXX for now */ 819 mc->is_default = 1; 820 mc->default_boot_order = "c"; 821 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-UltraSparc-IIi"); 822 mc->ignore_boot_device_suffixes = true; 823 mc->default_display = "std"; 824 fwc->get_dev_path = sun4u_fw_dev_path; 825 } 826 827 static const TypeInfo sun4u_type = { 828 .name = MACHINE_TYPE_NAME("sun4u"), 829 .parent = TYPE_MACHINE, 830 .class_init = sun4u_class_init, 831 .interfaces = (InterfaceInfo[]) { 832 { TYPE_FW_PATH_PROVIDER }, 833 { } 834 }, 835 }; 836 837 static void sun4v_class_init(ObjectClass *oc, void *data) 838 { 839 MachineClass *mc = MACHINE_CLASS(oc); 840 841 mc->desc = "Sun4v platform"; 842 mc->init = sun4v_init; 843 mc->block_default_type = IF_IDE; 844 mc->max_cpus = 1; /* XXX for now */ 845 mc->default_boot_order = "c"; 846 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Sun-UltraSparc-T1"); 847 mc->default_display = "std"; 848 } 849 850 static const TypeInfo sun4v_type = { 851 .name = MACHINE_TYPE_NAME("sun4v"), 852 .parent = TYPE_MACHINE, 853 .class_init = sun4v_class_init, 854 }; 855 856 static void sun4u_register_types(void) 857 { 858 type_register_static(&power_info); 859 type_register_static(&ebus_info); 860 type_register_static(&prom_info); 861 type_register_static(&ram_info); 862 863 type_register_static(&sun4u_type); 864 type_register_static(&sun4v_type); 865 } 866 867 type_init(sun4u_register_types) 868