1 /* 2 * QEMU Sun4u/Sun4v System Emulator 3 * 4 * Copyright (c) 2005 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "qemu/error-report.h" 28 #include "qapi/error.h" 29 #include "qemu-common.h" 30 #include "cpu.h" 31 #include "hw/pci/pci.h" 32 #include "hw/pci/pci_bridge.h" 33 #include "hw/pci/pci_bus.h" 34 #include "hw/pci/pci_host.h" 35 #include "hw/pci-host/sabre.h" 36 #include "hw/char/serial.h" 37 #include "hw/char/parallel.h" 38 #include "hw/timer/m48t59.h" 39 #include "migration/vmstate.h" 40 #include "hw/input/i8042.h" 41 #include "hw/block/fdc.h" 42 #include "net/net.h" 43 #include "qemu/timer.h" 44 #include "sysemu/sysemu.h" 45 #include "hw/boards.h" 46 #include "hw/nvram/sun_nvram.h" 47 #include "hw/nvram/chrp_nvram.h" 48 #include "hw/sparc/sparc64.h" 49 #include "hw/nvram/fw_cfg.h" 50 #include "hw/sysbus.h" 51 #include "hw/ide.h" 52 #include "hw/ide/pci.h" 53 #include "hw/loader.h" 54 #include "hw/fw-path-provider.h" 55 #include "elf.h" 56 #include "trace.h" 57 58 #define KERNEL_LOAD_ADDR 0x00404000 59 #define CMDLINE_ADDR 0x003ff000 60 #define PROM_SIZE_MAX (4 * MiB) 61 #define PROM_VADDR 0x000ffd00000ULL 62 #define PBM_SPECIAL_BASE 0x1fe00000000ULL 63 #define PBM_MEM_BASE 0x1ff00000000ULL 64 #define PBM_PCI_IO_BASE (PBM_SPECIAL_BASE + 0x02000000ULL) 65 #define PROM_FILENAME "openbios-sparc64" 66 #define NVRAM_SIZE 0x2000 67 #define MAX_IDE_BUS 2 68 #define BIOS_CFG_IOPORT 0x510 69 #define FW_CFG_SPARC64_WIDTH (FW_CFG_ARCH_LOCAL + 0x00) 70 #define FW_CFG_SPARC64_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01) 71 #define FW_CFG_SPARC64_DEPTH (FW_CFG_ARCH_LOCAL + 0x02) 72 73 #define IVEC_MAX 0x40 74 75 struct hwdef { 76 uint16_t machine_id; 77 uint64_t prom_addr; 78 uint64_t console_serial_base; 79 }; 80 81 typedef struct EbusState { 82 /*< private >*/ 83 PCIDevice parent_obj; 84 85 ISABus *isa_bus; 86 qemu_irq isa_bus_irqs[ISA_NUM_IRQS]; 87 uint64_t console_serial_base; 88 MemoryRegion bar0; 89 MemoryRegion bar1; 90 } EbusState; 91 92 #define TYPE_EBUS "ebus" 93 #define EBUS(obj) OBJECT_CHECK(EbusState, (obj), TYPE_EBUS) 94 95 const char *fw_cfg_arch_key_name(uint16_t key) 96 { 97 static const struct { 98 uint16_t key; 99 const char *name; 100 } fw_cfg_arch_wellknown_keys[] = { 101 {FW_CFG_SPARC64_WIDTH, "width"}, 102 {FW_CFG_SPARC64_HEIGHT, "height"}, 103 {FW_CFG_SPARC64_DEPTH, "depth"}, 104 }; 105 106 for (size_t i = 0; i < ARRAY_SIZE(fw_cfg_arch_wellknown_keys); i++) { 107 if (fw_cfg_arch_wellknown_keys[i].key == key) { 108 return fw_cfg_arch_wellknown_keys[i].name; 109 } 110 } 111 return NULL; 112 } 113 114 static void fw_cfg_boot_set(void *opaque, const char *boot_device, 115 Error **errp) 116 { 117 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); 118 } 119 120 static int sun4u_NVRAM_set_params(Nvram *nvram, uint16_t NVRAM_size, 121 const char *arch, ram_addr_t RAM_size, 122 const char *boot_devices, 123 uint32_t kernel_image, uint32_t kernel_size, 124 const char *cmdline, 125 uint32_t initrd_image, uint32_t initrd_size, 126 uint32_t NVRAM_image, 127 int width, int height, int depth, 128 const uint8_t *macaddr) 129 { 130 unsigned int i; 131 int sysp_end; 132 uint8_t image[0x1ff0]; 133 NvramClass *k = NVRAM_GET_CLASS(nvram); 134 135 memset(image, '\0', sizeof(image)); 136 137 /* OpenBIOS nvram variables partition */ 138 sysp_end = chrp_nvram_create_system_partition(image, 0); 139 140 /* Free space partition */ 141 chrp_nvram_create_free_partition(&image[sysp_end], 0x1fd0 - sysp_end); 142 143 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80); 144 145 for (i = 0; i < sizeof(image); i++) { 146 (k->write)(nvram, i, image[i]); 147 } 148 149 return 0; 150 } 151 152 static uint64_t sun4u_load_kernel(const char *kernel_filename, 153 const char *initrd_filename, 154 ram_addr_t RAM_size, uint64_t *initrd_size, 155 uint64_t *initrd_addr, uint64_t *kernel_addr, 156 uint64_t *kernel_entry) 157 { 158 int linux_boot; 159 unsigned int i; 160 long kernel_size; 161 uint8_t *ptr; 162 uint64_t kernel_top = 0; 163 164 linux_boot = (kernel_filename != NULL); 165 166 kernel_size = 0; 167 if (linux_boot) { 168 int bswap_needed; 169 170 #ifdef BSWAP_NEEDED 171 bswap_needed = 1; 172 #else 173 bswap_needed = 0; 174 #endif 175 kernel_size = load_elf(kernel_filename, NULL, NULL, NULL, kernel_entry, 176 kernel_addr, &kernel_top, 1, EM_SPARCV9, 0, 0); 177 if (kernel_size < 0) { 178 *kernel_addr = KERNEL_LOAD_ADDR; 179 *kernel_entry = KERNEL_LOAD_ADDR; 180 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR, 181 RAM_size - KERNEL_LOAD_ADDR, bswap_needed, 182 TARGET_PAGE_SIZE); 183 } 184 if (kernel_size < 0) { 185 kernel_size = load_image_targphys(kernel_filename, 186 KERNEL_LOAD_ADDR, 187 RAM_size - KERNEL_LOAD_ADDR); 188 } 189 if (kernel_size < 0) { 190 error_report("could not load kernel '%s'", kernel_filename); 191 exit(1); 192 } 193 /* load initrd above kernel */ 194 *initrd_size = 0; 195 if (initrd_filename && kernel_top) { 196 *initrd_addr = TARGET_PAGE_ALIGN(kernel_top); 197 198 *initrd_size = load_image_targphys(initrd_filename, 199 *initrd_addr, 200 RAM_size - *initrd_addr); 201 if ((int)*initrd_size < 0) { 202 error_report("could not load initial ram disk '%s'", 203 initrd_filename); 204 exit(1); 205 } 206 } 207 if (*initrd_size > 0) { 208 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { 209 ptr = rom_ptr(*kernel_addr + i, 32); 210 if (ptr && ldl_p(ptr + 8) == 0x48647253) { /* HdrS */ 211 stl_p(ptr + 24, *initrd_addr + *kernel_addr); 212 stl_p(ptr + 28, *initrd_size); 213 break; 214 } 215 } 216 } 217 } 218 return kernel_size; 219 } 220 221 typedef struct ResetData { 222 SPARCCPU *cpu; 223 uint64_t prom_addr; 224 } ResetData; 225 226 #define TYPE_SUN4U_POWER "power" 227 #define SUN4U_POWER(obj) OBJECT_CHECK(PowerDevice, (obj), TYPE_SUN4U_POWER) 228 229 typedef struct PowerDevice { 230 SysBusDevice parent_obj; 231 232 MemoryRegion power_mmio; 233 } PowerDevice; 234 235 /* Power */ 236 static uint64_t power_mem_read(void *opaque, hwaddr addr, unsigned size) 237 { 238 return 0; 239 } 240 241 static void power_mem_write(void *opaque, hwaddr addr, 242 uint64_t val, unsigned size) 243 { 244 /* According to a real Ultra 5, bit 24 controls the power */ 245 if (val & 0x1000000) { 246 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); 247 } 248 } 249 250 static const MemoryRegionOps power_mem_ops = { 251 .read = power_mem_read, 252 .write = power_mem_write, 253 .endianness = DEVICE_NATIVE_ENDIAN, 254 .valid = { 255 .min_access_size = 4, 256 .max_access_size = 4, 257 }, 258 }; 259 260 static void power_realize(DeviceState *dev, Error **errp) 261 { 262 PowerDevice *d = SUN4U_POWER(dev); 263 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 264 265 memory_region_init_io(&d->power_mmio, OBJECT(dev), &power_mem_ops, d, 266 "power", sizeof(uint32_t)); 267 268 sysbus_init_mmio(sbd, &d->power_mmio); 269 } 270 271 static void power_class_init(ObjectClass *klass, void *data) 272 { 273 DeviceClass *dc = DEVICE_CLASS(klass); 274 275 dc->realize = power_realize; 276 } 277 278 static const TypeInfo power_info = { 279 .name = TYPE_SUN4U_POWER, 280 .parent = TYPE_SYS_BUS_DEVICE, 281 .instance_size = sizeof(PowerDevice), 282 .class_init = power_class_init, 283 }; 284 285 static void ebus_isa_irq_handler(void *opaque, int n, int level) 286 { 287 EbusState *s = EBUS(opaque); 288 qemu_irq irq = s->isa_bus_irqs[n]; 289 290 /* Pass ISA bus IRQs onto their gpio equivalent */ 291 trace_ebus_isa_irq_handler(n, level); 292 if (irq) { 293 qemu_set_irq(irq, level); 294 } 295 } 296 297 /* EBUS (Eight bit bus) bridge */ 298 static void ebus_realize(PCIDevice *pci_dev, Error **errp) 299 { 300 EbusState *s = EBUS(pci_dev); 301 SysBusDevice *sbd; 302 DeviceState *dev; 303 qemu_irq *isa_irq; 304 DriveInfo *fd[MAX_FD]; 305 int i; 306 307 s->isa_bus = isa_bus_new(DEVICE(pci_dev), get_system_memory(), 308 pci_address_space_io(pci_dev), errp); 309 if (!s->isa_bus) { 310 error_setg(errp, "unable to instantiate EBUS ISA bus"); 311 return; 312 } 313 314 /* ISA bus */ 315 isa_irq = qemu_allocate_irqs(ebus_isa_irq_handler, s, ISA_NUM_IRQS); 316 isa_bus_irqs(s->isa_bus, isa_irq); 317 qdev_init_gpio_out_named(DEVICE(s), s->isa_bus_irqs, "isa-irq", 318 ISA_NUM_IRQS); 319 320 /* Serial ports */ 321 i = 0; 322 if (s->console_serial_base) { 323 serial_mm_init(pci_address_space(pci_dev), s->console_serial_base, 324 0, NULL, 115200, serial_hd(i), DEVICE_BIG_ENDIAN); 325 i++; 326 } 327 serial_hds_isa_init(s->isa_bus, i, MAX_ISA_SERIAL_PORTS); 328 329 /* Parallel ports */ 330 parallel_hds_isa_init(s->isa_bus, MAX_PARALLEL_PORTS); 331 332 /* Keyboard */ 333 isa_create_simple(s->isa_bus, "i8042"); 334 335 /* Floppy */ 336 for (i = 0; i < MAX_FD; i++) { 337 fd[i] = drive_get(IF_FLOPPY, 0, i); 338 } 339 dev = DEVICE(isa_create(s->isa_bus, TYPE_ISA_FDC)); 340 if (fd[0]) { 341 qdev_prop_set_drive(dev, "driveA", blk_by_legacy_dinfo(fd[0]), 342 &error_abort); 343 } 344 if (fd[1]) { 345 qdev_prop_set_drive(dev, "driveB", blk_by_legacy_dinfo(fd[1]), 346 &error_abort); 347 } 348 qdev_prop_set_uint32(dev, "dma", -1); 349 qdev_init_nofail(dev); 350 351 /* Power */ 352 dev = qdev_create(NULL, TYPE_SUN4U_POWER); 353 qdev_init_nofail(dev); 354 sbd = SYS_BUS_DEVICE(dev); 355 memory_region_add_subregion(pci_address_space_io(pci_dev), 0x7240, 356 sysbus_mmio_get_region(sbd, 0)); 357 358 /* PCI */ 359 pci_dev->config[0x04] = 0x06; // command = bus master, pci mem 360 pci_dev->config[0x05] = 0x00; 361 pci_dev->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error 362 pci_dev->config[0x07] = 0x03; // status = medium devsel 363 pci_dev->config[0x09] = 0x00; // programming i/f 364 pci_dev->config[0x0D] = 0x0a; // latency_timer 365 366 memory_region_init_alias(&s->bar0, OBJECT(s), "bar0", get_system_io(), 367 0, 0x1000000); 368 pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0); 369 memory_region_init_alias(&s->bar1, OBJECT(s), "bar1", get_system_io(), 370 0, 0x8000); 371 pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->bar1); 372 } 373 374 static Property ebus_properties[] = { 375 DEFINE_PROP_UINT64("console-serial-base", EbusState, 376 console_serial_base, 0), 377 DEFINE_PROP_END_OF_LIST(), 378 }; 379 380 static void ebus_class_init(ObjectClass *klass, void *data) 381 { 382 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 383 DeviceClass *dc = DEVICE_CLASS(klass); 384 385 k->realize = ebus_realize; 386 k->vendor_id = PCI_VENDOR_ID_SUN; 387 k->device_id = PCI_DEVICE_ID_SUN_EBUS; 388 k->revision = 0x01; 389 k->class_id = PCI_CLASS_BRIDGE_OTHER; 390 dc->props = ebus_properties; 391 } 392 393 static const TypeInfo ebus_info = { 394 .name = TYPE_EBUS, 395 .parent = TYPE_PCI_DEVICE, 396 .class_init = ebus_class_init, 397 .instance_size = sizeof(EbusState), 398 .interfaces = (InterfaceInfo[]) { 399 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 400 { }, 401 }, 402 }; 403 404 #define TYPE_OPENPROM "openprom" 405 #define OPENPROM(obj) OBJECT_CHECK(PROMState, (obj), TYPE_OPENPROM) 406 407 typedef struct PROMState { 408 SysBusDevice parent_obj; 409 410 MemoryRegion prom; 411 } PROMState; 412 413 static uint64_t translate_prom_address(void *opaque, uint64_t addr) 414 { 415 hwaddr *base_addr = (hwaddr *)opaque; 416 return addr + *base_addr - PROM_VADDR; 417 } 418 419 /* Boot PROM (OpenBIOS) */ 420 static void prom_init(hwaddr addr, const char *bios_name) 421 { 422 DeviceState *dev; 423 SysBusDevice *s; 424 char *filename; 425 int ret; 426 427 dev = qdev_create(NULL, TYPE_OPENPROM); 428 qdev_init_nofail(dev); 429 s = SYS_BUS_DEVICE(dev); 430 431 sysbus_mmio_map(s, 0, addr); 432 433 /* load boot prom */ 434 if (bios_name == NULL) { 435 bios_name = PROM_FILENAME; 436 } 437 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 438 if (filename) { 439 ret = load_elf(filename, NULL, translate_prom_address, &addr, 440 NULL, NULL, NULL, 1, EM_SPARCV9, 0, 0); 441 if (ret < 0 || ret > PROM_SIZE_MAX) { 442 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX); 443 } 444 g_free(filename); 445 } else { 446 ret = -1; 447 } 448 if (ret < 0 || ret > PROM_SIZE_MAX) { 449 error_report("could not load prom '%s'", bios_name); 450 exit(1); 451 } 452 } 453 454 static void prom_realize(DeviceState *ds, Error **errp) 455 { 456 PROMState *s = OPENPROM(ds); 457 SysBusDevice *dev = SYS_BUS_DEVICE(ds); 458 Error *local_err = NULL; 459 460 memory_region_init_ram_nomigrate(&s->prom, OBJECT(ds), "sun4u.prom", 461 PROM_SIZE_MAX, &local_err); 462 if (local_err) { 463 error_propagate(errp, local_err); 464 return; 465 } 466 467 vmstate_register_ram_global(&s->prom); 468 memory_region_set_readonly(&s->prom, true); 469 sysbus_init_mmio(dev, &s->prom); 470 } 471 472 static Property prom_properties[] = { 473 {/* end of property list */}, 474 }; 475 476 static void prom_class_init(ObjectClass *klass, void *data) 477 { 478 DeviceClass *dc = DEVICE_CLASS(klass); 479 480 dc->props = prom_properties; 481 dc->realize = prom_realize; 482 } 483 484 static const TypeInfo prom_info = { 485 .name = TYPE_OPENPROM, 486 .parent = TYPE_SYS_BUS_DEVICE, 487 .instance_size = sizeof(PROMState), 488 .class_init = prom_class_init, 489 }; 490 491 492 #define TYPE_SUN4U_MEMORY "memory" 493 #define SUN4U_RAM(obj) OBJECT_CHECK(RamDevice, (obj), TYPE_SUN4U_MEMORY) 494 495 typedef struct RamDevice { 496 SysBusDevice parent_obj; 497 498 MemoryRegion ram; 499 uint64_t size; 500 } RamDevice; 501 502 /* System RAM */ 503 static void ram_realize(DeviceState *dev, Error **errp) 504 { 505 RamDevice *d = SUN4U_RAM(dev); 506 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 507 508 memory_region_init_ram_nomigrate(&d->ram, OBJECT(d), "sun4u.ram", d->size, 509 &error_fatal); 510 vmstate_register_ram_global(&d->ram); 511 sysbus_init_mmio(sbd, &d->ram); 512 } 513 514 static void ram_init(hwaddr addr, ram_addr_t RAM_size) 515 { 516 DeviceState *dev; 517 SysBusDevice *s; 518 RamDevice *d; 519 520 /* allocate RAM */ 521 dev = qdev_create(NULL, TYPE_SUN4U_MEMORY); 522 s = SYS_BUS_DEVICE(dev); 523 524 d = SUN4U_RAM(dev); 525 d->size = RAM_size; 526 qdev_init_nofail(dev); 527 528 sysbus_mmio_map(s, 0, addr); 529 } 530 531 static Property ram_properties[] = { 532 DEFINE_PROP_UINT64("size", RamDevice, size, 0), 533 DEFINE_PROP_END_OF_LIST(), 534 }; 535 536 static void ram_class_init(ObjectClass *klass, void *data) 537 { 538 DeviceClass *dc = DEVICE_CLASS(klass); 539 540 dc->realize = ram_realize; 541 dc->props = ram_properties; 542 } 543 544 static const TypeInfo ram_info = { 545 .name = TYPE_SUN4U_MEMORY, 546 .parent = TYPE_SYS_BUS_DEVICE, 547 .instance_size = sizeof(RamDevice), 548 .class_init = ram_class_init, 549 }; 550 551 static void sun4uv_init(MemoryRegion *address_space_mem, 552 MachineState *machine, 553 const struct hwdef *hwdef) 554 { 555 SPARCCPU *cpu; 556 Nvram *nvram; 557 unsigned int i; 558 uint64_t initrd_addr, initrd_size, kernel_addr, kernel_size, kernel_entry; 559 SabreState *sabre; 560 PCIBus *pci_bus, *pci_busA, *pci_busB; 561 PCIDevice *ebus, *pci_dev; 562 SysBusDevice *s; 563 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; 564 DeviceState *iommu, *dev; 565 FWCfgState *fw_cfg; 566 NICInfo *nd; 567 MACAddr macaddr; 568 bool onboard_nic; 569 570 /* init CPUs */ 571 cpu = sparc64_cpu_devinit(machine->cpu_type, hwdef->prom_addr); 572 573 /* IOMMU */ 574 iommu = qdev_create(NULL, TYPE_SUN4U_IOMMU); 575 qdev_init_nofail(iommu); 576 577 /* set up devices */ 578 ram_init(0, machine->ram_size); 579 580 prom_init(hwdef->prom_addr, bios_name); 581 582 /* Init sabre (PCI host bridge) */ 583 sabre = SABRE_DEVICE(qdev_create(NULL, TYPE_SABRE)); 584 qdev_prop_set_uint64(DEVICE(sabre), "special-base", PBM_SPECIAL_BASE); 585 qdev_prop_set_uint64(DEVICE(sabre), "mem-base", PBM_MEM_BASE); 586 object_property_set_link(OBJECT(sabre), OBJECT(iommu), "iommu", 587 &error_abort); 588 qdev_init_nofail(DEVICE(sabre)); 589 590 /* Wire up PCI interrupts to CPU */ 591 for (i = 0; i < IVEC_MAX; i++) { 592 qdev_connect_gpio_out_named(DEVICE(sabre), "ivec-irq", i, 593 qdev_get_gpio_in_named(DEVICE(cpu), "ivec-irq", i)); 594 } 595 596 pci_bus = PCI_HOST_BRIDGE(sabre)->bus; 597 pci_busA = pci_bridge_get_sec_bus(sabre->bridgeA); 598 pci_busB = pci_bridge_get_sec_bus(sabre->bridgeB); 599 600 /* Only in-built Simba APBs can exist on the root bus, slot 0 on busA is 601 reserved (leaving no slots free after on-board devices) however slots 602 0-3 are free on busB */ 603 pci_bus->slot_reserved_mask = 0xfffffffc; 604 pci_busA->slot_reserved_mask = 0xfffffff1; 605 pci_busB->slot_reserved_mask = 0xfffffff0; 606 607 ebus = pci_create_multifunction(pci_busA, PCI_DEVFN(1, 0), true, TYPE_EBUS); 608 qdev_prop_set_uint64(DEVICE(ebus), "console-serial-base", 609 hwdef->console_serial_base); 610 qdev_init_nofail(DEVICE(ebus)); 611 612 /* Wire up "well-known" ISA IRQs to PBM legacy obio IRQs */ 613 qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 7, 614 qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_LPT_IRQ)); 615 qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 6, 616 qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_FDD_IRQ)); 617 qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 1, 618 qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_KBD_IRQ)); 619 qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 12, 620 qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_MSE_IRQ)); 621 qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 4, 622 qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_SER_IRQ)); 623 624 switch (vga_interface_type) { 625 case VGA_STD: 626 pci_create_simple(pci_busA, PCI_DEVFN(2, 0), "VGA"); 627 break; 628 case VGA_NONE: 629 break; 630 default: 631 abort(); /* Should not happen - types are checked in vl.c already */ 632 } 633 634 memset(&macaddr, 0, sizeof(MACAddr)); 635 onboard_nic = false; 636 for (i = 0; i < nb_nics; i++) { 637 nd = &nd_table[i]; 638 639 if (!nd->model || strcmp(nd->model, "sunhme") == 0) { 640 if (!onboard_nic) { 641 pci_dev = pci_create_multifunction(pci_busA, PCI_DEVFN(1, 1), 642 true, "sunhme"); 643 memcpy(&macaddr, &nd->macaddr.a, sizeof(MACAddr)); 644 onboard_nic = true; 645 } else { 646 pci_dev = pci_create(pci_busB, -1, "sunhme"); 647 } 648 } else { 649 pci_dev = pci_create(pci_busB, -1, nd->model); 650 } 651 652 dev = &pci_dev->qdev; 653 qdev_set_nic_properties(dev, nd); 654 qdev_init_nofail(dev); 655 } 656 657 /* If we don't have an onboard NIC, grab a default MAC address so that 658 * we have a valid machine id */ 659 if (!onboard_nic) { 660 qemu_macaddr_default_if_unset(&macaddr); 661 } 662 663 ide_drive_get(hd, ARRAY_SIZE(hd)); 664 665 pci_dev = pci_create(pci_busA, PCI_DEVFN(3, 0), "cmd646-ide"); 666 qdev_prop_set_uint32(&pci_dev->qdev, "secondary", 1); 667 qdev_init_nofail(&pci_dev->qdev); 668 pci_ide_create_devs(pci_dev, hd); 669 670 /* Map NVRAM into I/O (ebus) space */ 671 nvram = m48t59_init(NULL, 0, 0, NVRAM_SIZE, 1968, 59); 672 s = SYS_BUS_DEVICE(nvram); 673 memory_region_add_subregion(pci_address_space_io(ebus), 0x2000, 674 sysbus_mmio_get_region(s, 0)); 675 676 initrd_size = 0; 677 initrd_addr = 0; 678 kernel_size = sun4u_load_kernel(machine->kernel_filename, 679 machine->initrd_filename, 680 ram_size, &initrd_size, &initrd_addr, 681 &kernel_addr, &kernel_entry); 682 683 sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", machine->ram_size, 684 machine->boot_order, 685 kernel_addr, kernel_size, 686 machine->kernel_cmdline, 687 initrd_addr, initrd_size, 688 /* XXX: need an option to load a NVRAM image */ 689 0, 690 graphic_width, graphic_height, graphic_depth, 691 (uint8_t *)&macaddr); 692 693 dev = qdev_create(NULL, TYPE_FW_CFG_IO); 694 qdev_prop_set_bit(dev, "dma_enabled", false); 695 object_property_add_child(OBJECT(ebus), TYPE_FW_CFG, OBJECT(dev), NULL); 696 qdev_init_nofail(dev); 697 memory_region_add_subregion(pci_address_space_io(ebus), BIOS_CFG_IOPORT, 698 &FW_CFG_IO(dev)->comb_iomem); 699 700 fw_cfg = FW_CFG(dev); 701 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)machine->smp.cpus); 702 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)machine->smp.max_cpus); 703 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 704 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); 705 fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_entry); 706 fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 707 if (machine->kernel_cmdline) { 708 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 709 strlen(machine->kernel_cmdline) + 1); 710 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline); 711 } else { 712 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0); 713 } 714 fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); 715 fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 716 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]); 717 718 fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_WIDTH, graphic_width); 719 fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_HEIGHT, graphic_height); 720 fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_DEPTH, graphic_depth); 721 722 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); 723 } 724 725 enum { 726 sun4u_id = 0, 727 sun4v_id = 64, 728 }; 729 730 /* 731 * Implementation of an interface to adjust firmware path 732 * for the bootindex property handling. 733 */ 734 static char *sun4u_fw_dev_path(FWPathProvider *p, BusState *bus, 735 DeviceState *dev) 736 { 737 PCIDevice *pci; 738 IDEBus *ide_bus; 739 IDEState *ide_s; 740 int bus_id; 741 742 if (!strcmp(object_get_typename(OBJECT(dev)), "pbm-bridge")) { 743 pci = PCI_DEVICE(dev); 744 745 if (PCI_FUNC(pci->devfn)) { 746 return g_strdup_printf("pci@%x,%x", PCI_SLOT(pci->devfn), 747 PCI_FUNC(pci->devfn)); 748 } else { 749 return g_strdup_printf("pci@%x", PCI_SLOT(pci->devfn)); 750 } 751 } 752 753 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-drive")) { 754 ide_bus = IDE_BUS(qdev_get_parent_bus(dev)); 755 ide_s = idebus_active_if(ide_bus); 756 bus_id = ide_bus->bus_id; 757 758 if (ide_s->drive_kind == IDE_CD) { 759 return g_strdup_printf("ide@%x/cdrom", bus_id); 760 } 761 762 return g_strdup_printf("ide@%x/disk", bus_id); 763 } 764 765 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-hd")) { 766 return g_strdup("disk"); 767 } 768 769 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-cd")) { 770 return g_strdup("cdrom"); 771 } 772 773 if (!strcmp(object_get_typename(OBJECT(dev)), "virtio-blk-device")) { 774 return g_strdup("disk"); 775 } 776 777 return NULL; 778 } 779 780 static const struct hwdef hwdefs[] = { 781 /* Sun4u generic PC-like machine */ 782 { 783 .machine_id = sun4u_id, 784 .prom_addr = 0x1fff0000000ULL, 785 .console_serial_base = 0, 786 }, 787 /* Sun4v generic PC-like machine */ 788 { 789 .machine_id = sun4v_id, 790 .prom_addr = 0x1fff0000000ULL, 791 .console_serial_base = 0, 792 }, 793 }; 794 795 /* Sun4u hardware initialisation */ 796 static void sun4u_init(MachineState *machine) 797 { 798 sun4uv_init(get_system_memory(), machine, &hwdefs[0]); 799 } 800 801 /* Sun4v hardware initialisation */ 802 static void sun4v_init(MachineState *machine) 803 { 804 sun4uv_init(get_system_memory(), machine, &hwdefs[1]); 805 } 806 807 static void sun4u_class_init(ObjectClass *oc, void *data) 808 { 809 MachineClass *mc = MACHINE_CLASS(oc); 810 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 811 812 mc->desc = "Sun4u platform"; 813 mc->init = sun4u_init; 814 mc->block_default_type = IF_IDE; 815 mc->max_cpus = 1; /* XXX for now */ 816 mc->is_default = 1; 817 mc->default_boot_order = "c"; 818 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-UltraSparc-IIi"); 819 mc->ignore_boot_device_suffixes = true; 820 mc->default_display = "std"; 821 fwc->get_dev_path = sun4u_fw_dev_path; 822 } 823 824 static const TypeInfo sun4u_type = { 825 .name = MACHINE_TYPE_NAME("sun4u"), 826 .parent = TYPE_MACHINE, 827 .class_init = sun4u_class_init, 828 .interfaces = (InterfaceInfo[]) { 829 { TYPE_FW_PATH_PROVIDER }, 830 { } 831 }, 832 }; 833 834 static void sun4v_class_init(ObjectClass *oc, void *data) 835 { 836 MachineClass *mc = MACHINE_CLASS(oc); 837 838 mc->desc = "Sun4v platform"; 839 mc->init = sun4v_init; 840 mc->block_default_type = IF_IDE; 841 mc->max_cpus = 1; /* XXX for now */ 842 mc->default_boot_order = "c"; 843 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Sun-UltraSparc-T1"); 844 mc->default_display = "std"; 845 } 846 847 static const TypeInfo sun4v_type = { 848 .name = MACHINE_TYPE_NAME("sun4v"), 849 .parent = TYPE_MACHINE, 850 .class_init = sun4v_class_init, 851 }; 852 853 static void sun4u_register_types(void) 854 { 855 type_register_static(&power_info); 856 type_register_static(&ebus_info); 857 type_register_static(&prom_info); 858 type_register_static(&ram_info); 859 860 type_register_static(&sun4u_type); 861 type_register_static(&sun4v_type); 862 } 863 864 type_init(sun4u_register_types) 865