xref: /openbmc/qemu/hw/sparc64/sun4u.c (revision 64552b6b)
1 /*
2  * QEMU Sun4u/Sun4v System Emulator
3  *
4  * Copyright (c) 2005 Fabrice Bellard
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a copy
7  * of this software and associated documentation files (the "Software"), to deal
8  * in the Software without restriction, including without limitation the rights
9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10  * copies of the Software, and to permit persons to whom the Software is
11  * furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22  * THE SOFTWARE.
23  */
24 #include "qemu/osdep.h"
25 #include "qemu/units.h"
26 #include "qemu/error-report.h"
27 #include "qapi/error.h"
28 #include "qemu-common.h"
29 #include "cpu.h"
30 #include "hw/hw.h"
31 #include "hw/pci/pci.h"
32 #include "hw/pci/pci_bridge.h"
33 #include "hw/pci/pci_bus.h"
34 #include "hw/pci/pci_host.h"
35 #include "hw/pci-host/sabre.h"
36 #include "hw/char/serial.h"
37 #include "hw/char/parallel.h"
38 #include "hw/timer/m48t59.h"
39 #include "hw/input/i8042.h"
40 #include "hw/block/fdc.h"
41 #include "net/net.h"
42 #include "qemu/timer.h"
43 #include "sysemu/sysemu.h"
44 #include "hw/boards.h"
45 #include "hw/nvram/sun_nvram.h"
46 #include "hw/nvram/chrp_nvram.h"
47 #include "hw/sparc/sparc64.h"
48 #include "hw/nvram/fw_cfg.h"
49 #include "hw/sysbus.h"
50 #include "hw/ide.h"
51 #include "hw/ide/pci.h"
52 #include "hw/loader.h"
53 #include "hw/fw-path-provider.h"
54 #include "elf.h"
55 #include "trace.h"
56 
57 #define KERNEL_LOAD_ADDR     0x00404000
58 #define CMDLINE_ADDR         0x003ff000
59 #define PROM_SIZE_MAX        (4 * MiB)
60 #define PROM_VADDR           0x000ffd00000ULL
61 #define PBM_SPECIAL_BASE     0x1fe00000000ULL
62 #define PBM_MEM_BASE         0x1ff00000000ULL
63 #define PBM_PCI_IO_BASE      (PBM_SPECIAL_BASE + 0x02000000ULL)
64 #define PROM_FILENAME        "openbios-sparc64"
65 #define NVRAM_SIZE           0x2000
66 #define MAX_IDE_BUS          2
67 #define BIOS_CFG_IOPORT      0x510
68 #define FW_CFG_SPARC64_WIDTH (FW_CFG_ARCH_LOCAL + 0x00)
69 #define FW_CFG_SPARC64_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01)
70 #define FW_CFG_SPARC64_DEPTH (FW_CFG_ARCH_LOCAL + 0x02)
71 
72 #define IVEC_MAX             0x40
73 
74 struct hwdef {
75     uint16_t machine_id;
76     uint64_t prom_addr;
77     uint64_t console_serial_base;
78 };
79 
80 typedef struct EbusState {
81     /*< private >*/
82     PCIDevice parent_obj;
83 
84     ISABus *isa_bus;
85     qemu_irq isa_bus_irqs[ISA_NUM_IRQS];
86     uint64_t console_serial_base;
87     MemoryRegion bar0;
88     MemoryRegion bar1;
89 } EbusState;
90 
91 #define TYPE_EBUS "ebus"
92 #define EBUS(obj) OBJECT_CHECK(EbusState, (obj), TYPE_EBUS)
93 
94 const char *fw_cfg_arch_key_name(uint16_t key)
95 {
96     static const struct {
97         uint16_t key;
98         const char *name;
99     } fw_cfg_arch_wellknown_keys[] = {
100         {FW_CFG_SPARC64_WIDTH, "width"},
101         {FW_CFG_SPARC64_HEIGHT, "height"},
102         {FW_CFG_SPARC64_DEPTH, "depth"},
103     };
104 
105     for (size_t i = 0; i < ARRAY_SIZE(fw_cfg_arch_wellknown_keys); i++) {
106         if (fw_cfg_arch_wellknown_keys[i].key == key) {
107             return fw_cfg_arch_wellknown_keys[i].name;
108         }
109     }
110     return NULL;
111 }
112 
113 static void fw_cfg_boot_set(void *opaque, const char *boot_device,
114                             Error **errp)
115 {
116     fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
117 }
118 
119 static int sun4u_NVRAM_set_params(Nvram *nvram, uint16_t NVRAM_size,
120                                   const char *arch, ram_addr_t RAM_size,
121                                   const char *boot_devices,
122                                   uint32_t kernel_image, uint32_t kernel_size,
123                                   const char *cmdline,
124                                   uint32_t initrd_image, uint32_t initrd_size,
125                                   uint32_t NVRAM_image,
126                                   int width, int height, int depth,
127                                   const uint8_t *macaddr)
128 {
129     unsigned int i;
130     int sysp_end;
131     uint8_t image[0x1ff0];
132     NvramClass *k = NVRAM_GET_CLASS(nvram);
133 
134     memset(image, '\0', sizeof(image));
135 
136     /* OpenBIOS nvram variables partition */
137     sysp_end = chrp_nvram_create_system_partition(image, 0);
138 
139     /* Free space partition */
140     chrp_nvram_create_free_partition(&image[sysp_end], 0x1fd0 - sysp_end);
141 
142     Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80);
143 
144     for (i = 0; i < sizeof(image); i++) {
145         (k->write)(nvram, i, image[i]);
146     }
147 
148     return 0;
149 }
150 
151 static uint64_t sun4u_load_kernel(const char *kernel_filename,
152                                   const char *initrd_filename,
153                                   ram_addr_t RAM_size, uint64_t *initrd_size,
154                                   uint64_t *initrd_addr, uint64_t *kernel_addr,
155                                   uint64_t *kernel_entry)
156 {
157     int linux_boot;
158     unsigned int i;
159     long kernel_size;
160     uint8_t *ptr;
161     uint64_t kernel_top = 0;
162 
163     linux_boot = (kernel_filename != NULL);
164 
165     kernel_size = 0;
166     if (linux_boot) {
167         int bswap_needed;
168 
169 #ifdef BSWAP_NEEDED
170         bswap_needed = 1;
171 #else
172         bswap_needed = 0;
173 #endif
174         kernel_size = load_elf(kernel_filename, NULL, NULL, NULL, kernel_entry,
175                                kernel_addr, &kernel_top, 1, EM_SPARCV9, 0, 0);
176         if (kernel_size < 0) {
177             *kernel_addr = KERNEL_LOAD_ADDR;
178             *kernel_entry = KERNEL_LOAD_ADDR;
179             kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
180                                     RAM_size - KERNEL_LOAD_ADDR, bswap_needed,
181                                     TARGET_PAGE_SIZE);
182         }
183         if (kernel_size < 0) {
184             kernel_size = load_image_targphys(kernel_filename,
185                                               KERNEL_LOAD_ADDR,
186                                               RAM_size - KERNEL_LOAD_ADDR);
187         }
188         if (kernel_size < 0) {
189             error_report("could not load kernel '%s'", kernel_filename);
190             exit(1);
191         }
192         /* load initrd above kernel */
193         *initrd_size = 0;
194         if (initrd_filename && kernel_top) {
195             *initrd_addr = TARGET_PAGE_ALIGN(kernel_top);
196 
197             *initrd_size = load_image_targphys(initrd_filename,
198                                                *initrd_addr,
199                                                RAM_size - *initrd_addr);
200             if ((int)*initrd_size < 0) {
201                 error_report("could not load initial ram disk '%s'",
202                              initrd_filename);
203                 exit(1);
204             }
205         }
206         if (*initrd_size > 0) {
207             for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
208                 ptr = rom_ptr(*kernel_addr + i, 32);
209                 if (ptr && ldl_p(ptr + 8) == 0x48647253) { /* HdrS */
210                     stl_p(ptr + 24, *initrd_addr + *kernel_addr);
211                     stl_p(ptr + 28, *initrd_size);
212                     break;
213                 }
214             }
215         }
216     }
217     return kernel_size;
218 }
219 
220 typedef struct ResetData {
221     SPARCCPU *cpu;
222     uint64_t prom_addr;
223 } ResetData;
224 
225 #define TYPE_SUN4U_POWER "power"
226 #define SUN4U_POWER(obj) OBJECT_CHECK(PowerDevice, (obj), TYPE_SUN4U_POWER)
227 
228 typedef struct PowerDevice {
229     SysBusDevice parent_obj;
230 
231     MemoryRegion power_mmio;
232 } PowerDevice;
233 
234 /* Power */
235 static uint64_t power_mem_read(void *opaque, hwaddr addr, unsigned size)
236 {
237     return 0;
238 }
239 
240 static void power_mem_write(void *opaque, hwaddr addr,
241                             uint64_t val, unsigned size)
242 {
243     /* According to a real Ultra 5, bit 24 controls the power */
244     if (val & 0x1000000) {
245         qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
246     }
247 }
248 
249 static const MemoryRegionOps power_mem_ops = {
250     .read = power_mem_read,
251     .write = power_mem_write,
252     .endianness = DEVICE_NATIVE_ENDIAN,
253     .valid = {
254         .min_access_size = 4,
255         .max_access_size = 4,
256     },
257 };
258 
259 static void power_realize(DeviceState *dev, Error **errp)
260 {
261     PowerDevice *d = SUN4U_POWER(dev);
262     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
263 
264     memory_region_init_io(&d->power_mmio, OBJECT(dev), &power_mem_ops, d,
265                           "power", sizeof(uint32_t));
266 
267     sysbus_init_mmio(sbd, &d->power_mmio);
268 }
269 
270 static void power_class_init(ObjectClass *klass, void *data)
271 {
272     DeviceClass *dc = DEVICE_CLASS(klass);
273 
274     dc->realize = power_realize;
275 }
276 
277 static const TypeInfo power_info = {
278     .name          = TYPE_SUN4U_POWER,
279     .parent        = TYPE_SYS_BUS_DEVICE,
280     .instance_size = sizeof(PowerDevice),
281     .class_init    = power_class_init,
282 };
283 
284 static void ebus_isa_irq_handler(void *opaque, int n, int level)
285 {
286     EbusState *s = EBUS(opaque);
287     qemu_irq irq = s->isa_bus_irqs[n];
288 
289     /* Pass ISA bus IRQs onto their gpio equivalent */
290     trace_ebus_isa_irq_handler(n, level);
291     if (irq) {
292         qemu_set_irq(irq, level);
293     }
294 }
295 
296 /* EBUS (Eight bit bus) bridge */
297 static void ebus_realize(PCIDevice *pci_dev, Error **errp)
298 {
299     EbusState *s = EBUS(pci_dev);
300     SysBusDevice *sbd;
301     DeviceState *dev;
302     qemu_irq *isa_irq;
303     DriveInfo *fd[MAX_FD];
304     int i;
305 
306     s->isa_bus = isa_bus_new(DEVICE(pci_dev), get_system_memory(),
307                              pci_address_space_io(pci_dev), errp);
308     if (!s->isa_bus) {
309         error_setg(errp, "unable to instantiate EBUS ISA bus");
310         return;
311     }
312 
313     /* ISA bus */
314     isa_irq = qemu_allocate_irqs(ebus_isa_irq_handler, s, ISA_NUM_IRQS);
315     isa_bus_irqs(s->isa_bus, isa_irq);
316     qdev_init_gpio_out_named(DEVICE(s), s->isa_bus_irqs, "isa-irq",
317                              ISA_NUM_IRQS);
318 
319     /* Serial ports */
320     i = 0;
321     if (s->console_serial_base) {
322         serial_mm_init(pci_address_space(pci_dev), s->console_serial_base,
323                        0, NULL, 115200, serial_hd(i), DEVICE_BIG_ENDIAN);
324         i++;
325     }
326     serial_hds_isa_init(s->isa_bus, i, MAX_ISA_SERIAL_PORTS);
327 
328     /* Parallel ports */
329     parallel_hds_isa_init(s->isa_bus, MAX_PARALLEL_PORTS);
330 
331     /* Keyboard */
332     isa_create_simple(s->isa_bus, "i8042");
333 
334     /* Floppy */
335     for (i = 0; i < MAX_FD; i++) {
336         fd[i] = drive_get(IF_FLOPPY, 0, i);
337     }
338     dev = DEVICE(isa_create(s->isa_bus, TYPE_ISA_FDC));
339     if (fd[0]) {
340         qdev_prop_set_drive(dev, "driveA", blk_by_legacy_dinfo(fd[0]),
341                             &error_abort);
342     }
343     if (fd[1]) {
344         qdev_prop_set_drive(dev, "driveB", blk_by_legacy_dinfo(fd[1]),
345                             &error_abort);
346     }
347     qdev_prop_set_uint32(dev, "dma", -1);
348     qdev_init_nofail(dev);
349 
350     /* Power */
351     dev = qdev_create(NULL, TYPE_SUN4U_POWER);
352     qdev_init_nofail(dev);
353     sbd = SYS_BUS_DEVICE(dev);
354     memory_region_add_subregion(pci_address_space_io(pci_dev), 0x7240,
355                                 sysbus_mmio_get_region(sbd, 0));
356 
357     /* PCI */
358     pci_dev->config[0x04] = 0x06; // command = bus master, pci mem
359     pci_dev->config[0x05] = 0x00;
360     pci_dev->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
361     pci_dev->config[0x07] = 0x03; // status = medium devsel
362     pci_dev->config[0x09] = 0x00; // programming i/f
363     pci_dev->config[0x0D] = 0x0a; // latency_timer
364 
365     memory_region_init_alias(&s->bar0, OBJECT(s), "bar0", get_system_io(),
366                              0, 0x1000000);
367     pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0);
368     memory_region_init_alias(&s->bar1, OBJECT(s), "bar1", get_system_io(),
369                              0, 0x8000);
370     pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->bar1);
371 }
372 
373 static Property ebus_properties[] = {
374     DEFINE_PROP_UINT64("console-serial-base", EbusState,
375                        console_serial_base, 0),
376     DEFINE_PROP_END_OF_LIST(),
377 };
378 
379 static void ebus_class_init(ObjectClass *klass, void *data)
380 {
381     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
382     DeviceClass *dc = DEVICE_CLASS(klass);
383 
384     k->realize = ebus_realize;
385     k->vendor_id = PCI_VENDOR_ID_SUN;
386     k->device_id = PCI_DEVICE_ID_SUN_EBUS;
387     k->revision = 0x01;
388     k->class_id = PCI_CLASS_BRIDGE_OTHER;
389     dc->props = ebus_properties;
390 }
391 
392 static const TypeInfo ebus_info = {
393     .name          = TYPE_EBUS,
394     .parent        = TYPE_PCI_DEVICE,
395     .class_init    = ebus_class_init,
396     .instance_size = sizeof(EbusState),
397     .interfaces = (InterfaceInfo[]) {
398         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
399         { },
400     },
401 };
402 
403 #define TYPE_OPENPROM "openprom"
404 #define OPENPROM(obj) OBJECT_CHECK(PROMState, (obj), TYPE_OPENPROM)
405 
406 typedef struct PROMState {
407     SysBusDevice parent_obj;
408 
409     MemoryRegion prom;
410 } PROMState;
411 
412 static uint64_t translate_prom_address(void *opaque, uint64_t addr)
413 {
414     hwaddr *base_addr = (hwaddr *)opaque;
415     return addr + *base_addr - PROM_VADDR;
416 }
417 
418 /* Boot PROM (OpenBIOS) */
419 static void prom_init(hwaddr addr, const char *bios_name)
420 {
421     DeviceState *dev;
422     SysBusDevice *s;
423     char *filename;
424     int ret;
425 
426     dev = qdev_create(NULL, TYPE_OPENPROM);
427     qdev_init_nofail(dev);
428     s = SYS_BUS_DEVICE(dev);
429 
430     sysbus_mmio_map(s, 0, addr);
431 
432     /* load boot prom */
433     if (bios_name == NULL) {
434         bios_name = PROM_FILENAME;
435     }
436     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
437     if (filename) {
438         ret = load_elf(filename, NULL, translate_prom_address, &addr,
439                        NULL, NULL, NULL, 1, EM_SPARCV9, 0, 0);
440         if (ret < 0 || ret > PROM_SIZE_MAX) {
441             ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
442         }
443         g_free(filename);
444     } else {
445         ret = -1;
446     }
447     if (ret < 0 || ret > PROM_SIZE_MAX) {
448         error_report("could not load prom '%s'", bios_name);
449         exit(1);
450     }
451 }
452 
453 static void prom_realize(DeviceState *ds, Error **errp)
454 {
455     PROMState *s = OPENPROM(ds);
456     SysBusDevice *dev = SYS_BUS_DEVICE(ds);
457     Error *local_err = NULL;
458 
459     memory_region_init_ram_nomigrate(&s->prom, OBJECT(ds), "sun4u.prom",
460                                      PROM_SIZE_MAX, &local_err);
461     if (local_err) {
462         error_propagate(errp, local_err);
463         return;
464     }
465 
466     vmstate_register_ram_global(&s->prom);
467     memory_region_set_readonly(&s->prom, true);
468     sysbus_init_mmio(dev, &s->prom);
469 }
470 
471 static Property prom_properties[] = {
472     {/* end of property list */},
473 };
474 
475 static void prom_class_init(ObjectClass *klass, void *data)
476 {
477     DeviceClass *dc = DEVICE_CLASS(klass);
478 
479     dc->props = prom_properties;
480     dc->realize = prom_realize;
481 }
482 
483 static const TypeInfo prom_info = {
484     .name          = TYPE_OPENPROM,
485     .parent        = TYPE_SYS_BUS_DEVICE,
486     .instance_size = sizeof(PROMState),
487     .class_init    = prom_class_init,
488 };
489 
490 
491 #define TYPE_SUN4U_MEMORY "memory"
492 #define SUN4U_RAM(obj) OBJECT_CHECK(RamDevice, (obj), TYPE_SUN4U_MEMORY)
493 
494 typedef struct RamDevice {
495     SysBusDevice parent_obj;
496 
497     MemoryRegion ram;
498     uint64_t size;
499 } RamDevice;
500 
501 /* System RAM */
502 static void ram_realize(DeviceState *dev, Error **errp)
503 {
504     RamDevice *d = SUN4U_RAM(dev);
505     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
506 
507     memory_region_init_ram_nomigrate(&d->ram, OBJECT(d), "sun4u.ram", d->size,
508                            &error_fatal);
509     vmstate_register_ram_global(&d->ram);
510     sysbus_init_mmio(sbd, &d->ram);
511 }
512 
513 static void ram_init(hwaddr addr, ram_addr_t RAM_size)
514 {
515     DeviceState *dev;
516     SysBusDevice *s;
517     RamDevice *d;
518 
519     /* allocate RAM */
520     dev = qdev_create(NULL, TYPE_SUN4U_MEMORY);
521     s = SYS_BUS_DEVICE(dev);
522 
523     d = SUN4U_RAM(dev);
524     d->size = RAM_size;
525     qdev_init_nofail(dev);
526 
527     sysbus_mmio_map(s, 0, addr);
528 }
529 
530 static Property ram_properties[] = {
531     DEFINE_PROP_UINT64("size", RamDevice, size, 0),
532     DEFINE_PROP_END_OF_LIST(),
533 };
534 
535 static void ram_class_init(ObjectClass *klass, void *data)
536 {
537     DeviceClass *dc = DEVICE_CLASS(klass);
538 
539     dc->realize = ram_realize;
540     dc->props = ram_properties;
541 }
542 
543 static const TypeInfo ram_info = {
544     .name          = TYPE_SUN4U_MEMORY,
545     .parent        = TYPE_SYS_BUS_DEVICE,
546     .instance_size = sizeof(RamDevice),
547     .class_init    = ram_class_init,
548 };
549 
550 static void sun4uv_init(MemoryRegion *address_space_mem,
551                         MachineState *machine,
552                         const struct hwdef *hwdef)
553 {
554     SPARCCPU *cpu;
555     Nvram *nvram;
556     unsigned int i;
557     uint64_t initrd_addr, initrd_size, kernel_addr, kernel_size, kernel_entry;
558     SabreState *sabre;
559     PCIBus *pci_bus, *pci_busA, *pci_busB;
560     PCIDevice *ebus, *pci_dev;
561     SysBusDevice *s;
562     DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
563     DeviceState *iommu, *dev;
564     FWCfgState *fw_cfg;
565     NICInfo *nd;
566     MACAddr macaddr;
567     bool onboard_nic;
568 
569     /* init CPUs */
570     cpu = sparc64_cpu_devinit(machine->cpu_type, hwdef->prom_addr);
571 
572     /* IOMMU */
573     iommu = qdev_create(NULL, TYPE_SUN4U_IOMMU);
574     qdev_init_nofail(iommu);
575 
576     /* set up devices */
577     ram_init(0, machine->ram_size);
578 
579     prom_init(hwdef->prom_addr, bios_name);
580 
581     /* Init sabre (PCI host bridge) */
582     sabre = SABRE_DEVICE(qdev_create(NULL, TYPE_SABRE));
583     qdev_prop_set_uint64(DEVICE(sabre), "special-base", PBM_SPECIAL_BASE);
584     qdev_prop_set_uint64(DEVICE(sabre), "mem-base", PBM_MEM_BASE);
585     object_property_set_link(OBJECT(sabre), OBJECT(iommu), "iommu",
586                              &error_abort);
587     qdev_init_nofail(DEVICE(sabre));
588 
589     /* Wire up PCI interrupts to CPU */
590     for (i = 0; i < IVEC_MAX; i++) {
591         qdev_connect_gpio_out_named(DEVICE(sabre), "ivec-irq", i,
592             qdev_get_gpio_in_named(DEVICE(cpu), "ivec-irq", i));
593     }
594 
595     pci_bus = PCI_HOST_BRIDGE(sabre)->bus;
596     pci_busA = pci_bridge_get_sec_bus(sabre->bridgeA);
597     pci_busB = pci_bridge_get_sec_bus(sabre->bridgeB);
598 
599     /* Only in-built Simba APBs can exist on the root bus, slot 0 on busA is
600        reserved (leaving no slots free after on-board devices) however slots
601        0-3 are free on busB */
602     pci_bus->slot_reserved_mask = 0xfffffffc;
603     pci_busA->slot_reserved_mask = 0xfffffff1;
604     pci_busB->slot_reserved_mask = 0xfffffff0;
605 
606     ebus = pci_create_multifunction(pci_busA, PCI_DEVFN(1, 0), true, TYPE_EBUS);
607     qdev_prop_set_uint64(DEVICE(ebus), "console-serial-base",
608                          hwdef->console_serial_base);
609     qdev_init_nofail(DEVICE(ebus));
610 
611     /* Wire up "well-known" ISA IRQs to PBM legacy obio IRQs */
612     qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 7,
613         qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_LPT_IRQ));
614     qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 6,
615         qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_FDD_IRQ));
616     qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 1,
617         qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_KBD_IRQ));
618     qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 12,
619         qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_MSE_IRQ));
620     qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 4,
621         qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_SER_IRQ));
622 
623     switch (vga_interface_type) {
624     case VGA_STD:
625         pci_create_simple(pci_busA, PCI_DEVFN(2, 0), "VGA");
626         break;
627     case VGA_NONE:
628         break;
629     default:
630         abort();   /* Should not happen - types are checked in vl.c already */
631     }
632 
633     memset(&macaddr, 0, sizeof(MACAddr));
634     onboard_nic = false;
635     for (i = 0; i < nb_nics; i++) {
636         nd = &nd_table[i];
637 
638         if (!nd->model || strcmp(nd->model, "sunhme") == 0) {
639             if (!onboard_nic) {
640                 pci_dev = pci_create_multifunction(pci_busA, PCI_DEVFN(1, 1),
641                                                    true, "sunhme");
642                 memcpy(&macaddr, &nd->macaddr.a, sizeof(MACAddr));
643                 onboard_nic = true;
644             } else {
645                 pci_dev = pci_create(pci_busB, -1, "sunhme");
646             }
647         } else {
648             pci_dev = pci_create(pci_busB, -1, nd->model);
649         }
650 
651         dev = &pci_dev->qdev;
652         qdev_set_nic_properties(dev, nd);
653         qdev_init_nofail(dev);
654     }
655 
656     /* If we don't have an onboard NIC, grab a default MAC address so that
657      * we have a valid machine id */
658     if (!onboard_nic) {
659         qemu_macaddr_default_if_unset(&macaddr);
660     }
661 
662     ide_drive_get(hd, ARRAY_SIZE(hd));
663 
664     pci_dev = pci_create(pci_busA, PCI_DEVFN(3, 0), "cmd646-ide");
665     qdev_prop_set_uint32(&pci_dev->qdev, "secondary", 1);
666     qdev_init_nofail(&pci_dev->qdev);
667     pci_ide_create_devs(pci_dev, hd);
668 
669     /* Map NVRAM into I/O (ebus) space */
670     nvram = m48t59_init(NULL, 0, 0, NVRAM_SIZE, 1968, 59);
671     s = SYS_BUS_DEVICE(nvram);
672     memory_region_add_subregion(pci_address_space_io(ebus), 0x2000,
673                                 sysbus_mmio_get_region(s, 0));
674 
675     initrd_size = 0;
676     initrd_addr = 0;
677     kernel_size = sun4u_load_kernel(machine->kernel_filename,
678                                     machine->initrd_filename,
679                                     ram_size, &initrd_size, &initrd_addr,
680                                     &kernel_addr, &kernel_entry);
681 
682     sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", machine->ram_size,
683                            machine->boot_order,
684                            kernel_addr, kernel_size,
685                            machine->kernel_cmdline,
686                            initrd_addr, initrd_size,
687                            /* XXX: need an option to load a NVRAM image */
688                            0,
689                            graphic_width, graphic_height, graphic_depth,
690                            (uint8_t *)&macaddr);
691 
692     dev = qdev_create(NULL, TYPE_FW_CFG_IO);
693     qdev_prop_set_bit(dev, "dma_enabled", false);
694     object_property_add_child(OBJECT(ebus), TYPE_FW_CFG, OBJECT(dev), NULL);
695     qdev_init_nofail(dev);
696     memory_region_add_subregion(pci_address_space_io(ebus), BIOS_CFG_IOPORT,
697                                 &FW_CFG_IO(dev)->comb_iomem);
698 
699     fw_cfg = FW_CFG(dev);
700     fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)machine->smp.cpus);
701     fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)machine->smp.max_cpus);
702     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
703     fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
704     fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_entry);
705     fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
706     if (machine->kernel_cmdline) {
707         fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
708                        strlen(machine->kernel_cmdline) + 1);
709         fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline);
710     } else {
711         fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
712     }
713     fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
714     fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
715     fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]);
716 
717     fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_WIDTH, graphic_width);
718     fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_HEIGHT, graphic_height);
719     fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_DEPTH, graphic_depth);
720 
721     qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
722 }
723 
724 enum {
725     sun4u_id = 0,
726     sun4v_id = 64,
727 };
728 
729 /*
730  * Implementation of an interface to adjust firmware path
731  * for the bootindex property handling.
732  */
733 static char *sun4u_fw_dev_path(FWPathProvider *p, BusState *bus,
734                                DeviceState *dev)
735 {
736     PCIDevice *pci;
737     IDEBus *ide_bus;
738     IDEState *ide_s;
739     int bus_id;
740 
741     if (!strcmp(object_get_typename(OBJECT(dev)), "pbm-bridge")) {
742         pci = PCI_DEVICE(dev);
743 
744         if (PCI_FUNC(pci->devfn)) {
745             return g_strdup_printf("pci@%x,%x", PCI_SLOT(pci->devfn),
746                                    PCI_FUNC(pci->devfn));
747         } else {
748             return g_strdup_printf("pci@%x", PCI_SLOT(pci->devfn));
749         }
750     }
751 
752     if (!strcmp(object_get_typename(OBJECT(dev)), "ide-drive")) {
753          ide_bus = IDE_BUS(qdev_get_parent_bus(dev));
754          ide_s = idebus_active_if(ide_bus);
755          bus_id = ide_bus->bus_id;
756 
757          if (ide_s->drive_kind == IDE_CD) {
758              return g_strdup_printf("ide@%x/cdrom", bus_id);
759          }
760 
761          return g_strdup_printf("ide@%x/disk", bus_id);
762     }
763 
764     if (!strcmp(object_get_typename(OBJECT(dev)), "ide-hd")) {
765         return g_strdup("disk");
766     }
767 
768     if (!strcmp(object_get_typename(OBJECT(dev)), "ide-cd")) {
769         return g_strdup("cdrom");
770     }
771 
772     if (!strcmp(object_get_typename(OBJECT(dev)), "virtio-blk-device")) {
773         return g_strdup("disk");
774     }
775 
776     return NULL;
777 }
778 
779 static const struct hwdef hwdefs[] = {
780     /* Sun4u generic PC-like machine */
781     {
782         .machine_id = sun4u_id,
783         .prom_addr = 0x1fff0000000ULL,
784         .console_serial_base = 0,
785     },
786     /* Sun4v generic PC-like machine */
787     {
788         .machine_id = sun4v_id,
789         .prom_addr = 0x1fff0000000ULL,
790         .console_serial_base = 0,
791     },
792 };
793 
794 /* Sun4u hardware initialisation */
795 static void sun4u_init(MachineState *machine)
796 {
797     sun4uv_init(get_system_memory(), machine, &hwdefs[0]);
798 }
799 
800 /* Sun4v hardware initialisation */
801 static void sun4v_init(MachineState *machine)
802 {
803     sun4uv_init(get_system_memory(), machine, &hwdefs[1]);
804 }
805 
806 static void sun4u_class_init(ObjectClass *oc, void *data)
807 {
808     MachineClass *mc = MACHINE_CLASS(oc);
809     FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc);
810 
811     mc->desc = "Sun4u platform";
812     mc->init = sun4u_init;
813     mc->block_default_type = IF_IDE;
814     mc->max_cpus = 1; /* XXX for now */
815     mc->is_default = 1;
816     mc->default_boot_order = "c";
817     mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-UltraSparc-IIi");
818     mc->ignore_boot_device_suffixes = true;
819     mc->default_display = "std";
820     fwc->get_dev_path = sun4u_fw_dev_path;
821 }
822 
823 static const TypeInfo sun4u_type = {
824     .name = MACHINE_TYPE_NAME("sun4u"),
825     .parent = TYPE_MACHINE,
826     .class_init = sun4u_class_init,
827     .interfaces = (InterfaceInfo[]) {
828         { TYPE_FW_PATH_PROVIDER },
829         { }
830     },
831 };
832 
833 static void sun4v_class_init(ObjectClass *oc, void *data)
834 {
835     MachineClass *mc = MACHINE_CLASS(oc);
836 
837     mc->desc = "Sun4v platform";
838     mc->init = sun4v_init;
839     mc->block_default_type = IF_IDE;
840     mc->max_cpus = 1; /* XXX for now */
841     mc->default_boot_order = "c";
842     mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Sun-UltraSparc-T1");
843     mc->default_display = "std";
844 }
845 
846 static const TypeInfo sun4v_type = {
847     .name = MACHINE_TYPE_NAME("sun4v"),
848     .parent = TYPE_MACHINE,
849     .class_init = sun4v_class_init,
850 };
851 
852 static void sun4u_register_types(void)
853 {
854     type_register_static(&power_info);
855     type_register_static(&ebus_info);
856     type_register_static(&prom_info);
857     type_register_static(&ram_info);
858 
859     type_register_static(&sun4u_type);
860     type_register_static(&sun4v_type);
861 }
862 
863 type_init(sun4u_register_types)
864