1 /* 2 * QEMU Sun4u/Sun4v System Emulator 3 * 4 * Copyright (c) 2005 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "qemu/error-report.h" 28 #include "qapi/error.h" 29 #include "qemu/datadir.h" 30 #include "cpu.h" 31 #include "hw/irq.h" 32 #include "hw/pci/pci.h" 33 #include "hw/pci/pci_bridge.h" 34 #include "hw/pci/pci_host.h" 35 #include "hw/qdev-properties.h" 36 #include "hw/pci-host/sabre.h" 37 #include "hw/char/serial-isa.h" 38 #include "hw/char/serial-mm.h" 39 #include "hw/char/parallel-isa.h" 40 #include "hw/rtc/m48t59.h" 41 #include "migration/vmstate.h" 42 #include "hw/input/i8042.h" 43 #include "hw/block/fdc.h" 44 #include "net/net.h" 45 #include "qemu/timer.h" 46 #include "sysemu/runstate.h" 47 #include "sysemu/sysemu.h" 48 #include "hw/boards.h" 49 #include "hw/nvram/sun_nvram.h" 50 #include "hw/nvram/chrp_nvram.h" 51 #include "hw/sparc/sparc64.h" 52 #include "hw/nvram/fw_cfg.h" 53 #include "hw/sysbus.h" 54 #include "hw/ide/pci.h" 55 #include "hw/loader.h" 56 #include "hw/fw-path-provider.h" 57 #include "elf.h" 58 #include "trace.h" 59 #include "qom/object.h" 60 61 #define KERNEL_LOAD_ADDR 0x00404000 62 #define CMDLINE_ADDR 0x003ff000 63 #define PROM_SIZE_MAX (4 * MiB) 64 #define PROM_VADDR 0x000ffd00000ULL 65 #define PBM_SPECIAL_BASE 0x1fe00000000ULL 66 #define PBM_MEM_BASE 0x1ff00000000ULL 67 #define PBM_PCI_IO_BASE (PBM_SPECIAL_BASE + 0x02000000ULL) 68 #define PROM_FILENAME "openbios-sparc64" 69 #define NVRAM_SIZE 0x2000 70 #define BIOS_CFG_IOPORT 0x510 71 #define FW_CFG_SPARC64_WIDTH (FW_CFG_ARCH_LOCAL + 0x00) 72 #define FW_CFG_SPARC64_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01) 73 #define FW_CFG_SPARC64_DEPTH (FW_CFG_ARCH_LOCAL + 0x02) 74 75 #define IVEC_MAX 0x40 76 77 struct hwdef { 78 uint16_t machine_id; 79 uint64_t prom_addr; 80 uint64_t console_serial_base; 81 }; 82 83 struct EbusState { 84 /*< private >*/ 85 PCIDevice parent_obj; 86 87 ISABus *isa_bus; 88 qemu_irq *isa_irqs_in; 89 qemu_irq isa_irqs_out[ISA_NUM_IRQS]; 90 uint64_t console_serial_base; 91 MemoryRegion bar0; 92 MemoryRegion bar1; 93 }; 94 95 #define TYPE_EBUS "ebus" 96 OBJECT_DECLARE_SIMPLE_TYPE(EbusState, EBUS) 97 98 const char *fw_cfg_arch_key_name(uint16_t key) 99 { 100 static const struct { 101 uint16_t key; 102 const char *name; 103 } fw_cfg_arch_wellknown_keys[] = { 104 {FW_CFG_SPARC64_WIDTH, "width"}, 105 {FW_CFG_SPARC64_HEIGHT, "height"}, 106 {FW_CFG_SPARC64_DEPTH, "depth"}, 107 }; 108 109 for (size_t i = 0; i < ARRAY_SIZE(fw_cfg_arch_wellknown_keys); i++) { 110 if (fw_cfg_arch_wellknown_keys[i].key == key) { 111 return fw_cfg_arch_wellknown_keys[i].name; 112 } 113 } 114 return NULL; 115 } 116 117 static void fw_cfg_boot_set(void *opaque, const char *boot_device, 118 Error **errp) 119 { 120 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); 121 } 122 123 static int sun4u_NVRAM_set_params(Nvram *nvram, uint16_t NVRAM_size, 124 const char *arch, ram_addr_t RAM_size, 125 const char *boot_devices, 126 uint32_t kernel_image, uint32_t kernel_size, 127 const char *cmdline, 128 uint32_t initrd_image, uint32_t initrd_size, 129 uint32_t NVRAM_image, 130 int width, int height, int depth, 131 const uint8_t *macaddr) 132 { 133 unsigned int i; 134 int sysp_end; 135 uint8_t image[0x1ff0]; 136 NvramClass *k = NVRAM_GET_CLASS(nvram); 137 138 memset(image, '\0', sizeof(image)); 139 140 /* OpenBIOS nvram variables partition */ 141 sysp_end = chrp_nvram_create_system_partition(image, 0, 0x1fd0); 142 143 /* Free space partition */ 144 chrp_nvram_create_free_partition(&image[sysp_end], 0x1fd0 - sysp_end); 145 146 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80); 147 148 for (i = 0; i < sizeof(image); i++) { 149 (k->write)(nvram, i, image[i]); 150 } 151 152 return 0; 153 } 154 155 static uint64_t sun4u_load_kernel(const char *kernel_filename, 156 const char *initrd_filename, 157 ram_addr_t RAM_size, uint64_t *initrd_size, 158 uint64_t *initrd_addr, uint64_t *kernel_addr, 159 uint64_t *kernel_entry) 160 { 161 int linux_boot; 162 unsigned int i; 163 long kernel_size; 164 uint8_t *ptr; 165 uint64_t kernel_top = 0; 166 167 linux_boot = (kernel_filename != NULL); 168 169 kernel_size = 0; 170 if (linux_boot) { 171 int bswap_needed; 172 173 #ifdef BSWAP_NEEDED 174 bswap_needed = 1; 175 #else 176 bswap_needed = 0; 177 #endif 178 kernel_size = load_elf(kernel_filename, NULL, NULL, NULL, kernel_entry, 179 kernel_addr, &kernel_top, NULL, 1, EM_SPARCV9, 0, 180 0); 181 if (kernel_size < 0) { 182 *kernel_addr = KERNEL_LOAD_ADDR; 183 *kernel_entry = KERNEL_LOAD_ADDR; 184 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR, 185 RAM_size - KERNEL_LOAD_ADDR, bswap_needed, 186 TARGET_PAGE_SIZE); 187 } 188 if (kernel_size < 0) { 189 kernel_size = load_image_targphys(kernel_filename, 190 KERNEL_LOAD_ADDR, 191 RAM_size - KERNEL_LOAD_ADDR); 192 } 193 if (kernel_size < 0) { 194 error_report("could not load kernel '%s'", kernel_filename); 195 exit(1); 196 } 197 /* load initrd above kernel */ 198 *initrd_size = 0; 199 if (initrd_filename && kernel_top) { 200 *initrd_addr = TARGET_PAGE_ALIGN(kernel_top); 201 202 *initrd_size = load_image_targphys(initrd_filename, 203 *initrd_addr, 204 RAM_size - *initrd_addr); 205 if ((int)*initrd_size < 0) { 206 error_report("could not load initial ram disk '%s'", 207 initrd_filename); 208 exit(1); 209 } 210 } 211 if (*initrd_size > 0) { 212 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { 213 ptr = rom_ptr(*kernel_addr + i, 32); 214 if (ptr && ldl_p(ptr + 8) == 0x48647253) { /* HdrS */ 215 stl_p(ptr + 24, *initrd_addr + *kernel_addr); 216 stl_p(ptr + 28, *initrd_size); 217 break; 218 } 219 } 220 } 221 } 222 return kernel_size; 223 } 224 225 typedef struct ResetData { 226 SPARCCPU *cpu; 227 uint64_t prom_addr; 228 } ResetData; 229 230 #define TYPE_SUN4U_POWER "power" 231 OBJECT_DECLARE_SIMPLE_TYPE(PowerDevice, SUN4U_POWER) 232 233 struct PowerDevice { 234 SysBusDevice parent_obj; 235 236 MemoryRegion power_mmio; 237 }; 238 239 /* Power */ 240 static uint64_t power_mem_read(void *opaque, hwaddr addr, unsigned size) 241 { 242 return 0; 243 } 244 245 static void power_mem_write(void *opaque, hwaddr addr, 246 uint64_t val, unsigned size) 247 { 248 /* According to a real Ultra 5, bit 24 controls the power */ 249 if (val & 0x1000000) { 250 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); 251 } 252 } 253 254 static const MemoryRegionOps power_mem_ops = { 255 .read = power_mem_read, 256 .write = power_mem_write, 257 .endianness = DEVICE_NATIVE_ENDIAN, 258 .valid = { 259 .min_access_size = 4, 260 .max_access_size = 4, 261 }, 262 }; 263 264 static void power_realize(DeviceState *dev, Error **errp) 265 { 266 PowerDevice *d = SUN4U_POWER(dev); 267 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 268 269 memory_region_init_io(&d->power_mmio, OBJECT(dev), &power_mem_ops, d, 270 "power", sizeof(uint32_t)); 271 272 sysbus_init_mmio(sbd, &d->power_mmio); 273 } 274 275 static void power_class_init(ObjectClass *klass, void *data) 276 { 277 DeviceClass *dc = DEVICE_CLASS(klass); 278 279 dc->realize = power_realize; 280 } 281 282 static const TypeInfo power_info = { 283 .name = TYPE_SUN4U_POWER, 284 .parent = TYPE_SYS_BUS_DEVICE, 285 .instance_size = sizeof(PowerDevice), 286 .class_init = power_class_init, 287 }; 288 289 static void ebus_isa_irq_handler(void *opaque, int n, int level) 290 { 291 EbusState *s = EBUS(opaque); 292 qemu_irq irq = s->isa_irqs_out[n]; 293 294 /* Pass ISA bus IRQs onto their gpio equivalent */ 295 trace_ebus_isa_irq_handler(n, level); 296 if (irq) { 297 qemu_set_irq(irq, level); 298 } 299 } 300 301 /* EBUS (Eight bit bus) bridge */ 302 static void ebus_realize(PCIDevice *pci_dev, Error **errp) 303 { 304 EbusState *s = EBUS(pci_dev); 305 ISADevice *isa_dev; 306 SysBusDevice *sbd; 307 DeviceState *dev; 308 DriveInfo *fd[MAX_FD]; 309 int i; 310 311 s->isa_bus = isa_bus_new(DEVICE(pci_dev), get_system_memory(), 312 pci_address_space_io(pci_dev), errp); 313 if (!s->isa_bus) { 314 error_setg(errp, "unable to instantiate EBUS ISA bus"); 315 return; 316 } 317 318 /* ISA bus */ 319 s->isa_irqs_in = qemu_allocate_irqs(ebus_isa_irq_handler, s, ISA_NUM_IRQS); 320 isa_bus_register_input_irqs(s->isa_bus, s->isa_irqs_in); 321 qdev_init_gpio_out_named(DEVICE(s), s->isa_irqs_out, "isa-irq", 322 ISA_NUM_IRQS); 323 324 /* Serial ports */ 325 i = 0; 326 if (s->console_serial_base) { 327 serial_mm_init(pci_address_space(pci_dev), s->console_serial_base, 328 0, NULL, 115200, serial_hd(i), DEVICE_BIG_ENDIAN); 329 i++; 330 } 331 serial_hds_isa_init(s->isa_bus, i, MAX_ISA_SERIAL_PORTS); 332 333 /* Parallel ports */ 334 parallel_hds_isa_init(s->isa_bus, MAX_PARALLEL_PORTS); 335 336 /* Keyboard */ 337 isa_create_simple(s->isa_bus, TYPE_I8042); 338 339 /* Floppy */ 340 for (i = 0; i < MAX_FD; i++) { 341 fd[i] = drive_get(IF_FLOPPY, 0, i); 342 } 343 isa_dev = isa_new(TYPE_ISA_FDC); 344 dev = DEVICE(isa_dev); 345 qdev_prop_set_uint32(dev, "dma", -1); 346 isa_realize_and_unref(isa_dev, s->isa_bus, &error_fatal); 347 isa_fdc_init_drives(isa_dev, fd); 348 349 /* Power */ 350 dev = qdev_new(TYPE_SUN4U_POWER); 351 sbd = SYS_BUS_DEVICE(dev); 352 sysbus_realize_and_unref(sbd, &error_fatal); 353 memory_region_add_subregion(pci_address_space_io(pci_dev), 0x7240, 354 sysbus_mmio_get_region(sbd, 0)); 355 356 /* PCI */ 357 pci_dev->config[0x04] = 0x06; // command = bus master, pci mem 358 pci_dev->config[0x05] = 0x00; 359 pci_dev->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error 360 pci_dev->config[0x07] = 0x03; // status = medium devsel 361 pci_dev->config[0x09] = 0x00; // programming i/f 362 pci_dev->config[0x0D] = 0x0a; // latency_timer 363 364 /* 365 * BAR0 is accessed by OpenBSD but not for ebus device access: allow any 366 * memory access to this region to succeed which allows the OpenBSD kernel 367 * to boot. 368 */ 369 memory_region_init_io(&s->bar0, OBJECT(s), &unassigned_io_ops, s, 370 "bar0", 0x1000000); 371 pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0); 372 memory_region_init_alias(&s->bar1, OBJECT(s), "bar1", 373 pci_address_space_io(pci_dev), 0, 0x8000); 374 pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->bar1); 375 } 376 377 static const Property ebus_properties[] = { 378 DEFINE_PROP_UINT64("console-serial-base", EbusState, 379 console_serial_base, 0), 380 DEFINE_PROP_END_OF_LIST(), 381 }; 382 383 static void ebus_class_init(ObjectClass *klass, void *data) 384 { 385 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 386 DeviceClass *dc = DEVICE_CLASS(klass); 387 388 k->realize = ebus_realize; 389 k->vendor_id = PCI_VENDOR_ID_SUN; 390 k->device_id = PCI_DEVICE_ID_SUN_EBUS; 391 k->revision = 0x01; 392 k->class_id = PCI_CLASS_BRIDGE_OTHER; 393 device_class_set_props(dc, ebus_properties); 394 } 395 396 static const TypeInfo ebus_info = { 397 .name = TYPE_EBUS, 398 .parent = TYPE_PCI_DEVICE, 399 .class_init = ebus_class_init, 400 .instance_size = sizeof(EbusState), 401 .interfaces = (InterfaceInfo[]) { 402 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 403 { }, 404 }, 405 }; 406 407 #define TYPE_OPENPROM "openprom" 408 typedef struct PROMState PROMState; 409 DECLARE_INSTANCE_CHECKER(PROMState, OPENPROM, 410 TYPE_OPENPROM) 411 412 struct PROMState { 413 SysBusDevice parent_obj; 414 415 MemoryRegion prom; 416 }; 417 418 static uint64_t translate_prom_address(void *opaque, uint64_t addr) 419 { 420 hwaddr *base_addr = (hwaddr *)opaque; 421 return addr + *base_addr - PROM_VADDR; 422 } 423 424 /* Boot PROM (OpenBIOS) */ 425 static void prom_init(hwaddr addr, const char *bios_name) 426 { 427 DeviceState *dev; 428 SysBusDevice *s; 429 char *filename; 430 int ret; 431 432 dev = qdev_new(TYPE_OPENPROM); 433 s = SYS_BUS_DEVICE(dev); 434 sysbus_realize_and_unref(s, &error_fatal); 435 436 sysbus_mmio_map(s, 0, addr); 437 438 /* load boot prom */ 439 if (bios_name == NULL) { 440 bios_name = PROM_FILENAME; 441 } 442 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 443 if (filename) { 444 ret = load_elf(filename, NULL, translate_prom_address, &addr, 445 NULL, NULL, NULL, NULL, 1, EM_SPARCV9, 0, 0); 446 if (ret < 0 || ret > PROM_SIZE_MAX) { 447 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX); 448 } 449 g_free(filename); 450 } else { 451 ret = -1; 452 } 453 if (ret < 0 || ret > PROM_SIZE_MAX) { 454 error_report("could not load prom '%s'", bios_name); 455 exit(1); 456 } 457 } 458 459 static void prom_realize(DeviceState *ds, Error **errp) 460 { 461 PROMState *s = OPENPROM(ds); 462 SysBusDevice *dev = SYS_BUS_DEVICE(ds); 463 464 if (!memory_region_init_ram_nomigrate(&s->prom, OBJECT(ds), "sun4u.prom", 465 PROM_SIZE_MAX, errp)) { 466 return; 467 } 468 469 vmstate_register_ram_global(&s->prom); 470 memory_region_set_readonly(&s->prom, true); 471 sysbus_init_mmio(dev, &s->prom); 472 } 473 474 static void prom_class_init(ObjectClass *klass, void *data) 475 { 476 DeviceClass *dc = DEVICE_CLASS(klass); 477 478 dc->realize = prom_realize; 479 } 480 481 static const TypeInfo prom_info = { 482 .name = TYPE_OPENPROM, 483 .parent = TYPE_SYS_BUS_DEVICE, 484 .instance_size = sizeof(PROMState), 485 .class_init = prom_class_init, 486 }; 487 488 489 #define TYPE_SUN4U_MEMORY "memory" 490 typedef struct RamDevice RamDevice; 491 DECLARE_INSTANCE_CHECKER(RamDevice, SUN4U_RAM, 492 TYPE_SUN4U_MEMORY) 493 494 struct RamDevice { 495 SysBusDevice parent_obj; 496 497 MemoryRegion ram; 498 uint64_t size; 499 }; 500 501 /* System RAM */ 502 static void ram_realize(DeviceState *dev, Error **errp) 503 { 504 RamDevice *d = SUN4U_RAM(dev); 505 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 506 507 memory_region_init_ram_nomigrate(&d->ram, OBJECT(d), "sun4u.ram", d->size, 508 &error_fatal); 509 vmstate_register_ram_global(&d->ram); 510 sysbus_init_mmio(sbd, &d->ram); 511 } 512 513 static void ram_init(hwaddr addr, ram_addr_t RAM_size) 514 { 515 DeviceState *dev; 516 SysBusDevice *s; 517 RamDevice *d; 518 519 /* allocate RAM */ 520 dev = qdev_new(TYPE_SUN4U_MEMORY); 521 s = SYS_BUS_DEVICE(dev); 522 523 d = SUN4U_RAM(dev); 524 d->size = RAM_size; 525 sysbus_realize_and_unref(s, &error_fatal); 526 527 sysbus_mmio_map(s, 0, addr); 528 } 529 530 static const Property ram_properties[] = { 531 DEFINE_PROP_UINT64("size", RamDevice, size, 0), 532 DEFINE_PROP_END_OF_LIST(), 533 }; 534 535 static void ram_class_init(ObjectClass *klass, void *data) 536 { 537 DeviceClass *dc = DEVICE_CLASS(klass); 538 539 dc->realize = ram_realize; 540 device_class_set_props(dc, ram_properties); 541 } 542 543 static const TypeInfo ram_info = { 544 .name = TYPE_SUN4U_MEMORY, 545 .parent = TYPE_SYS_BUS_DEVICE, 546 .instance_size = sizeof(RamDevice), 547 .class_init = ram_class_init, 548 }; 549 550 static void sun4uv_init(MemoryRegion *address_space_mem, 551 MachineState *machine, 552 const struct hwdef *hwdef) 553 { 554 MachineClass *mc = MACHINE_GET_CLASS(machine); 555 SPARCCPU *cpu; 556 Nvram *nvram; 557 unsigned int i; 558 uint64_t initrd_addr, initrd_size, kernel_addr, kernel_size, kernel_entry; 559 SabreState *sabre; 560 PCIBus *pci_bus, *pci_busA, *pci_busB; 561 PCIDevice *ebus, *pci_dev; 562 SysBusDevice *s; 563 DeviceState *iommu, *dev; 564 FWCfgState *fw_cfg; 565 NICInfo *nd; 566 MACAddr macaddr; 567 bool onboard_nic; 568 569 /* init CPUs */ 570 cpu = sparc64_cpu_devinit(machine->cpu_type, hwdef->prom_addr); 571 572 /* IOMMU */ 573 iommu = qdev_new(TYPE_SUN4U_IOMMU); 574 sysbus_realize_and_unref(SYS_BUS_DEVICE(iommu), &error_fatal); 575 576 /* set up devices */ 577 ram_init(0, machine->ram_size); 578 579 prom_init(hwdef->prom_addr, machine->firmware); 580 581 /* Init sabre (PCI host bridge) */ 582 sabre = SABRE(qdev_new(TYPE_SABRE)); 583 qdev_prop_set_uint64(DEVICE(sabre), "special-base", PBM_SPECIAL_BASE); 584 qdev_prop_set_uint64(DEVICE(sabre), "mem-base", PBM_MEM_BASE); 585 object_property_set_link(OBJECT(sabre), "iommu", OBJECT(iommu), 586 &error_abort); 587 sysbus_realize_and_unref(SYS_BUS_DEVICE(sabre), &error_fatal); 588 589 /* sabre_config */ 590 sysbus_mmio_map(SYS_BUS_DEVICE(sabre), 0, PBM_SPECIAL_BASE); 591 /* PCI configuration space */ 592 sysbus_mmio_map(SYS_BUS_DEVICE(sabre), 1, PBM_SPECIAL_BASE + 0x1000000ULL); 593 /* pci_ioport */ 594 sysbus_mmio_map(SYS_BUS_DEVICE(sabre), 2, PBM_SPECIAL_BASE + 0x2000000ULL); 595 596 /* Wire up PCI interrupts to CPU */ 597 for (i = 0; i < IVEC_MAX; i++) { 598 qdev_connect_gpio_out_named(DEVICE(sabre), "ivec-irq", i, 599 qdev_get_gpio_in_named(DEVICE(cpu), "ivec-irq", i)); 600 } 601 602 pci_bus = PCI_HOST_BRIDGE(sabre)->bus; 603 pci_busA = pci_bridge_get_sec_bus(sabre->bridgeA); 604 pci_busB = pci_bridge_get_sec_bus(sabre->bridgeB); 605 606 /* Only in-built Simba APBs can exist on the root bus, slot 0 on busA is 607 reserved (leaving no slots free after on-board devices) however slots 608 0-3 are free on busB */ 609 pci_bus_set_slot_reserved_mask(pci_bus, 0xfffffffc); 610 pci_bus_set_slot_reserved_mask(pci_busA, 0xfffffff1); 611 pci_bus_set_slot_reserved_mask(pci_busB, 0xfffffff0); 612 613 ebus = pci_new_multifunction(PCI_DEVFN(1, 0), TYPE_EBUS); 614 qdev_prop_set_uint64(DEVICE(ebus), "console-serial-base", 615 hwdef->console_serial_base); 616 pci_realize_and_unref(ebus, pci_busA, &error_fatal); 617 618 /* Wire up "well-known" ISA IRQs to PBM legacy obio IRQs */ 619 qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 7, 620 qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_LPT_IRQ)); 621 qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 6, 622 qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_FDD_IRQ)); 623 qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 1, 624 qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_KBD_IRQ)); 625 qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 12, 626 qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_MSE_IRQ)); 627 qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 4, 628 qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_SER_IRQ)); 629 630 switch (vga_interface_type) { 631 case VGA_STD: 632 pci_create_simple(pci_busA, PCI_DEVFN(2, 0), "VGA"); 633 vga_interface_created = true; 634 break; 635 case VGA_NONE: 636 break; 637 default: 638 abort(); /* Should not happen - types are checked in vl.c already */ 639 } 640 641 memset(&macaddr, 0, sizeof(MACAddr)); 642 onboard_nic = false; 643 644 nd = qemu_find_nic_info(mc->default_nic, true, NULL); 645 if (nd) { 646 pci_dev = pci_new_multifunction(PCI_DEVFN(1, 1), mc->default_nic); 647 dev = &pci_dev->qdev; 648 qdev_set_nic_properties(dev, nd); 649 pci_realize_and_unref(pci_dev, pci_busA, &error_fatal); 650 651 memcpy(&macaddr, &nd->macaddr.a, sizeof(MACAddr)); 652 onboard_nic = true; 653 } 654 pci_init_nic_devices(pci_busB, mc->default_nic); 655 656 /* If we don't have an onboard NIC, grab a default MAC address so that 657 * we have a valid machine id */ 658 if (!onboard_nic) { 659 qemu_macaddr_default_if_unset(&macaddr); 660 } 661 662 pci_dev = pci_new(PCI_DEVFN(3, 0), "cmd646-ide"); 663 qdev_prop_set_uint32(&pci_dev->qdev, "secondary", 1); 664 pci_realize_and_unref(pci_dev, pci_busA, &error_fatal); 665 pci_ide_create_devs(pci_dev); 666 667 /* Map NVRAM into I/O (ebus) space */ 668 dev = qdev_new("sysbus-m48t59"); 669 qdev_prop_set_int32(dev, "base-year", 1968); 670 s = SYS_BUS_DEVICE(dev); 671 sysbus_realize_and_unref(s, &error_fatal); 672 memory_region_add_subregion(pci_address_space_io(ebus), 0x2000, 673 sysbus_mmio_get_region(s, 0)); 674 nvram = NVRAM(dev); 675 676 initrd_size = 0; 677 initrd_addr = 0; 678 kernel_size = sun4u_load_kernel(machine->kernel_filename, 679 machine->initrd_filename, 680 machine->ram_size, &initrd_size, &initrd_addr, 681 &kernel_addr, &kernel_entry); 682 683 sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", machine->ram_size, 684 machine->boot_config.order, 685 kernel_addr, kernel_size, 686 machine->kernel_cmdline, 687 initrd_addr, initrd_size, 688 /* XXX: need an option to load a NVRAM image */ 689 0, 690 graphic_width, graphic_height, graphic_depth, 691 (uint8_t *)&macaddr); 692 693 dev = qdev_new(TYPE_FW_CFG_IO); 694 qdev_prop_set_bit(dev, "dma_enabled", false); 695 object_property_add_child(OBJECT(ebus), TYPE_FW_CFG, OBJECT(dev)); 696 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 697 memory_region_add_subregion(pci_address_space_io(ebus), BIOS_CFG_IOPORT, 698 &FW_CFG_IO(dev)->comb_iomem); 699 700 fw_cfg = FW_CFG(dev); 701 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)machine->smp.cpus); 702 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)machine->smp.max_cpus); 703 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)machine->ram_size); 704 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); 705 fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_entry); 706 fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 707 if (machine->kernel_cmdline) { 708 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 709 strlen(machine->kernel_cmdline) + 1); 710 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline); 711 } else { 712 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0); 713 } 714 fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); 715 fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 716 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_config.order[0]); 717 718 fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_WIDTH, graphic_width); 719 fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_HEIGHT, graphic_height); 720 fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_DEPTH, graphic_depth); 721 722 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); 723 } 724 725 enum { 726 sun4u_id = 0, 727 sun4v_id = 64, 728 }; 729 730 /* 731 * Implementation of an interface to adjust firmware path 732 * for the bootindex property handling. 733 */ 734 static char *sun4u_fw_dev_path(FWPathProvider *p, BusState *bus, 735 DeviceState *dev) 736 { 737 PCIDevice *pci; 738 739 if (!strcmp(object_get_typename(OBJECT(dev)), "pbm-bridge")) { 740 pci = PCI_DEVICE(dev); 741 742 if (PCI_FUNC(pci->devfn)) { 743 return g_strdup_printf("pci@%x,%x", PCI_SLOT(pci->devfn), 744 PCI_FUNC(pci->devfn)); 745 } else { 746 return g_strdup_printf("pci@%x", PCI_SLOT(pci->devfn)); 747 } 748 } 749 750 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-hd")) { 751 return g_strdup("disk"); 752 } 753 754 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-cd")) { 755 return g_strdup("cdrom"); 756 } 757 758 if (!strcmp(object_get_typename(OBJECT(dev)), "virtio-blk-device")) { 759 return g_strdup("disk"); 760 } 761 762 return NULL; 763 } 764 765 static const struct hwdef hwdefs[] = { 766 /* Sun4u generic PC-like machine */ 767 { 768 .machine_id = sun4u_id, 769 .prom_addr = 0x1fff0000000ULL, 770 .console_serial_base = 0, 771 }, 772 /* Sun4v generic PC-like machine */ 773 { 774 .machine_id = sun4v_id, 775 .prom_addr = 0x1fff0000000ULL, 776 .console_serial_base = 0, 777 }, 778 }; 779 780 /* Sun4u hardware initialisation */ 781 static void sun4u_init(MachineState *machine) 782 { 783 sun4uv_init(get_system_memory(), machine, &hwdefs[0]); 784 } 785 786 /* Sun4v hardware initialisation */ 787 static void sun4v_init(MachineState *machine) 788 { 789 sun4uv_init(get_system_memory(), machine, &hwdefs[1]); 790 } 791 792 static GlobalProperty hw_compat_sparc64[] = { 793 { "virtio-pci", "disable-legacy", "on", .optional = true }, 794 { "virtio-device", "iommu_platform", "on" }, 795 }; 796 static const size_t hw_compat_sparc64_len = G_N_ELEMENTS(hw_compat_sparc64); 797 798 static void sun4u_class_init(ObjectClass *oc, void *data) 799 { 800 MachineClass *mc = MACHINE_CLASS(oc); 801 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 802 803 mc->desc = "Sun4u platform"; 804 mc->init = sun4u_init; 805 mc->block_default_type = IF_IDE; 806 mc->max_cpus = 1; /* XXX for now */ 807 mc->is_default = true; 808 mc->default_boot_order = "c"; 809 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-UltraSparc-IIi"); 810 mc->ignore_boot_device_suffixes = true; 811 mc->default_display = "std"; 812 mc->default_nic = "sunhme"; 813 mc->no_parallel = !module_object_class_by_name(TYPE_ISA_PARALLEL); 814 fwc->get_dev_path = sun4u_fw_dev_path; 815 compat_props_add(mc->compat_props, hw_compat_sparc64, hw_compat_sparc64_len); 816 } 817 818 static const TypeInfo sun4u_type = { 819 .name = MACHINE_TYPE_NAME("sun4u"), 820 .parent = TYPE_MACHINE, 821 .class_init = sun4u_class_init, 822 .interfaces = (InterfaceInfo[]) { 823 { TYPE_FW_PATH_PROVIDER }, 824 { } 825 }, 826 }; 827 828 static void sun4v_class_init(ObjectClass *oc, void *data) 829 { 830 MachineClass *mc = MACHINE_CLASS(oc); 831 832 mc->desc = "Sun4v platform"; 833 mc->init = sun4v_init; 834 mc->block_default_type = IF_IDE; 835 mc->max_cpus = 1; /* XXX for now */ 836 mc->default_boot_order = "c"; 837 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Sun-UltraSparc-T1"); 838 mc->default_display = "std"; 839 mc->default_nic = "sunhme"; 840 mc->no_parallel = !module_object_class_by_name(TYPE_ISA_PARALLEL); 841 } 842 843 static const TypeInfo sun4v_type = { 844 .name = MACHINE_TYPE_NAME("sun4v"), 845 .parent = TYPE_MACHINE, 846 .class_init = sun4v_class_init, 847 }; 848 849 static void sun4u_register_types(void) 850 { 851 type_register_static(&power_info); 852 type_register_static(&ebus_info); 853 type_register_static(&prom_info); 854 type_register_static(&ram_info); 855 856 type_register_static(&sun4u_type); 857 type_register_static(&sun4v_type); 858 } 859 860 type_init(sun4u_register_types) 861