1 /* 2 * QEMU Sun4u/Sun4v System Emulator 3 * 4 * Copyright (c) 2005 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "qemu/osdep.h" 25 #include "qapi/error.h" 26 #include "qemu-common.h" 27 #include "cpu.h" 28 #include "hw/hw.h" 29 #include "hw/pci/pci.h" 30 #include "hw/pci/pci_bus.h" 31 #include "hw/pci-host/apb.h" 32 #include "hw/i386/pc.h" 33 #include "hw/char/serial.h" 34 #include "hw/timer/m48t59.h" 35 #include "hw/block/fdc.h" 36 #include "net/net.h" 37 #include "qemu/timer.h" 38 #include "sysemu/sysemu.h" 39 #include "hw/boards.h" 40 #include "hw/nvram/sun_nvram.h" 41 #include "hw/nvram/chrp_nvram.h" 42 #include "hw/sparc/sparc64.h" 43 #include "hw/nvram/fw_cfg.h" 44 #include "hw/sysbus.h" 45 #include "hw/ide.h" 46 #include "hw/ide/pci.h" 47 #include "hw/loader.h" 48 #include "elf.h" 49 #include "qemu/cutils.h" 50 51 //#define DEBUG_EBUS 52 53 #ifdef DEBUG_EBUS 54 #define EBUS_DPRINTF(fmt, ...) \ 55 do { printf("EBUS: " fmt , ## __VA_ARGS__); } while (0) 56 #else 57 #define EBUS_DPRINTF(fmt, ...) 58 #endif 59 60 #define KERNEL_LOAD_ADDR 0x00404000 61 #define CMDLINE_ADDR 0x003ff000 62 #define PROM_SIZE_MAX (4 * 1024 * 1024) 63 #define PROM_VADDR 0x000ffd00000ULL 64 #define APB_SPECIAL_BASE 0x1fe00000000ULL 65 #define APB_MEM_BASE 0x1ff00000000ULL 66 #define APB_PCI_IO_BASE (APB_SPECIAL_BASE + 0x02000000ULL) 67 #define PROM_FILENAME "openbios-sparc64" 68 #define NVRAM_SIZE 0x2000 69 #define MAX_IDE_BUS 2 70 #define BIOS_CFG_IOPORT 0x510 71 #define FW_CFG_SPARC64_WIDTH (FW_CFG_ARCH_LOCAL + 0x00) 72 #define FW_CFG_SPARC64_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01) 73 #define FW_CFG_SPARC64_DEPTH (FW_CFG_ARCH_LOCAL + 0x02) 74 75 #define IVEC_MAX 0x40 76 77 struct hwdef { 78 uint16_t machine_id; 79 uint64_t prom_addr; 80 uint64_t console_serial_base; 81 }; 82 83 typedef struct EbusState { 84 /*< private >*/ 85 PCIDevice parent_obj; 86 87 ISABus *isa_bus; 88 uint64_t console_serial_base; 89 MemoryRegion bar0; 90 MemoryRegion bar1; 91 } EbusState; 92 93 #define TYPE_EBUS "ebus" 94 #define EBUS(obj) OBJECT_CHECK(EbusState, (obj), TYPE_EBUS) 95 96 void DMA_init(ISABus *bus, int high_page_enable) 97 { 98 } 99 100 static void fw_cfg_boot_set(void *opaque, const char *boot_device, 101 Error **errp) 102 { 103 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); 104 } 105 106 static int sun4u_NVRAM_set_params(Nvram *nvram, uint16_t NVRAM_size, 107 const char *arch, ram_addr_t RAM_size, 108 const char *boot_devices, 109 uint32_t kernel_image, uint32_t kernel_size, 110 const char *cmdline, 111 uint32_t initrd_image, uint32_t initrd_size, 112 uint32_t NVRAM_image, 113 int width, int height, int depth, 114 const uint8_t *macaddr) 115 { 116 unsigned int i; 117 int sysp_end; 118 uint8_t image[0x1ff0]; 119 NvramClass *k = NVRAM_GET_CLASS(nvram); 120 121 memset(image, '\0', sizeof(image)); 122 123 /* OpenBIOS nvram variables partition */ 124 sysp_end = chrp_nvram_create_system_partition(image, 0); 125 126 /* Free space partition */ 127 chrp_nvram_create_free_partition(&image[sysp_end], 0x1fd0 - sysp_end); 128 129 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80); 130 131 for (i = 0; i < sizeof(image); i++) { 132 (k->write)(nvram, i, image[i]); 133 } 134 135 return 0; 136 } 137 138 static uint64_t sun4u_load_kernel(const char *kernel_filename, 139 const char *initrd_filename, 140 ram_addr_t RAM_size, uint64_t *initrd_size, 141 uint64_t *initrd_addr, uint64_t *kernel_addr, 142 uint64_t *kernel_entry) 143 { 144 int linux_boot; 145 unsigned int i; 146 long kernel_size; 147 uint8_t *ptr; 148 uint64_t kernel_top; 149 150 linux_boot = (kernel_filename != NULL); 151 152 kernel_size = 0; 153 if (linux_boot) { 154 int bswap_needed; 155 156 #ifdef BSWAP_NEEDED 157 bswap_needed = 1; 158 #else 159 bswap_needed = 0; 160 #endif 161 kernel_size = load_elf(kernel_filename, NULL, NULL, kernel_entry, 162 kernel_addr, &kernel_top, 1, EM_SPARCV9, 0, 0); 163 if (kernel_size < 0) { 164 *kernel_addr = KERNEL_LOAD_ADDR; 165 *kernel_entry = KERNEL_LOAD_ADDR; 166 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR, 167 RAM_size - KERNEL_LOAD_ADDR, bswap_needed, 168 TARGET_PAGE_SIZE); 169 } 170 if (kernel_size < 0) { 171 kernel_size = load_image_targphys(kernel_filename, 172 KERNEL_LOAD_ADDR, 173 RAM_size - KERNEL_LOAD_ADDR); 174 } 175 if (kernel_size < 0) { 176 fprintf(stderr, "qemu: could not load kernel '%s'\n", 177 kernel_filename); 178 exit(1); 179 } 180 /* load initrd above kernel */ 181 *initrd_size = 0; 182 if (initrd_filename) { 183 *initrd_addr = TARGET_PAGE_ALIGN(kernel_top); 184 185 *initrd_size = load_image_targphys(initrd_filename, 186 *initrd_addr, 187 RAM_size - *initrd_addr); 188 if ((int)*initrd_size < 0) { 189 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", 190 initrd_filename); 191 exit(1); 192 } 193 } 194 if (*initrd_size > 0) { 195 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { 196 ptr = rom_ptr(*kernel_addr + i); 197 if (ldl_p(ptr + 8) == 0x48647253) { /* HdrS */ 198 stl_p(ptr + 24, *initrd_addr + *kernel_addr); 199 stl_p(ptr + 28, *initrd_size); 200 break; 201 } 202 } 203 } 204 } 205 return kernel_size; 206 } 207 208 typedef struct ResetData { 209 SPARCCPU *cpu; 210 uint64_t prom_addr; 211 } ResetData; 212 213 static void isa_irq_handler(void *opaque, int n, int level) 214 { 215 static const int isa_irq_to_ivec[16] = { 216 [1] = 0x29, /* keyboard */ 217 [4] = 0x2b, /* serial */ 218 [6] = 0x27, /* floppy */ 219 [7] = 0x22, /* parallel */ 220 [12] = 0x2a, /* mouse */ 221 }; 222 qemu_irq *irqs = opaque; 223 int ivec; 224 225 assert(n < ARRAY_SIZE(isa_irq_to_ivec)); 226 ivec = isa_irq_to_ivec[n]; 227 EBUS_DPRINTF("Set ISA IRQ %d level %d -> ivec 0x%x\n", n, level, ivec); 228 if (ivec) { 229 qemu_set_irq(irqs[ivec], level); 230 } 231 } 232 233 /* EBUS (Eight bit bus) bridge */ 234 static void ebus_realize(PCIDevice *pci_dev, Error **errp) 235 { 236 EbusState *s = EBUS(pci_dev); 237 APBState *apb; 238 DeviceState *dev; 239 qemu_irq *isa_irq; 240 DriveInfo *fd[MAX_FD]; 241 int i; 242 243 s->isa_bus = isa_bus_new(DEVICE(pci_dev), get_system_memory(), 244 pci_address_space_io(pci_dev), errp); 245 if (!s->isa_bus) { 246 error_setg(errp, "unable to instantiate EBUS ISA bus"); 247 return; 248 } 249 250 apb = APB_DEVICE(object_resolve_path_type("", TYPE_APB, NULL)); 251 if (!apb) { 252 error_setg(errp, "unable to locate APB PCI host bridge"); 253 return; 254 } 255 256 isa_irq = qemu_allocate_irqs(isa_irq_handler, apb->pbm_irqs, 16); 257 isa_bus_irqs(s->isa_bus, isa_irq); 258 259 /* Serial ports */ 260 i = 0; 261 if (s->console_serial_base) { 262 serial_mm_init(pci_address_space(pci_dev), s->console_serial_base, 263 0, NULL, 115200, serial_hds[i], DEVICE_BIG_ENDIAN); 264 i++; 265 } 266 serial_hds_isa_init(s->isa_bus, i, MAX_SERIAL_PORTS); 267 268 /* Parallel ports */ 269 parallel_hds_isa_init(s->isa_bus, MAX_PARALLEL_PORTS); 270 271 /* Keyboard */ 272 isa_create_simple(s->isa_bus, "i8042"); 273 274 /* Floppy */ 275 for (i = 0; i < MAX_FD; i++) { 276 fd[i] = drive_get(IF_FLOPPY, 0, i); 277 } 278 dev = DEVICE(isa_create(s->isa_bus, TYPE_ISA_FDC)); 279 if (fd[0]) { 280 qdev_prop_set_drive(dev, "driveA", blk_by_legacy_dinfo(fd[0]), 281 &error_abort); 282 } 283 if (fd[1]) { 284 qdev_prop_set_drive(dev, "driveB", blk_by_legacy_dinfo(fd[1]), 285 &error_abort); 286 } 287 qdev_prop_set_uint32(dev, "dma", -1); 288 qdev_init_nofail(dev); 289 290 /* PCI */ 291 pci_dev->config[0x04] = 0x06; // command = bus master, pci mem 292 pci_dev->config[0x05] = 0x00; 293 pci_dev->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error 294 pci_dev->config[0x07] = 0x03; // status = medium devsel 295 pci_dev->config[0x09] = 0x00; // programming i/f 296 pci_dev->config[0x0D] = 0x0a; // latency_timer 297 298 memory_region_init_alias(&s->bar0, OBJECT(s), "bar0", get_system_io(), 299 0, 0x1000000); 300 pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0); 301 memory_region_init_alias(&s->bar1, OBJECT(s), "bar1", get_system_io(), 302 0, 0x4000); 303 pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->bar1); 304 } 305 306 static Property ebus_properties[] = { 307 DEFINE_PROP_UINT64("console-serial-base", EbusState, 308 console_serial_base, 0), 309 DEFINE_PROP_END_OF_LIST(), 310 }; 311 312 static void ebus_class_init(ObjectClass *klass, void *data) 313 { 314 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 315 DeviceClass *dc = DEVICE_CLASS(klass); 316 317 k->realize = ebus_realize; 318 k->vendor_id = PCI_VENDOR_ID_SUN; 319 k->device_id = PCI_DEVICE_ID_SUN_EBUS; 320 k->revision = 0x01; 321 k->class_id = PCI_CLASS_BRIDGE_OTHER; 322 dc->props = ebus_properties; 323 } 324 325 static const TypeInfo ebus_info = { 326 .name = TYPE_EBUS, 327 .parent = TYPE_PCI_DEVICE, 328 .class_init = ebus_class_init, 329 .instance_size = sizeof(EbusState), 330 .interfaces = (InterfaceInfo[]) { 331 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 332 { }, 333 }, 334 }; 335 336 #define TYPE_OPENPROM "openprom" 337 #define OPENPROM(obj) OBJECT_CHECK(PROMState, (obj), TYPE_OPENPROM) 338 339 typedef struct PROMState { 340 SysBusDevice parent_obj; 341 342 MemoryRegion prom; 343 } PROMState; 344 345 static uint64_t translate_prom_address(void *opaque, uint64_t addr) 346 { 347 hwaddr *base_addr = (hwaddr *)opaque; 348 return addr + *base_addr - PROM_VADDR; 349 } 350 351 /* Boot PROM (OpenBIOS) */ 352 static void prom_init(hwaddr addr, const char *bios_name) 353 { 354 DeviceState *dev; 355 SysBusDevice *s; 356 char *filename; 357 int ret; 358 359 dev = qdev_create(NULL, TYPE_OPENPROM); 360 qdev_init_nofail(dev); 361 s = SYS_BUS_DEVICE(dev); 362 363 sysbus_mmio_map(s, 0, addr); 364 365 /* load boot prom */ 366 if (bios_name == NULL) { 367 bios_name = PROM_FILENAME; 368 } 369 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 370 if (filename) { 371 ret = load_elf(filename, translate_prom_address, &addr, 372 NULL, NULL, NULL, 1, EM_SPARCV9, 0, 0); 373 if (ret < 0 || ret > PROM_SIZE_MAX) { 374 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX); 375 } 376 g_free(filename); 377 } else { 378 ret = -1; 379 } 380 if (ret < 0 || ret > PROM_SIZE_MAX) { 381 fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name); 382 exit(1); 383 } 384 } 385 386 static void prom_init1(Object *obj) 387 { 388 PROMState *s = OPENPROM(obj); 389 SysBusDevice *dev = SYS_BUS_DEVICE(obj); 390 391 memory_region_init_ram_nomigrate(&s->prom, obj, "sun4u.prom", PROM_SIZE_MAX, 392 &error_fatal); 393 vmstate_register_ram_global(&s->prom); 394 memory_region_set_readonly(&s->prom, true); 395 sysbus_init_mmio(dev, &s->prom); 396 } 397 398 static Property prom_properties[] = { 399 {/* end of property list */}, 400 }; 401 402 static void prom_class_init(ObjectClass *klass, void *data) 403 { 404 DeviceClass *dc = DEVICE_CLASS(klass); 405 406 dc->props = prom_properties; 407 } 408 409 static const TypeInfo prom_info = { 410 .name = TYPE_OPENPROM, 411 .parent = TYPE_SYS_BUS_DEVICE, 412 .instance_size = sizeof(PROMState), 413 .class_init = prom_class_init, 414 .instance_init = prom_init1, 415 }; 416 417 418 #define TYPE_SUN4U_MEMORY "memory" 419 #define SUN4U_RAM(obj) OBJECT_CHECK(RamDevice, (obj), TYPE_SUN4U_MEMORY) 420 421 typedef struct RamDevice { 422 SysBusDevice parent_obj; 423 424 MemoryRegion ram; 425 uint64_t size; 426 } RamDevice; 427 428 /* System RAM */ 429 static void ram_realize(DeviceState *dev, Error **errp) 430 { 431 RamDevice *d = SUN4U_RAM(dev); 432 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 433 434 memory_region_init_ram_nomigrate(&d->ram, OBJECT(d), "sun4u.ram", d->size, 435 &error_fatal); 436 vmstate_register_ram_global(&d->ram); 437 sysbus_init_mmio(sbd, &d->ram); 438 } 439 440 static void ram_init(hwaddr addr, ram_addr_t RAM_size) 441 { 442 DeviceState *dev; 443 SysBusDevice *s; 444 RamDevice *d; 445 446 /* allocate RAM */ 447 dev = qdev_create(NULL, TYPE_SUN4U_MEMORY); 448 s = SYS_BUS_DEVICE(dev); 449 450 d = SUN4U_RAM(dev); 451 d->size = RAM_size; 452 qdev_init_nofail(dev); 453 454 sysbus_mmio_map(s, 0, addr); 455 } 456 457 static Property ram_properties[] = { 458 DEFINE_PROP_UINT64("size", RamDevice, size, 0), 459 DEFINE_PROP_END_OF_LIST(), 460 }; 461 462 static void ram_class_init(ObjectClass *klass, void *data) 463 { 464 DeviceClass *dc = DEVICE_CLASS(klass); 465 466 dc->realize = ram_realize; 467 dc->props = ram_properties; 468 } 469 470 static const TypeInfo ram_info = { 471 .name = TYPE_SUN4U_MEMORY, 472 .parent = TYPE_SYS_BUS_DEVICE, 473 .instance_size = sizeof(RamDevice), 474 .class_init = ram_class_init, 475 }; 476 477 static void sun4uv_init(MemoryRegion *address_space_mem, 478 MachineState *machine, 479 const struct hwdef *hwdef) 480 { 481 SPARCCPU *cpu; 482 Nvram *nvram; 483 unsigned int i; 484 uint64_t initrd_addr, initrd_size, kernel_addr, kernel_size, kernel_entry; 485 APBState *apb; 486 PCIBus *pci_bus, *pci_busA, *pci_busB; 487 PCIDevice *ebus, *pci_dev; 488 SysBusDevice *s; 489 qemu_irq *ivec_irqs; 490 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; 491 DeviceState *dev; 492 FWCfgState *fw_cfg; 493 NICInfo *nd; 494 MACAddr macaddr; 495 bool onboard_nic; 496 497 /* init CPUs */ 498 cpu = sparc64_cpu_devinit(machine->cpu_type, hwdef->prom_addr); 499 500 /* set up devices */ 501 ram_init(0, machine->ram_size); 502 503 prom_init(hwdef->prom_addr, bios_name); 504 505 ivec_irqs = qemu_allocate_irqs(sparc64_cpu_set_ivec_irq, cpu, IVEC_MAX); 506 apb = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, ivec_irqs, &pci_busA, 507 &pci_busB); 508 pci_bus = PCI_HOST_BRIDGE(apb)->bus; 509 510 /* Only in-built Simba PBMs can exist on the root bus, slot 0 on busA is 511 reserved (leaving no slots free after on-board devices) however slots 512 0-3 are free on busB */ 513 pci_bus->slot_reserved_mask = 0xfffffffc; 514 pci_busA->slot_reserved_mask = 0xfffffff1; 515 pci_busB->slot_reserved_mask = 0xfffffff0; 516 517 ebus = pci_create_multifunction(pci_busA, PCI_DEVFN(1, 0), true, TYPE_EBUS); 518 qdev_prop_set_uint64(DEVICE(ebus), "console-serial-base", 519 hwdef->console_serial_base); 520 qdev_init_nofail(DEVICE(ebus)); 521 522 pci_dev = pci_create_simple(pci_busA, PCI_DEVFN(2, 0), "VGA"); 523 524 memset(&macaddr, 0, sizeof(MACAddr)); 525 onboard_nic = false; 526 for (i = 0; i < nb_nics; i++) { 527 nd = &nd_table[i]; 528 529 if (!nd->model || strcmp(nd->model, "sunhme") == 0) { 530 if (!onboard_nic) { 531 pci_dev = pci_create_multifunction(pci_busA, PCI_DEVFN(1, 1), 532 true, "sunhme"); 533 memcpy(&macaddr, &nd->macaddr.a, sizeof(MACAddr)); 534 onboard_nic = true; 535 } else { 536 pci_dev = pci_create(pci_busB, -1, "sunhme"); 537 } 538 } else { 539 pci_dev = pci_create(pci_busB, -1, nd->model); 540 } 541 542 dev = &pci_dev->qdev; 543 qdev_set_nic_properties(dev, nd); 544 qdev_init_nofail(dev); 545 } 546 547 /* If we don't have an onboard NIC, grab a default MAC address so that 548 * we have a valid machine id */ 549 if (!onboard_nic) { 550 qemu_macaddr_default_if_unset(&macaddr); 551 } 552 553 ide_drive_get(hd, ARRAY_SIZE(hd)); 554 555 pci_dev = pci_create(pci_busA, PCI_DEVFN(3, 0), "cmd646-ide"); 556 qdev_prop_set_uint32(&pci_dev->qdev, "secondary", 1); 557 qdev_init_nofail(&pci_dev->qdev); 558 pci_ide_create_devs(pci_dev, hd); 559 560 /* Map NVRAM into I/O (ebus) space */ 561 nvram = m48t59_init(NULL, 0, 0, NVRAM_SIZE, 1968, 59); 562 s = SYS_BUS_DEVICE(nvram); 563 memory_region_add_subregion(pci_address_space_io(ebus), 0x2000, 564 sysbus_mmio_get_region(s, 0)); 565 566 initrd_size = 0; 567 initrd_addr = 0; 568 kernel_size = sun4u_load_kernel(machine->kernel_filename, 569 machine->initrd_filename, 570 ram_size, &initrd_size, &initrd_addr, 571 &kernel_addr, &kernel_entry); 572 573 sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", machine->ram_size, 574 machine->boot_order, 575 kernel_addr, kernel_size, 576 machine->kernel_cmdline, 577 initrd_addr, initrd_size, 578 /* XXX: need an option to load a NVRAM image */ 579 0, 580 graphic_width, graphic_height, graphic_depth, 581 (uint8_t *)&macaddr); 582 583 dev = qdev_create(NULL, TYPE_FW_CFG_IO); 584 qdev_prop_set_bit(dev, "dma_enabled", false); 585 object_property_add_child(OBJECT(ebus), TYPE_FW_CFG, OBJECT(dev), NULL); 586 qdev_init_nofail(dev); 587 memory_region_add_subregion(pci_address_space_io(ebus), BIOS_CFG_IOPORT, 588 &FW_CFG_IO(dev)->comb_iomem); 589 590 fw_cfg = FW_CFG(dev); 591 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus); 592 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus); 593 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 594 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); 595 fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_entry); 596 fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 597 if (machine->kernel_cmdline) { 598 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 599 strlen(machine->kernel_cmdline) + 1); 600 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline); 601 } else { 602 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0); 603 } 604 fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); 605 fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 606 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]); 607 608 fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_WIDTH, graphic_width); 609 fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_HEIGHT, graphic_height); 610 fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_DEPTH, graphic_depth); 611 612 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); 613 } 614 615 enum { 616 sun4u_id = 0, 617 sun4v_id = 64, 618 }; 619 620 static const struct hwdef hwdefs[] = { 621 /* Sun4u generic PC-like machine */ 622 { 623 .machine_id = sun4u_id, 624 .prom_addr = 0x1fff0000000ULL, 625 .console_serial_base = 0, 626 }, 627 /* Sun4v generic PC-like machine */ 628 { 629 .machine_id = sun4v_id, 630 .prom_addr = 0x1fff0000000ULL, 631 .console_serial_base = 0, 632 }, 633 }; 634 635 /* Sun4u hardware initialisation */ 636 static void sun4u_init(MachineState *machine) 637 { 638 sun4uv_init(get_system_memory(), machine, &hwdefs[0]); 639 } 640 641 /* Sun4v hardware initialisation */ 642 static void sun4v_init(MachineState *machine) 643 { 644 sun4uv_init(get_system_memory(), machine, &hwdefs[1]); 645 } 646 647 static void sun4u_class_init(ObjectClass *oc, void *data) 648 { 649 MachineClass *mc = MACHINE_CLASS(oc); 650 651 mc->desc = "Sun4u platform"; 652 mc->init = sun4u_init; 653 mc->block_default_type = IF_IDE; 654 mc->max_cpus = 1; /* XXX for now */ 655 mc->is_default = 1; 656 mc->default_boot_order = "c"; 657 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-UltraSparc-IIi"); 658 } 659 660 static const TypeInfo sun4u_type = { 661 .name = MACHINE_TYPE_NAME("sun4u"), 662 .parent = TYPE_MACHINE, 663 .class_init = sun4u_class_init, 664 }; 665 666 static void sun4v_class_init(ObjectClass *oc, void *data) 667 { 668 MachineClass *mc = MACHINE_CLASS(oc); 669 670 mc->desc = "Sun4v platform"; 671 mc->init = sun4v_init; 672 mc->block_default_type = IF_IDE; 673 mc->max_cpus = 1; /* XXX for now */ 674 mc->default_boot_order = "c"; 675 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Sun-UltraSparc-T1"); 676 } 677 678 static const TypeInfo sun4v_type = { 679 .name = MACHINE_TYPE_NAME("sun4v"), 680 .parent = TYPE_MACHINE, 681 .class_init = sun4v_class_init, 682 }; 683 684 static void sun4u_register_types(void) 685 { 686 type_register_static(&ebus_info); 687 type_register_static(&prom_info); 688 type_register_static(&ram_info); 689 690 type_register_static(&sun4u_type); 691 type_register_static(&sun4v_type); 692 } 693 694 type_init(sun4u_register_types) 695