1 /* 2 * QEMU Sun4u/Sun4v System Emulator 3 * 4 * Copyright (c) 2005 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "qemu/osdep.h" 25 #include "qapi/error.h" 26 #include "qemu-common.h" 27 #include "cpu.h" 28 #include "hw/hw.h" 29 #include "hw/pci/pci.h" 30 #include "hw/pci/pci_bridge.h" 31 #include "hw/pci/pci_bus.h" 32 #include "hw/pci-host/apb.h" 33 #include "hw/i386/pc.h" 34 #include "hw/char/serial.h" 35 #include "hw/timer/m48t59.h" 36 #include "hw/block/fdc.h" 37 #include "net/net.h" 38 #include "qemu/timer.h" 39 #include "sysemu/sysemu.h" 40 #include "hw/boards.h" 41 #include "hw/nvram/sun_nvram.h" 42 #include "hw/nvram/chrp_nvram.h" 43 #include "hw/sparc/sparc64.h" 44 #include "hw/nvram/fw_cfg.h" 45 #include "hw/sysbus.h" 46 #include "hw/ide.h" 47 #include "hw/ide/pci.h" 48 #include "hw/loader.h" 49 #include "elf.h" 50 #include "qemu/cutils.h" 51 52 //#define DEBUG_EBUS 53 54 #ifdef DEBUG_EBUS 55 #define EBUS_DPRINTF(fmt, ...) \ 56 do { printf("EBUS: " fmt , ## __VA_ARGS__); } while (0) 57 #else 58 #define EBUS_DPRINTF(fmt, ...) 59 #endif 60 61 #define KERNEL_LOAD_ADDR 0x00404000 62 #define CMDLINE_ADDR 0x003ff000 63 #define PROM_SIZE_MAX (4 * 1024 * 1024) 64 #define PROM_VADDR 0x000ffd00000ULL 65 #define APB_SPECIAL_BASE 0x1fe00000000ULL 66 #define APB_MEM_BASE 0x1ff00000000ULL 67 #define APB_PCI_IO_BASE (APB_SPECIAL_BASE + 0x02000000ULL) 68 #define PROM_FILENAME "openbios-sparc64" 69 #define NVRAM_SIZE 0x2000 70 #define MAX_IDE_BUS 2 71 #define BIOS_CFG_IOPORT 0x510 72 #define FW_CFG_SPARC64_WIDTH (FW_CFG_ARCH_LOCAL + 0x00) 73 #define FW_CFG_SPARC64_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01) 74 #define FW_CFG_SPARC64_DEPTH (FW_CFG_ARCH_LOCAL + 0x02) 75 76 #define IVEC_MAX 0x40 77 78 struct hwdef { 79 uint16_t machine_id; 80 uint64_t prom_addr; 81 uint64_t console_serial_base; 82 }; 83 84 typedef struct EbusState { 85 /*< private >*/ 86 PCIDevice parent_obj; 87 88 ISABus *isa_bus; 89 qemu_irq isa_bus_irqs[ISA_NUM_IRQS]; 90 uint64_t console_serial_base; 91 MemoryRegion bar0; 92 MemoryRegion bar1; 93 } EbusState; 94 95 #define TYPE_EBUS "ebus" 96 #define EBUS(obj) OBJECT_CHECK(EbusState, (obj), TYPE_EBUS) 97 98 void DMA_init(ISABus *bus, int high_page_enable) 99 { 100 } 101 102 static void fw_cfg_boot_set(void *opaque, const char *boot_device, 103 Error **errp) 104 { 105 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); 106 } 107 108 static int sun4u_NVRAM_set_params(Nvram *nvram, uint16_t NVRAM_size, 109 const char *arch, ram_addr_t RAM_size, 110 const char *boot_devices, 111 uint32_t kernel_image, uint32_t kernel_size, 112 const char *cmdline, 113 uint32_t initrd_image, uint32_t initrd_size, 114 uint32_t NVRAM_image, 115 int width, int height, int depth, 116 const uint8_t *macaddr) 117 { 118 unsigned int i; 119 int sysp_end; 120 uint8_t image[0x1ff0]; 121 NvramClass *k = NVRAM_GET_CLASS(nvram); 122 123 memset(image, '\0', sizeof(image)); 124 125 /* OpenBIOS nvram variables partition */ 126 sysp_end = chrp_nvram_create_system_partition(image, 0); 127 128 /* Free space partition */ 129 chrp_nvram_create_free_partition(&image[sysp_end], 0x1fd0 - sysp_end); 130 131 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80); 132 133 for (i = 0; i < sizeof(image); i++) { 134 (k->write)(nvram, i, image[i]); 135 } 136 137 return 0; 138 } 139 140 static uint64_t sun4u_load_kernel(const char *kernel_filename, 141 const char *initrd_filename, 142 ram_addr_t RAM_size, uint64_t *initrd_size, 143 uint64_t *initrd_addr, uint64_t *kernel_addr, 144 uint64_t *kernel_entry) 145 { 146 int linux_boot; 147 unsigned int i; 148 long kernel_size; 149 uint8_t *ptr; 150 uint64_t kernel_top; 151 152 linux_boot = (kernel_filename != NULL); 153 154 kernel_size = 0; 155 if (linux_boot) { 156 int bswap_needed; 157 158 #ifdef BSWAP_NEEDED 159 bswap_needed = 1; 160 #else 161 bswap_needed = 0; 162 #endif 163 kernel_size = load_elf(kernel_filename, NULL, NULL, kernel_entry, 164 kernel_addr, &kernel_top, 1, EM_SPARCV9, 0, 0); 165 if (kernel_size < 0) { 166 *kernel_addr = KERNEL_LOAD_ADDR; 167 *kernel_entry = KERNEL_LOAD_ADDR; 168 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR, 169 RAM_size - KERNEL_LOAD_ADDR, bswap_needed, 170 TARGET_PAGE_SIZE); 171 } 172 if (kernel_size < 0) { 173 kernel_size = load_image_targphys(kernel_filename, 174 KERNEL_LOAD_ADDR, 175 RAM_size - KERNEL_LOAD_ADDR); 176 } 177 if (kernel_size < 0) { 178 fprintf(stderr, "qemu: could not load kernel '%s'\n", 179 kernel_filename); 180 exit(1); 181 } 182 /* load initrd above kernel */ 183 *initrd_size = 0; 184 if (initrd_filename) { 185 *initrd_addr = TARGET_PAGE_ALIGN(kernel_top); 186 187 *initrd_size = load_image_targphys(initrd_filename, 188 *initrd_addr, 189 RAM_size - *initrd_addr); 190 if ((int)*initrd_size < 0) { 191 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", 192 initrd_filename); 193 exit(1); 194 } 195 } 196 if (*initrd_size > 0) { 197 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { 198 ptr = rom_ptr(*kernel_addr + i); 199 if (ldl_p(ptr + 8) == 0x48647253) { /* HdrS */ 200 stl_p(ptr + 24, *initrd_addr + *kernel_addr); 201 stl_p(ptr + 28, *initrd_size); 202 break; 203 } 204 } 205 } 206 } 207 return kernel_size; 208 } 209 210 typedef struct ResetData { 211 SPARCCPU *cpu; 212 uint64_t prom_addr; 213 } ResetData; 214 215 static void ebus_isa_irq_handler(void *opaque, int n, int level) 216 { 217 EbusState *s = EBUS(opaque); 218 qemu_irq irq = s->isa_bus_irqs[n]; 219 220 /* Pass ISA bus IRQs onto their gpio equivalent */ 221 EBUS_DPRINTF("Set ISA IRQ %d level %d\n", n, level); 222 if (irq) { 223 qemu_set_irq(irq, level); 224 } 225 } 226 227 /* EBUS (Eight bit bus) bridge */ 228 static void ebus_realize(PCIDevice *pci_dev, Error **errp) 229 { 230 EbusState *s = EBUS(pci_dev); 231 DeviceState *dev; 232 qemu_irq *isa_irq; 233 DriveInfo *fd[MAX_FD]; 234 int i; 235 236 s->isa_bus = isa_bus_new(DEVICE(pci_dev), get_system_memory(), 237 pci_address_space_io(pci_dev), errp); 238 if (!s->isa_bus) { 239 error_setg(errp, "unable to instantiate EBUS ISA bus"); 240 return; 241 } 242 243 /* ISA bus */ 244 isa_irq = qemu_allocate_irqs(ebus_isa_irq_handler, s, ISA_NUM_IRQS); 245 isa_bus_irqs(s->isa_bus, isa_irq); 246 qdev_init_gpio_out_named(DEVICE(s), s->isa_bus_irqs, "isa-irq", 247 ISA_NUM_IRQS); 248 249 /* Serial ports */ 250 i = 0; 251 if (s->console_serial_base) { 252 serial_mm_init(pci_address_space(pci_dev), s->console_serial_base, 253 0, NULL, 115200, serial_hds[i], DEVICE_BIG_ENDIAN); 254 i++; 255 } 256 serial_hds_isa_init(s->isa_bus, i, MAX_SERIAL_PORTS); 257 258 /* Parallel ports */ 259 parallel_hds_isa_init(s->isa_bus, MAX_PARALLEL_PORTS); 260 261 /* Keyboard */ 262 isa_create_simple(s->isa_bus, "i8042"); 263 264 /* Floppy */ 265 for (i = 0; i < MAX_FD; i++) { 266 fd[i] = drive_get(IF_FLOPPY, 0, i); 267 } 268 dev = DEVICE(isa_create(s->isa_bus, TYPE_ISA_FDC)); 269 if (fd[0]) { 270 qdev_prop_set_drive(dev, "driveA", blk_by_legacy_dinfo(fd[0]), 271 &error_abort); 272 } 273 if (fd[1]) { 274 qdev_prop_set_drive(dev, "driveB", blk_by_legacy_dinfo(fd[1]), 275 &error_abort); 276 } 277 qdev_prop_set_uint32(dev, "dma", -1); 278 qdev_init_nofail(dev); 279 280 /* PCI */ 281 pci_dev->config[0x04] = 0x06; // command = bus master, pci mem 282 pci_dev->config[0x05] = 0x00; 283 pci_dev->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error 284 pci_dev->config[0x07] = 0x03; // status = medium devsel 285 pci_dev->config[0x09] = 0x00; // programming i/f 286 pci_dev->config[0x0D] = 0x0a; // latency_timer 287 288 memory_region_init_alias(&s->bar0, OBJECT(s), "bar0", get_system_io(), 289 0, 0x1000000); 290 pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0); 291 memory_region_init_alias(&s->bar1, OBJECT(s), "bar1", get_system_io(), 292 0, 0x4000); 293 pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->bar1); 294 } 295 296 static Property ebus_properties[] = { 297 DEFINE_PROP_UINT64("console-serial-base", EbusState, 298 console_serial_base, 0), 299 DEFINE_PROP_END_OF_LIST(), 300 }; 301 302 static void ebus_class_init(ObjectClass *klass, void *data) 303 { 304 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 305 DeviceClass *dc = DEVICE_CLASS(klass); 306 307 k->realize = ebus_realize; 308 k->vendor_id = PCI_VENDOR_ID_SUN; 309 k->device_id = PCI_DEVICE_ID_SUN_EBUS; 310 k->revision = 0x01; 311 k->class_id = PCI_CLASS_BRIDGE_OTHER; 312 dc->props = ebus_properties; 313 } 314 315 static const TypeInfo ebus_info = { 316 .name = TYPE_EBUS, 317 .parent = TYPE_PCI_DEVICE, 318 .class_init = ebus_class_init, 319 .instance_size = sizeof(EbusState), 320 .interfaces = (InterfaceInfo[]) { 321 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 322 { }, 323 }, 324 }; 325 326 #define TYPE_OPENPROM "openprom" 327 #define OPENPROM(obj) OBJECT_CHECK(PROMState, (obj), TYPE_OPENPROM) 328 329 typedef struct PROMState { 330 SysBusDevice parent_obj; 331 332 MemoryRegion prom; 333 } PROMState; 334 335 static uint64_t translate_prom_address(void *opaque, uint64_t addr) 336 { 337 hwaddr *base_addr = (hwaddr *)opaque; 338 return addr + *base_addr - PROM_VADDR; 339 } 340 341 /* Boot PROM (OpenBIOS) */ 342 static void prom_init(hwaddr addr, const char *bios_name) 343 { 344 DeviceState *dev; 345 SysBusDevice *s; 346 char *filename; 347 int ret; 348 349 dev = qdev_create(NULL, TYPE_OPENPROM); 350 qdev_init_nofail(dev); 351 s = SYS_BUS_DEVICE(dev); 352 353 sysbus_mmio_map(s, 0, addr); 354 355 /* load boot prom */ 356 if (bios_name == NULL) { 357 bios_name = PROM_FILENAME; 358 } 359 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 360 if (filename) { 361 ret = load_elf(filename, translate_prom_address, &addr, 362 NULL, NULL, NULL, 1, EM_SPARCV9, 0, 0); 363 if (ret < 0 || ret > PROM_SIZE_MAX) { 364 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX); 365 } 366 g_free(filename); 367 } else { 368 ret = -1; 369 } 370 if (ret < 0 || ret > PROM_SIZE_MAX) { 371 fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name); 372 exit(1); 373 } 374 } 375 376 static void prom_init1(Object *obj) 377 { 378 PROMState *s = OPENPROM(obj); 379 SysBusDevice *dev = SYS_BUS_DEVICE(obj); 380 381 memory_region_init_ram_nomigrate(&s->prom, obj, "sun4u.prom", PROM_SIZE_MAX, 382 &error_fatal); 383 vmstate_register_ram_global(&s->prom); 384 memory_region_set_readonly(&s->prom, true); 385 sysbus_init_mmio(dev, &s->prom); 386 } 387 388 static Property prom_properties[] = { 389 {/* end of property list */}, 390 }; 391 392 static void prom_class_init(ObjectClass *klass, void *data) 393 { 394 DeviceClass *dc = DEVICE_CLASS(klass); 395 396 dc->props = prom_properties; 397 } 398 399 static const TypeInfo prom_info = { 400 .name = TYPE_OPENPROM, 401 .parent = TYPE_SYS_BUS_DEVICE, 402 .instance_size = sizeof(PROMState), 403 .class_init = prom_class_init, 404 .instance_init = prom_init1, 405 }; 406 407 408 #define TYPE_SUN4U_MEMORY "memory" 409 #define SUN4U_RAM(obj) OBJECT_CHECK(RamDevice, (obj), TYPE_SUN4U_MEMORY) 410 411 typedef struct RamDevice { 412 SysBusDevice parent_obj; 413 414 MemoryRegion ram; 415 uint64_t size; 416 } RamDevice; 417 418 /* System RAM */ 419 static void ram_realize(DeviceState *dev, Error **errp) 420 { 421 RamDevice *d = SUN4U_RAM(dev); 422 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 423 424 memory_region_init_ram_nomigrate(&d->ram, OBJECT(d), "sun4u.ram", d->size, 425 &error_fatal); 426 vmstate_register_ram_global(&d->ram); 427 sysbus_init_mmio(sbd, &d->ram); 428 } 429 430 static void ram_init(hwaddr addr, ram_addr_t RAM_size) 431 { 432 DeviceState *dev; 433 SysBusDevice *s; 434 RamDevice *d; 435 436 /* allocate RAM */ 437 dev = qdev_create(NULL, TYPE_SUN4U_MEMORY); 438 s = SYS_BUS_DEVICE(dev); 439 440 d = SUN4U_RAM(dev); 441 d->size = RAM_size; 442 qdev_init_nofail(dev); 443 444 sysbus_mmio_map(s, 0, addr); 445 } 446 447 static Property ram_properties[] = { 448 DEFINE_PROP_UINT64("size", RamDevice, size, 0), 449 DEFINE_PROP_END_OF_LIST(), 450 }; 451 452 static void ram_class_init(ObjectClass *klass, void *data) 453 { 454 DeviceClass *dc = DEVICE_CLASS(klass); 455 456 dc->realize = ram_realize; 457 dc->props = ram_properties; 458 } 459 460 static const TypeInfo ram_info = { 461 .name = TYPE_SUN4U_MEMORY, 462 .parent = TYPE_SYS_BUS_DEVICE, 463 .instance_size = sizeof(RamDevice), 464 .class_init = ram_class_init, 465 }; 466 467 static void sun4uv_init(MemoryRegion *address_space_mem, 468 MachineState *machine, 469 const struct hwdef *hwdef) 470 { 471 SPARCCPU *cpu; 472 Nvram *nvram; 473 unsigned int i; 474 uint64_t initrd_addr, initrd_size, kernel_addr, kernel_size, kernel_entry; 475 APBState *apb; 476 PCIBus *pci_bus, *pci_busA, *pci_busB; 477 PCIDevice *ebus, *pci_dev; 478 SysBusDevice *s; 479 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; 480 DeviceState *dev; 481 FWCfgState *fw_cfg; 482 NICInfo *nd; 483 MACAddr macaddr; 484 bool onboard_nic; 485 486 /* init CPUs */ 487 cpu = sparc64_cpu_devinit(machine->cpu_type, hwdef->prom_addr); 488 489 /* set up devices */ 490 ram_init(0, machine->ram_size); 491 492 prom_init(hwdef->prom_addr, bios_name); 493 494 /* Init APB (PCI host bridge) */ 495 apb = APB_DEVICE(qdev_create(NULL, TYPE_APB)); 496 qdev_prop_set_uint64(DEVICE(apb), "special-base", APB_SPECIAL_BASE); 497 qdev_prop_set_uint64(DEVICE(apb), "mem-base", APB_MEM_BASE); 498 qdev_init_nofail(DEVICE(apb)); 499 500 /* Wire up PCI interrupts to CPU */ 501 for (i = 0; i < IVEC_MAX; i++) { 502 qdev_connect_gpio_out_named(DEVICE(apb), "ivec-irq", i, 503 qdev_get_gpio_in_named(DEVICE(cpu), "ivec-irq", i)); 504 } 505 506 pci_bus = PCI_HOST_BRIDGE(apb)->bus; 507 pci_busA = pci_bridge_get_sec_bus(apb->bridgeA); 508 pci_busB = pci_bridge_get_sec_bus(apb->bridgeB); 509 510 /* Only in-built Simba PBMs can exist on the root bus, slot 0 on busA is 511 reserved (leaving no slots free after on-board devices) however slots 512 0-3 are free on busB */ 513 pci_bus->slot_reserved_mask = 0xfffffffc; 514 pci_busA->slot_reserved_mask = 0xfffffff1; 515 pci_busB->slot_reserved_mask = 0xfffffff0; 516 517 ebus = pci_create_multifunction(pci_busA, PCI_DEVFN(1, 0), true, TYPE_EBUS); 518 qdev_prop_set_uint64(DEVICE(ebus), "console-serial-base", 519 hwdef->console_serial_base); 520 qdev_init_nofail(DEVICE(ebus)); 521 522 /* Wire up "well-known" ISA IRQs to APB legacy obio IRQs */ 523 qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 7, 524 qdev_get_gpio_in_named(DEVICE(apb), "pbm-irq", OBIO_LPT_IRQ)); 525 qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 6, 526 qdev_get_gpio_in_named(DEVICE(apb), "pbm-irq", OBIO_FDD_IRQ)); 527 qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 1, 528 qdev_get_gpio_in_named(DEVICE(apb), "pbm-irq", OBIO_KBD_IRQ)); 529 qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 12, 530 qdev_get_gpio_in_named(DEVICE(apb), "pbm-irq", OBIO_MSE_IRQ)); 531 qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 4, 532 qdev_get_gpio_in_named(DEVICE(apb), "pbm-irq", OBIO_SER_IRQ)); 533 534 pci_dev = pci_create_simple(pci_busA, PCI_DEVFN(2, 0), "VGA"); 535 536 memset(&macaddr, 0, sizeof(MACAddr)); 537 onboard_nic = false; 538 for (i = 0; i < nb_nics; i++) { 539 nd = &nd_table[i]; 540 541 if (!nd->model || strcmp(nd->model, "sunhme") == 0) { 542 if (!onboard_nic) { 543 pci_dev = pci_create_multifunction(pci_busA, PCI_DEVFN(1, 1), 544 true, "sunhme"); 545 memcpy(&macaddr, &nd->macaddr.a, sizeof(MACAddr)); 546 onboard_nic = true; 547 } else { 548 pci_dev = pci_create(pci_busB, -1, "sunhme"); 549 } 550 } else { 551 pci_dev = pci_create(pci_busB, -1, nd->model); 552 } 553 554 dev = &pci_dev->qdev; 555 qdev_set_nic_properties(dev, nd); 556 qdev_init_nofail(dev); 557 } 558 559 /* If we don't have an onboard NIC, grab a default MAC address so that 560 * we have a valid machine id */ 561 if (!onboard_nic) { 562 qemu_macaddr_default_if_unset(&macaddr); 563 } 564 565 ide_drive_get(hd, ARRAY_SIZE(hd)); 566 567 pci_dev = pci_create(pci_busA, PCI_DEVFN(3, 0), "cmd646-ide"); 568 qdev_prop_set_uint32(&pci_dev->qdev, "secondary", 1); 569 qdev_init_nofail(&pci_dev->qdev); 570 pci_ide_create_devs(pci_dev, hd); 571 572 /* Map NVRAM into I/O (ebus) space */ 573 nvram = m48t59_init(NULL, 0, 0, NVRAM_SIZE, 1968, 59); 574 s = SYS_BUS_DEVICE(nvram); 575 memory_region_add_subregion(pci_address_space_io(ebus), 0x2000, 576 sysbus_mmio_get_region(s, 0)); 577 578 initrd_size = 0; 579 initrd_addr = 0; 580 kernel_size = sun4u_load_kernel(machine->kernel_filename, 581 machine->initrd_filename, 582 ram_size, &initrd_size, &initrd_addr, 583 &kernel_addr, &kernel_entry); 584 585 sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", machine->ram_size, 586 machine->boot_order, 587 kernel_addr, kernel_size, 588 machine->kernel_cmdline, 589 initrd_addr, initrd_size, 590 /* XXX: need an option to load a NVRAM image */ 591 0, 592 graphic_width, graphic_height, graphic_depth, 593 (uint8_t *)&macaddr); 594 595 dev = qdev_create(NULL, TYPE_FW_CFG_IO); 596 qdev_prop_set_bit(dev, "dma_enabled", false); 597 object_property_add_child(OBJECT(ebus), TYPE_FW_CFG, OBJECT(dev), NULL); 598 qdev_init_nofail(dev); 599 memory_region_add_subregion(pci_address_space_io(ebus), BIOS_CFG_IOPORT, 600 &FW_CFG_IO(dev)->comb_iomem); 601 602 fw_cfg = FW_CFG(dev); 603 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus); 604 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus); 605 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 606 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); 607 fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_entry); 608 fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 609 if (machine->kernel_cmdline) { 610 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 611 strlen(machine->kernel_cmdline) + 1); 612 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline); 613 } else { 614 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0); 615 } 616 fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); 617 fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 618 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]); 619 620 fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_WIDTH, graphic_width); 621 fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_HEIGHT, graphic_height); 622 fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_DEPTH, graphic_depth); 623 624 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); 625 } 626 627 enum { 628 sun4u_id = 0, 629 sun4v_id = 64, 630 }; 631 632 static const struct hwdef hwdefs[] = { 633 /* Sun4u generic PC-like machine */ 634 { 635 .machine_id = sun4u_id, 636 .prom_addr = 0x1fff0000000ULL, 637 .console_serial_base = 0, 638 }, 639 /* Sun4v generic PC-like machine */ 640 { 641 .machine_id = sun4v_id, 642 .prom_addr = 0x1fff0000000ULL, 643 .console_serial_base = 0, 644 }, 645 }; 646 647 /* Sun4u hardware initialisation */ 648 static void sun4u_init(MachineState *machine) 649 { 650 sun4uv_init(get_system_memory(), machine, &hwdefs[0]); 651 } 652 653 /* Sun4v hardware initialisation */ 654 static void sun4v_init(MachineState *machine) 655 { 656 sun4uv_init(get_system_memory(), machine, &hwdefs[1]); 657 } 658 659 static void sun4u_class_init(ObjectClass *oc, void *data) 660 { 661 MachineClass *mc = MACHINE_CLASS(oc); 662 663 mc->desc = "Sun4u platform"; 664 mc->init = sun4u_init; 665 mc->block_default_type = IF_IDE; 666 mc->max_cpus = 1; /* XXX for now */ 667 mc->is_default = 1; 668 mc->default_boot_order = "c"; 669 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-UltraSparc-IIi"); 670 } 671 672 static const TypeInfo sun4u_type = { 673 .name = MACHINE_TYPE_NAME("sun4u"), 674 .parent = TYPE_MACHINE, 675 .class_init = sun4u_class_init, 676 }; 677 678 static void sun4v_class_init(ObjectClass *oc, void *data) 679 { 680 MachineClass *mc = MACHINE_CLASS(oc); 681 682 mc->desc = "Sun4v platform"; 683 mc->init = sun4v_init; 684 mc->block_default_type = IF_IDE; 685 mc->max_cpus = 1; /* XXX for now */ 686 mc->default_boot_order = "c"; 687 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Sun-UltraSparc-T1"); 688 } 689 690 static const TypeInfo sun4v_type = { 691 .name = MACHINE_TYPE_NAME("sun4v"), 692 .parent = TYPE_MACHINE, 693 .class_init = sun4v_class_init, 694 }; 695 696 static void sun4u_register_types(void) 697 { 698 type_register_static(&ebus_info); 699 type_register_static(&prom_info); 700 type_register_static(&ram_info); 701 702 type_register_static(&sun4u_type); 703 type_register_static(&sun4v_type); 704 } 705 706 type_init(sun4u_register_types) 707