1 /* 2 * QEMU Sun4u/Sun4v System Emulator 3 * 4 * Copyright (c) 2005 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "qemu/osdep.h" 25 #include "qapi/error.h" 26 #include "qemu-common.h" 27 #include "cpu.h" 28 #include "hw/hw.h" 29 #include "hw/pci/pci.h" 30 #include "hw/pci-host/apb.h" 31 #include "hw/i386/pc.h" 32 #include "hw/char/serial.h" 33 #include "hw/timer/m48t59.h" 34 #include "hw/block/fdc.h" 35 #include "net/net.h" 36 #include "qemu/timer.h" 37 #include "sysemu/sysemu.h" 38 #include "hw/boards.h" 39 #include "hw/nvram/openbios_firmware_abi.h" 40 #include "hw/nvram/fw_cfg.h" 41 #include "hw/sysbus.h" 42 #include "hw/ide.h" 43 #include "hw/loader.h" 44 #include "elf.h" 45 #include "sysemu/block-backend.h" 46 #include "exec/address-spaces.h" 47 48 //#define DEBUG_IRQ 49 //#define DEBUG_EBUS 50 //#define DEBUG_TIMER 51 52 #ifdef DEBUG_IRQ 53 #define CPUIRQ_DPRINTF(fmt, ...) \ 54 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0) 55 #else 56 #define CPUIRQ_DPRINTF(fmt, ...) 57 #endif 58 59 #ifdef DEBUG_EBUS 60 #define EBUS_DPRINTF(fmt, ...) \ 61 do { printf("EBUS: " fmt , ## __VA_ARGS__); } while (0) 62 #else 63 #define EBUS_DPRINTF(fmt, ...) 64 #endif 65 66 #ifdef DEBUG_TIMER 67 #define TIMER_DPRINTF(fmt, ...) \ 68 do { printf("TIMER: " fmt , ## __VA_ARGS__); } while (0) 69 #else 70 #define TIMER_DPRINTF(fmt, ...) 71 #endif 72 73 #define KERNEL_LOAD_ADDR 0x00404000 74 #define CMDLINE_ADDR 0x003ff000 75 #define PROM_SIZE_MAX (4 * 1024 * 1024) 76 #define PROM_VADDR 0x000ffd00000ULL 77 #define APB_SPECIAL_BASE 0x1fe00000000ULL 78 #define APB_MEM_BASE 0x1ff00000000ULL 79 #define APB_PCI_IO_BASE (APB_SPECIAL_BASE + 0x02000000ULL) 80 #define PROM_FILENAME "openbios-sparc64" 81 #define NVRAM_SIZE 0x2000 82 #define MAX_IDE_BUS 2 83 #define BIOS_CFG_IOPORT 0x510 84 #define FW_CFG_SPARC64_WIDTH (FW_CFG_ARCH_LOCAL + 0x00) 85 #define FW_CFG_SPARC64_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01) 86 #define FW_CFG_SPARC64_DEPTH (FW_CFG_ARCH_LOCAL + 0x02) 87 88 #define IVEC_MAX 0x40 89 90 #define TICK_MAX 0x7fffffffffffffffULL 91 92 struct hwdef { 93 const char * const default_cpu_model; 94 uint16_t machine_id; 95 uint64_t prom_addr; 96 uint64_t console_serial_base; 97 }; 98 99 typedef struct EbusState { 100 PCIDevice pci_dev; 101 MemoryRegion bar0; 102 MemoryRegion bar1; 103 } EbusState; 104 105 void DMA_init(ISABus *bus, int high_page_enable) 106 { 107 } 108 109 static void fw_cfg_boot_set(void *opaque, const char *boot_device, 110 Error **errp) 111 { 112 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); 113 } 114 115 static int sun4u_NVRAM_set_params(Nvram *nvram, uint16_t NVRAM_size, 116 const char *arch, ram_addr_t RAM_size, 117 const char *boot_devices, 118 uint32_t kernel_image, uint32_t kernel_size, 119 const char *cmdline, 120 uint32_t initrd_image, uint32_t initrd_size, 121 uint32_t NVRAM_image, 122 int width, int height, int depth, 123 const uint8_t *macaddr) 124 { 125 unsigned int i; 126 uint32_t start, end; 127 uint8_t image[0x1ff0]; 128 struct OpenBIOS_nvpart_v1 *part_header; 129 NvramClass *k = NVRAM_GET_CLASS(nvram); 130 131 memset(image, '\0', sizeof(image)); 132 133 start = 0; 134 135 // OpenBIOS nvram variables 136 // Variable partition 137 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start]; 138 part_header->signature = OPENBIOS_PART_SYSTEM; 139 pstrcpy(part_header->name, sizeof(part_header->name), "system"); 140 141 end = start + sizeof(struct OpenBIOS_nvpart_v1); 142 for (i = 0; i < nb_prom_envs; i++) 143 end = OpenBIOS_set_var(image, end, prom_envs[i]); 144 145 // End marker 146 image[end++] = '\0'; 147 148 end = start + ((end - start + 15) & ~15); 149 OpenBIOS_finish_partition(part_header, end - start); 150 151 // free partition 152 start = end; 153 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start]; 154 part_header->signature = OPENBIOS_PART_FREE; 155 pstrcpy(part_header->name, sizeof(part_header->name), "free"); 156 157 end = 0x1fd0; 158 OpenBIOS_finish_partition(part_header, end - start); 159 160 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80); 161 162 for (i = 0; i < sizeof(image); i++) { 163 (k->write)(nvram, i, image[i]); 164 } 165 166 return 0; 167 } 168 169 static uint64_t sun4u_load_kernel(const char *kernel_filename, 170 const char *initrd_filename, 171 ram_addr_t RAM_size, uint64_t *initrd_size, 172 uint64_t *initrd_addr, uint64_t *kernel_addr, 173 uint64_t *kernel_entry) 174 { 175 int linux_boot; 176 unsigned int i; 177 long kernel_size; 178 uint8_t *ptr; 179 uint64_t kernel_top; 180 181 linux_boot = (kernel_filename != NULL); 182 183 kernel_size = 0; 184 if (linux_boot) { 185 int bswap_needed; 186 187 #ifdef BSWAP_NEEDED 188 bswap_needed = 1; 189 #else 190 bswap_needed = 0; 191 #endif 192 kernel_size = load_elf(kernel_filename, NULL, NULL, kernel_entry, 193 kernel_addr, &kernel_top, 1, EM_SPARCV9, 0, 0); 194 if (kernel_size < 0) { 195 *kernel_addr = KERNEL_LOAD_ADDR; 196 *kernel_entry = KERNEL_LOAD_ADDR; 197 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR, 198 RAM_size - KERNEL_LOAD_ADDR, bswap_needed, 199 TARGET_PAGE_SIZE); 200 } 201 if (kernel_size < 0) { 202 kernel_size = load_image_targphys(kernel_filename, 203 KERNEL_LOAD_ADDR, 204 RAM_size - KERNEL_LOAD_ADDR); 205 } 206 if (kernel_size < 0) { 207 fprintf(stderr, "qemu: could not load kernel '%s'\n", 208 kernel_filename); 209 exit(1); 210 } 211 /* load initrd above kernel */ 212 *initrd_size = 0; 213 if (initrd_filename) { 214 *initrd_addr = TARGET_PAGE_ALIGN(kernel_top); 215 216 *initrd_size = load_image_targphys(initrd_filename, 217 *initrd_addr, 218 RAM_size - *initrd_addr); 219 if ((int)*initrd_size < 0) { 220 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", 221 initrd_filename); 222 exit(1); 223 } 224 } 225 if (*initrd_size > 0) { 226 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { 227 ptr = rom_ptr(*kernel_addr + i); 228 if (ldl_p(ptr + 8) == 0x48647253) { /* HdrS */ 229 stl_p(ptr + 24, *initrd_addr + *kernel_addr); 230 stl_p(ptr + 28, *initrd_size); 231 break; 232 } 233 } 234 } 235 } 236 return kernel_size; 237 } 238 239 void cpu_check_irqs(CPUSPARCState *env) 240 { 241 CPUState *cs; 242 uint32_t pil = env->pil_in | 243 (env->softint & ~(SOFTINT_TIMER | SOFTINT_STIMER)); 244 245 /* TT_IVEC has a higher priority (16) than TT_EXTINT (31..17) */ 246 if (env->ivec_status & 0x20) { 247 return; 248 } 249 cs = CPU(sparc_env_get_cpu(env)); 250 /* check if TM or SM in SOFTINT are set 251 setting these also causes interrupt 14 */ 252 if (env->softint & (SOFTINT_TIMER | SOFTINT_STIMER)) { 253 pil |= 1 << 14; 254 } 255 256 /* The bit corresponding to psrpil is (1<< psrpil), the next bit 257 is (2 << psrpil). */ 258 if (pil < (2 << env->psrpil)){ 259 if (cs->interrupt_request & CPU_INTERRUPT_HARD) { 260 CPUIRQ_DPRINTF("Reset CPU IRQ (current interrupt %x)\n", 261 env->interrupt_index); 262 env->interrupt_index = 0; 263 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 264 } 265 return; 266 } 267 268 if (cpu_interrupts_enabled(env)) { 269 270 unsigned int i; 271 272 for (i = 15; i > env->psrpil; i--) { 273 if (pil & (1 << i)) { 274 int old_interrupt = env->interrupt_index; 275 int new_interrupt = TT_EXTINT | i; 276 277 if (unlikely(env->tl > 0 && cpu_tsptr(env)->tt > new_interrupt 278 && ((cpu_tsptr(env)->tt & 0x1f0) == TT_EXTINT))) { 279 CPUIRQ_DPRINTF("Not setting CPU IRQ: TL=%d " 280 "current %x >= pending %x\n", 281 env->tl, cpu_tsptr(env)->tt, new_interrupt); 282 } else if (old_interrupt != new_interrupt) { 283 env->interrupt_index = new_interrupt; 284 CPUIRQ_DPRINTF("Set CPU IRQ %d old=%x new=%x\n", i, 285 old_interrupt, new_interrupt); 286 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 287 } 288 break; 289 } 290 } 291 } else if (cs->interrupt_request & CPU_INTERRUPT_HARD) { 292 CPUIRQ_DPRINTF("Interrupts disabled, pil=%08x pil_in=%08x softint=%08x " 293 "current interrupt %x\n", 294 pil, env->pil_in, env->softint, env->interrupt_index); 295 env->interrupt_index = 0; 296 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 297 } 298 } 299 300 static void cpu_kick_irq(SPARCCPU *cpu) 301 { 302 CPUState *cs = CPU(cpu); 303 CPUSPARCState *env = &cpu->env; 304 305 cs->halted = 0; 306 cpu_check_irqs(env); 307 qemu_cpu_kick(cs); 308 } 309 310 static void cpu_set_ivec_irq(void *opaque, int irq, int level) 311 { 312 SPARCCPU *cpu = opaque; 313 CPUSPARCState *env = &cpu->env; 314 CPUState *cs; 315 316 if (level) { 317 if (!(env->ivec_status & 0x20)) { 318 CPUIRQ_DPRINTF("Raise IVEC IRQ %d\n", irq); 319 cs = CPU(cpu); 320 cs->halted = 0; 321 env->interrupt_index = TT_IVEC; 322 env->ivec_status |= 0x20; 323 env->ivec_data[0] = (0x1f << 6) | irq; 324 env->ivec_data[1] = 0; 325 env->ivec_data[2] = 0; 326 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 327 } 328 } else { 329 if (env->ivec_status & 0x20) { 330 CPUIRQ_DPRINTF("Lower IVEC IRQ %d\n", irq); 331 cs = CPU(cpu); 332 env->ivec_status &= ~0x20; 333 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 334 } 335 } 336 } 337 338 typedef struct ResetData { 339 SPARCCPU *cpu; 340 uint64_t prom_addr; 341 } ResetData; 342 343 static CPUTimer *cpu_timer_create(const char *name, SPARCCPU *cpu, 344 QEMUBHFunc *cb, uint32_t frequency, 345 uint64_t disabled_mask, uint64_t npt_mask) 346 { 347 CPUTimer *timer = g_malloc0(sizeof (CPUTimer)); 348 349 timer->name = name; 350 timer->frequency = frequency; 351 timer->disabled_mask = disabled_mask; 352 timer->npt_mask = npt_mask; 353 354 timer->disabled = 1; 355 timer->npt = 1; 356 timer->clock_offset = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 357 358 timer->qtimer = timer_new_ns(QEMU_CLOCK_VIRTUAL, cb, cpu); 359 360 return timer; 361 } 362 363 static void cpu_timer_reset(CPUTimer *timer) 364 { 365 timer->disabled = 1; 366 timer->clock_offset = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 367 368 timer_del(timer->qtimer); 369 } 370 371 static void main_cpu_reset(void *opaque) 372 { 373 ResetData *s = (ResetData *)opaque; 374 CPUSPARCState *env = &s->cpu->env; 375 static unsigned int nr_resets; 376 377 cpu_reset(CPU(s->cpu)); 378 379 cpu_timer_reset(env->tick); 380 cpu_timer_reset(env->stick); 381 cpu_timer_reset(env->hstick); 382 383 env->gregs[1] = 0; // Memory start 384 env->gregs[2] = ram_size; // Memory size 385 env->gregs[3] = 0; // Machine description XXX 386 if (nr_resets++ == 0) { 387 /* Power on reset */ 388 env->pc = s->prom_addr + 0x20ULL; 389 } else { 390 env->pc = s->prom_addr + 0x40ULL; 391 } 392 env->npc = env->pc + 4; 393 } 394 395 static void tick_irq(void *opaque) 396 { 397 SPARCCPU *cpu = opaque; 398 CPUSPARCState *env = &cpu->env; 399 400 CPUTimer* timer = env->tick; 401 402 if (timer->disabled) { 403 CPUIRQ_DPRINTF("tick_irq: softint disabled\n"); 404 return; 405 } else { 406 CPUIRQ_DPRINTF("tick: fire\n"); 407 } 408 409 env->softint |= SOFTINT_TIMER; 410 cpu_kick_irq(cpu); 411 } 412 413 static void stick_irq(void *opaque) 414 { 415 SPARCCPU *cpu = opaque; 416 CPUSPARCState *env = &cpu->env; 417 418 CPUTimer* timer = env->stick; 419 420 if (timer->disabled) { 421 CPUIRQ_DPRINTF("stick_irq: softint disabled\n"); 422 return; 423 } else { 424 CPUIRQ_DPRINTF("stick: fire\n"); 425 } 426 427 env->softint |= SOFTINT_STIMER; 428 cpu_kick_irq(cpu); 429 } 430 431 static void hstick_irq(void *opaque) 432 { 433 SPARCCPU *cpu = opaque; 434 CPUSPARCState *env = &cpu->env; 435 436 CPUTimer* timer = env->hstick; 437 438 if (timer->disabled) { 439 CPUIRQ_DPRINTF("hstick_irq: softint disabled\n"); 440 return; 441 } else { 442 CPUIRQ_DPRINTF("hstick: fire\n"); 443 } 444 445 env->softint |= SOFTINT_STIMER; 446 cpu_kick_irq(cpu); 447 } 448 449 static int64_t cpu_to_timer_ticks(int64_t cpu_ticks, uint32_t frequency) 450 { 451 return muldiv64(cpu_ticks, get_ticks_per_sec(), frequency); 452 } 453 454 static uint64_t timer_to_cpu_ticks(int64_t timer_ticks, uint32_t frequency) 455 { 456 return muldiv64(timer_ticks, frequency, get_ticks_per_sec()); 457 } 458 459 void cpu_tick_set_count(CPUTimer *timer, uint64_t count) 460 { 461 uint64_t real_count = count & ~timer->npt_mask; 462 uint64_t npt_bit = count & timer->npt_mask; 463 464 int64_t vm_clock_offset = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - 465 cpu_to_timer_ticks(real_count, timer->frequency); 466 467 TIMER_DPRINTF("%s set_count count=0x%016lx (npt %s) p=%p\n", 468 timer->name, real_count, 469 timer->npt ? "disabled" : "enabled", timer); 470 471 timer->npt = npt_bit ? 1 : 0; 472 timer->clock_offset = vm_clock_offset; 473 } 474 475 uint64_t cpu_tick_get_count(CPUTimer *timer) 476 { 477 uint64_t real_count = timer_to_cpu_ticks( 478 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - timer->clock_offset, 479 timer->frequency); 480 481 TIMER_DPRINTF("%s get_count count=0x%016lx (npt %s) p=%p\n", 482 timer->name, real_count, 483 timer->npt ? "disabled" : "enabled", timer); 484 485 if (timer->npt) { 486 real_count |= timer->npt_mask; 487 } 488 489 return real_count; 490 } 491 492 void cpu_tick_set_limit(CPUTimer *timer, uint64_t limit) 493 { 494 int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 495 496 uint64_t real_limit = limit & ~timer->disabled_mask; 497 timer->disabled = (limit & timer->disabled_mask) ? 1 : 0; 498 499 int64_t expires = cpu_to_timer_ticks(real_limit, timer->frequency) + 500 timer->clock_offset; 501 502 if (expires < now) { 503 expires = now + 1; 504 } 505 506 TIMER_DPRINTF("%s set_limit limit=0x%016lx (%s) p=%p " 507 "called with limit=0x%016lx at 0x%016lx (delta=0x%016lx)\n", 508 timer->name, real_limit, 509 timer->disabled?"disabled":"enabled", 510 timer, limit, 511 timer_to_cpu_ticks(now - timer->clock_offset, 512 timer->frequency), 513 timer_to_cpu_ticks(expires - now, timer->frequency)); 514 515 if (!real_limit) { 516 TIMER_DPRINTF("%s set_limit limit=ZERO - not starting timer\n", 517 timer->name); 518 timer_del(timer->qtimer); 519 } else if (timer->disabled) { 520 timer_del(timer->qtimer); 521 } else { 522 timer_mod(timer->qtimer, expires); 523 } 524 } 525 526 static void isa_irq_handler(void *opaque, int n, int level) 527 { 528 static const int isa_irq_to_ivec[16] = { 529 [1] = 0x29, /* keyboard */ 530 [4] = 0x2b, /* serial */ 531 [6] = 0x27, /* floppy */ 532 [7] = 0x22, /* parallel */ 533 [12] = 0x2a, /* mouse */ 534 }; 535 qemu_irq *irqs = opaque; 536 int ivec; 537 538 assert(n < 16); 539 ivec = isa_irq_to_ivec[n]; 540 EBUS_DPRINTF("Set ISA IRQ %d level %d -> ivec 0x%x\n", n, level, ivec); 541 if (ivec) { 542 qemu_set_irq(irqs[ivec], level); 543 } 544 } 545 546 /* EBUS (Eight bit bus) bridge */ 547 static ISABus * 548 pci_ebus_init(PCIBus *bus, int devfn, qemu_irq *irqs) 549 { 550 qemu_irq *isa_irq; 551 PCIDevice *pci_dev; 552 ISABus *isa_bus; 553 554 pci_dev = pci_create_simple(bus, devfn, "ebus"); 555 isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(pci_dev), "isa.0")); 556 isa_irq = qemu_allocate_irqs(isa_irq_handler, irqs, 16); 557 isa_bus_irqs(isa_bus, isa_irq); 558 return isa_bus; 559 } 560 561 static void pci_ebus_realize(PCIDevice *pci_dev, Error **errp) 562 { 563 EbusState *s = DO_UPCAST(EbusState, pci_dev, pci_dev); 564 565 if (!isa_bus_new(DEVICE(pci_dev), get_system_memory(), 566 pci_address_space_io(pci_dev), errp)) { 567 return; 568 } 569 570 pci_dev->config[0x04] = 0x06; // command = bus master, pci mem 571 pci_dev->config[0x05] = 0x00; 572 pci_dev->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error 573 pci_dev->config[0x07] = 0x03; // status = medium devsel 574 pci_dev->config[0x09] = 0x00; // programming i/f 575 pci_dev->config[0x0D] = 0x0a; // latency_timer 576 577 memory_region_init_alias(&s->bar0, OBJECT(s), "bar0", get_system_io(), 578 0, 0x1000000); 579 pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0); 580 memory_region_init_alias(&s->bar1, OBJECT(s), "bar1", get_system_io(), 581 0, 0x4000); 582 pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->bar1); 583 } 584 585 static void ebus_class_init(ObjectClass *klass, void *data) 586 { 587 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 588 589 k->realize = pci_ebus_realize; 590 k->vendor_id = PCI_VENDOR_ID_SUN; 591 k->device_id = PCI_DEVICE_ID_SUN_EBUS; 592 k->revision = 0x01; 593 k->class_id = PCI_CLASS_BRIDGE_OTHER; 594 } 595 596 static const TypeInfo ebus_info = { 597 .name = "ebus", 598 .parent = TYPE_PCI_DEVICE, 599 .instance_size = sizeof(EbusState), 600 .class_init = ebus_class_init, 601 }; 602 603 #define TYPE_OPENPROM "openprom" 604 #define OPENPROM(obj) OBJECT_CHECK(PROMState, (obj), TYPE_OPENPROM) 605 606 typedef struct PROMState { 607 SysBusDevice parent_obj; 608 609 MemoryRegion prom; 610 } PROMState; 611 612 static uint64_t translate_prom_address(void *opaque, uint64_t addr) 613 { 614 hwaddr *base_addr = (hwaddr *)opaque; 615 return addr + *base_addr - PROM_VADDR; 616 } 617 618 /* Boot PROM (OpenBIOS) */ 619 static void prom_init(hwaddr addr, const char *bios_name) 620 { 621 DeviceState *dev; 622 SysBusDevice *s; 623 char *filename; 624 int ret; 625 626 dev = qdev_create(NULL, TYPE_OPENPROM); 627 qdev_init_nofail(dev); 628 s = SYS_BUS_DEVICE(dev); 629 630 sysbus_mmio_map(s, 0, addr); 631 632 /* load boot prom */ 633 if (bios_name == NULL) { 634 bios_name = PROM_FILENAME; 635 } 636 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 637 if (filename) { 638 ret = load_elf(filename, translate_prom_address, &addr, 639 NULL, NULL, NULL, 1, EM_SPARCV9, 0, 0); 640 if (ret < 0 || ret > PROM_SIZE_MAX) { 641 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX); 642 } 643 g_free(filename); 644 } else { 645 ret = -1; 646 } 647 if (ret < 0 || ret > PROM_SIZE_MAX) { 648 fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name); 649 exit(1); 650 } 651 } 652 653 static int prom_init1(SysBusDevice *dev) 654 { 655 PROMState *s = OPENPROM(dev); 656 657 memory_region_init_ram(&s->prom, OBJECT(s), "sun4u.prom", PROM_SIZE_MAX, 658 &error_fatal); 659 vmstate_register_ram_global(&s->prom); 660 memory_region_set_readonly(&s->prom, true); 661 sysbus_init_mmio(dev, &s->prom); 662 return 0; 663 } 664 665 static Property prom_properties[] = { 666 {/* end of property list */}, 667 }; 668 669 static void prom_class_init(ObjectClass *klass, void *data) 670 { 671 DeviceClass *dc = DEVICE_CLASS(klass); 672 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 673 674 k->init = prom_init1; 675 dc->props = prom_properties; 676 } 677 678 static const TypeInfo prom_info = { 679 .name = TYPE_OPENPROM, 680 .parent = TYPE_SYS_BUS_DEVICE, 681 .instance_size = sizeof(PROMState), 682 .class_init = prom_class_init, 683 }; 684 685 686 #define TYPE_SUN4U_MEMORY "memory" 687 #define SUN4U_RAM(obj) OBJECT_CHECK(RamDevice, (obj), TYPE_SUN4U_MEMORY) 688 689 typedef struct RamDevice { 690 SysBusDevice parent_obj; 691 692 MemoryRegion ram; 693 uint64_t size; 694 } RamDevice; 695 696 /* System RAM */ 697 static int ram_init1(SysBusDevice *dev) 698 { 699 RamDevice *d = SUN4U_RAM(dev); 700 701 memory_region_init_ram(&d->ram, OBJECT(d), "sun4u.ram", d->size, 702 &error_fatal); 703 vmstate_register_ram_global(&d->ram); 704 sysbus_init_mmio(dev, &d->ram); 705 return 0; 706 } 707 708 static void ram_init(hwaddr addr, ram_addr_t RAM_size) 709 { 710 DeviceState *dev; 711 SysBusDevice *s; 712 RamDevice *d; 713 714 /* allocate RAM */ 715 dev = qdev_create(NULL, TYPE_SUN4U_MEMORY); 716 s = SYS_BUS_DEVICE(dev); 717 718 d = SUN4U_RAM(dev); 719 d->size = RAM_size; 720 qdev_init_nofail(dev); 721 722 sysbus_mmio_map(s, 0, addr); 723 } 724 725 static Property ram_properties[] = { 726 DEFINE_PROP_UINT64("size", RamDevice, size, 0), 727 DEFINE_PROP_END_OF_LIST(), 728 }; 729 730 static void ram_class_init(ObjectClass *klass, void *data) 731 { 732 DeviceClass *dc = DEVICE_CLASS(klass); 733 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 734 735 k->init = ram_init1; 736 dc->props = ram_properties; 737 } 738 739 static const TypeInfo ram_info = { 740 .name = TYPE_SUN4U_MEMORY, 741 .parent = TYPE_SYS_BUS_DEVICE, 742 .instance_size = sizeof(RamDevice), 743 .class_init = ram_class_init, 744 }; 745 746 static SPARCCPU *cpu_devinit(const char *cpu_model, const struct hwdef *hwdef) 747 { 748 SPARCCPU *cpu; 749 CPUSPARCState *env; 750 ResetData *reset_info; 751 752 uint32_t tick_frequency = 100*1000000; 753 uint32_t stick_frequency = 100*1000000; 754 uint32_t hstick_frequency = 100*1000000; 755 756 if (cpu_model == NULL) { 757 cpu_model = hwdef->default_cpu_model; 758 } 759 cpu = cpu_sparc_init(cpu_model); 760 if (cpu == NULL) { 761 fprintf(stderr, "Unable to find Sparc CPU definition\n"); 762 exit(1); 763 } 764 env = &cpu->env; 765 766 env->tick = cpu_timer_create("tick", cpu, tick_irq, 767 tick_frequency, TICK_INT_DIS, 768 TICK_NPT_MASK); 769 770 env->stick = cpu_timer_create("stick", cpu, stick_irq, 771 stick_frequency, TICK_INT_DIS, 772 TICK_NPT_MASK); 773 774 env->hstick = cpu_timer_create("hstick", cpu, hstick_irq, 775 hstick_frequency, TICK_INT_DIS, 776 TICK_NPT_MASK); 777 778 reset_info = g_malloc0(sizeof(ResetData)); 779 reset_info->cpu = cpu; 780 reset_info->prom_addr = hwdef->prom_addr; 781 qemu_register_reset(main_cpu_reset, reset_info); 782 783 return cpu; 784 } 785 786 static void sun4uv_init(MemoryRegion *address_space_mem, 787 MachineState *machine, 788 const struct hwdef *hwdef) 789 { 790 SPARCCPU *cpu; 791 Nvram *nvram; 792 unsigned int i; 793 uint64_t initrd_addr, initrd_size, kernel_addr, kernel_size, kernel_entry; 794 PCIBus *pci_bus, *pci_bus2, *pci_bus3; 795 ISABus *isa_bus; 796 SysBusDevice *s; 797 qemu_irq *ivec_irqs, *pbm_irqs; 798 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; 799 DriveInfo *fd[MAX_FD]; 800 DeviceState *dev; 801 FWCfgState *fw_cfg; 802 803 /* init CPUs */ 804 cpu = cpu_devinit(machine->cpu_model, hwdef); 805 806 /* set up devices */ 807 ram_init(0, machine->ram_size); 808 809 prom_init(hwdef->prom_addr, bios_name); 810 811 ivec_irqs = qemu_allocate_irqs(cpu_set_ivec_irq, cpu, IVEC_MAX); 812 pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, ivec_irqs, &pci_bus2, 813 &pci_bus3, &pbm_irqs); 814 pci_vga_init(pci_bus); 815 816 // XXX Should be pci_bus3 817 isa_bus = pci_ebus_init(pci_bus, -1, pbm_irqs); 818 819 i = 0; 820 if (hwdef->console_serial_base) { 821 serial_mm_init(address_space_mem, hwdef->console_serial_base, 0, 822 NULL, 115200, serial_hds[i], DEVICE_BIG_ENDIAN); 823 i++; 824 } 825 826 serial_hds_isa_init(isa_bus, MAX_SERIAL_PORTS); 827 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); 828 829 for(i = 0; i < nb_nics; i++) 830 pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL); 831 832 ide_drive_get(hd, ARRAY_SIZE(hd)); 833 834 pci_cmd646_ide_init(pci_bus, hd, 1); 835 836 isa_create_simple(isa_bus, "i8042"); 837 838 /* Floppy */ 839 for(i = 0; i < MAX_FD; i++) { 840 fd[i] = drive_get(IF_FLOPPY, 0, i); 841 } 842 dev = DEVICE(isa_create(isa_bus, TYPE_ISA_FDC)); 843 if (fd[0]) { 844 qdev_prop_set_drive(dev, "driveA", blk_by_legacy_dinfo(fd[0]), 845 &error_abort); 846 } 847 if (fd[1]) { 848 qdev_prop_set_drive(dev, "driveB", blk_by_legacy_dinfo(fd[1]), 849 &error_abort); 850 } 851 qdev_prop_set_uint32(dev, "dma", -1); 852 qdev_init_nofail(dev); 853 854 /* Map NVRAM into I/O (ebus) space */ 855 nvram = m48t59_init(NULL, 0, 0, NVRAM_SIZE, 1968, 59); 856 s = SYS_BUS_DEVICE(nvram); 857 memory_region_add_subregion(get_system_io(), 0x2000, 858 sysbus_mmio_get_region(s, 0)); 859 860 initrd_size = 0; 861 initrd_addr = 0; 862 kernel_size = sun4u_load_kernel(machine->kernel_filename, 863 machine->initrd_filename, 864 ram_size, &initrd_size, &initrd_addr, 865 &kernel_addr, &kernel_entry); 866 867 sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", machine->ram_size, 868 machine->boot_order, 869 kernel_addr, kernel_size, 870 machine->kernel_cmdline, 871 initrd_addr, initrd_size, 872 /* XXX: need an option to load a NVRAM image */ 873 0, 874 graphic_width, graphic_height, graphic_depth, 875 (uint8_t *)&nd_table[0].macaddr); 876 877 fw_cfg = fw_cfg_init_io(BIOS_CFG_IOPORT); 878 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus); 879 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 880 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); 881 fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_entry); 882 fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 883 if (machine->kernel_cmdline) { 884 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 885 strlen(machine->kernel_cmdline) + 1); 886 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline); 887 } else { 888 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0); 889 } 890 fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); 891 fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 892 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]); 893 894 fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_WIDTH, graphic_width); 895 fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_HEIGHT, graphic_height); 896 fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_DEPTH, graphic_depth); 897 898 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); 899 } 900 901 enum { 902 sun4u_id = 0, 903 sun4v_id = 64, 904 niagara_id, 905 }; 906 907 static const struct hwdef hwdefs[] = { 908 /* Sun4u generic PC-like machine */ 909 { 910 .default_cpu_model = "TI UltraSparc IIi", 911 .machine_id = sun4u_id, 912 .prom_addr = 0x1fff0000000ULL, 913 .console_serial_base = 0, 914 }, 915 /* Sun4v generic PC-like machine */ 916 { 917 .default_cpu_model = "Sun UltraSparc T1", 918 .machine_id = sun4v_id, 919 .prom_addr = 0x1fff0000000ULL, 920 .console_serial_base = 0, 921 }, 922 /* Sun4v generic Niagara machine */ 923 { 924 .default_cpu_model = "Sun UltraSparc T1", 925 .machine_id = niagara_id, 926 .prom_addr = 0xfff0000000ULL, 927 .console_serial_base = 0xfff0c2c000ULL, 928 }, 929 }; 930 931 /* Sun4u hardware initialisation */ 932 static void sun4u_init(MachineState *machine) 933 { 934 sun4uv_init(get_system_memory(), machine, &hwdefs[0]); 935 } 936 937 /* Sun4v hardware initialisation */ 938 static void sun4v_init(MachineState *machine) 939 { 940 sun4uv_init(get_system_memory(), machine, &hwdefs[1]); 941 } 942 943 /* Niagara hardware initialisation */ 944 static void niagara_init(MachineState *machine) 945 { 946 sun4uv_init(get_system_memory(), machine, &hwdefs[2]); 947 } 948 949 static void sun4u_class_init(ObjectClass *oc, void *data) 950 { 951 MachineClass *mc = MACHINE_CLASS(oc); 952 953 mc->desc = "Sun4u platform"; 954 mc->init = sun4u_init; 955 mc->max_cpus = 1; /* XXX for now */ 956 mc->is_default = 1; 957 mc->default_boot_order = "c"; 958 } 959 960 static const TypeInfo sun4u_type = { 961 .name = MACHINE_TYPE_NAME("sun4u"), 962 .parent = TYPE_MACHINE, 963 .class_init = sun4u_class_init, 964 }; 965 966 static void sun4v_class_init(ObjectClass *oc, void *data) 967 { 968 MachineClass *mc = MACHINE_CLASS(oc); 969 970 mc->desc = "Sun4v platform"; 971 mc->init = sun4v_init; 972 mc->max_cpus = 1; /* XXX for now */ 973 mc->default_boot_order = "c"; 974 } 975 976 static const TypeInfo sun4v_type = { 977 .name = MACHINE_TYPE_NAME("sun4v"), 978 .parent = TYPE_MACHINE, 979 .class_init = sun4v_class_init, 980 }; 981 982 static void niagara_class_init(ObjectClass *oc, void *data) 983 { 984 MachineClass *mc = MACHINE_CLASS(oc); 985 986 mc->desc = "Sun4v platform, Niagara"; 987 mc->init = niagara_init; 988 mc->max_cpus = 1; /* XXX for now */ 989 mc->default_boot_order = "c"; 990 } 991 992 static const TypeInfo niagara_type = { 993 .name = MACHINE_TYPE_NAME("Niagara"), 994 .parent = TYPE_MACHINE, 995 .class_init = niagara_class_init, 996 }; 997 998 static void sun4u_register_types(void) 999 { 1000 type_register_static(&ebus_info); 1001 type_register_static(&prom_info); 1002 type_register_static(&ram_info); 1003 1004 type_register_static(&sun4u_type); 1005 type_register_static(&sun4v_type); 1006 type_register_static(&niagara_type); 1007 } 1008 1009 type_init(sun4u_register_types) 1010