1 /* 2 * QEMU Sun4u/Sun4v System Emulator 3 * 4 * Copyright (c) 2005 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "qemu/osdep.h" 25 #include "qapi/error.h" 26 #include "qemu-common.h" 27 #include "cpu.h" 28 #include "hw/hw.h" 29 #include "hw/pci/pci.h" 30 #include "hw/pci-host/apb.h" 31 #include "hw/i386/pc.h" 32 #include "hw/char/serial.h" 33 #include "hw/timer/m48t59.h" 34 #include "hw/block/fdc.h" 35 #include "net/net.h" 36 #include "qemu/timer.h" 37 #include "sysemu/sysemu.h" 38 #include "hw/boards.h" 39 #include "hw/nvram/sun_nvram.h" 40 #include "hw/nvram/chrp_nvram.h" 41 #include "hw/sparc/sparc64.h" 42 #include "hw/nvram/fw_cfg.h" 43 #include "hw/sysbus.h" 44 #include "hw/ide.h" 45 #include "hw/loader.h" 46 #include "elf.h" 47 #include "qemu/cutils.h" 48 49 //#define DEBUG_EBUS 50 51 #ifdef DEBUG_EBUS 52 #define EBUS_DPRINTF(fmt, ...) \ 53 do { printf("EBUS: " fmt , ## __VA_ARGS__); } while (0) 54 #else 55 #define EBUS_DPRINTF(fmt, ...) 56 #endif 57 58 #define KERNEL_LOAD_ADDR 0x00404000 59 #define CMDLINE_ADDR 0x003ff000 60 #define PROM_SIZE_MAX (4 * 1024 * 1024) 61 #define PROM_VADDR 0x000ffd00000ULL 62 #define APB_SPECIAL_BASE 0x1fe00000000ULL 63 #define APB_MEM_BASE 0x1ff00000000ULL 64 #define APB_PCI_IO_BASE (APB_SPECIAL_BASE + 0x02000000ULL) 65 #define PROM_FILENAME "openbios-sparc64" 66 #define NVRAM_SIZE 0x2000 67 #define MAX_IDE_BUS 2 68 #define BIOS_CFG_IOPORT 0x510 69 #define FW_CFG_SPARC64_WIDTH (FW_CFG_ARCH_LOCAL + 0x00) 70 #define FW_CFG_SPARC64_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01) 71 #define FW_CFG_SPARC64_DEPTH (FW_CFG_ARCH_LOCAL + 0x02) 72 73 #define IVEC_MAX 0x40 74 75 struct hwdef { 76 const char * const default_cpu_model; 77 uint16_t machine_id; 78 uint64_t prom_addr; 79 uint64_t console_serial_base; 80 }; 81 82 typedef struct EbusState { 83 PCIDevice pci_dev; 84 MemoryRegion bar0; 85 MemoryRegion bar1; 86 } EbusState; 87 88 void DMA_init(ISABus *bus, int high_page_enable) 89 { 90 } 91 92 static void fw_cfg_boot_set(void *opaque, const char *boot_device, 93 Error **errp) 94 { 95 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); 96 } 97 98 static int sun4u_NVRAM_set_params(Nvram *nvram, uint16_t NVRAM_size, 99 const char *arch, ram_addr_t RAM_size, 100 const char *boot_devices, 101 uint32_t kernel_image, uint32_t kernel_size, 102 const char *cmdline, 103 uint32_t initrd_image, uint32_t initrd_size, 104 uint32_t NVRAM_image, 105 int width, int height, int depth, 106 const uint8_t *macaddr) 107 { 108 unsigned int i; 109 int sysp_end; 110 uint8_t image[0x1ff0]; 111 NvramClass *k = NVRAM_GET_CLASS(nvram); 112 113 memset(image, '\0', sizeof(image)); 114 115 /* OpenBIOS nvram variables partition */ 116 sysp_end = chrp_nvram_create_system_partition(image, 0); 117 118 /* Free space partition */ 119 chrp_nvram_create_free_partition(&image[sysp_end], 0x1fd0 - sysp_end); 120 121 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80); 122 123 for (i = 0; i < sizeof(image); i++) { 124 (k->write)(nvram, i, image[i]); 125 } 126 127 return 0; 128 } 129 130 static uint64_t sun4u_load_kernel(const char *kernel_filename, 131 const char *initrd_filename, 132 ram_addr_t RAM_size, uint64_t *initrd_size, 133 uint64_t *initrd_addr, uint64_t *kernel_addr, 134 uint64_t *kernel_entry) 135 { 136 int linux_boot; 137 unsigned int i; 138 long kernel_size; 139 uint8_t *ptr; 140 uint64_t kernel_top; 141 142 linux_boot = (kernel_filename != NULL); 143 144 kernel_size = 0; 145 if (linux_boot) { 146 int bswap_needed; 147 148 #ifdef BSWAP_NEEDED 149 bswap_needed = 1; 150 #else 151 bswap_needed = 0; 152 #endif 153 kernel_size = load_elf(kernel_filename, NULL, NULL, kernel_entry, 154 kernel_addr, &kernel_top, 1, EM_SPARCV9, 0, 0); 155 if (kernel_size < 0) { 156 *kernel_addr = KERNEL_LOAD_ADDR; 157 *kernel_entry = KERNEL_LOAD_ADDR; 158 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR, 159 RAM_size - KERNEL_LOAD_ADDR, bswap_needed, 160 TARGET_PAGE_SIZE); 161 } 162 if (kernel_size < 0) { 163 kernel_size = load_image_targphys(kernel_filename, 164 KERNEL_LOAD_ADDR, 165 RAM_size - KERNEL_LOAD_ADDR); 166 } 167 if (kernel_size < 0) { 168 fprintf(stderr, "qemu: could not load kernel '%s'\n", 169 kernel_filename); 170 exit(1); 171 } 172 /* load initrd above kernel */ 173 *initrd_size = 0; 174 if (initrd_filename) { 175 *initrd_addr = TARGET_PAGE_ALIGN(kernel_top); 176 177 *initrd_size = load_image_targphys(initrd_filename, 178 *initrd_addr, 179 RAM_size - *initrd_addr); 180 if ((int)*initrd_size < 0) { 181 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", 182 initrd_filename); 183 exit(1); 184 } 185 } 186 if (*initrd_size > 0) { 187 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { 188 ptr = rom_ptr(*kernel_addr + i); 189 if (ldl_p(ptr + 8) == 0x48647253) { /* HdrS */ 190 stl_p(ptr + 24, *initrd_addr + *kernel_addr); 191 stl_p(ptr + 28, *initrd_size); 192 break; 193 } 194 } 195 } 196 } 197 return kernel_size; 198 } 199 200 typedef struct ResetData { 201 SPARCCPU *cpu; 202 uint64_t prom_addr; 203 } ResetData; 204 205 static void isa_irq_handler(void *opaque, int n, int level) 206 { 207 static const int isa_irq_to_ivec[16] = { 208 [1] = 0x29, /* keyboard */ 209 [4] = 0x2b, /* serial */ 210 [6] = 0x27, /* floppy */ 211 [7] = 0x22, /* parallel */ 212 [12] = 0x2a, /* mouse */ 213 }; 214 qemu_irq *irqs = opaque; 215 int ivec; 216 217 assert(n < ARRAY_SIZE(isa_irq_to_ivec)); 218 ivec = isa_irq_to_ivec[n]; 219 EBUS_DPRINTF("Set ISA IRQ %d level %d -> ivec 0x%x\n", n, level, ivec); 220 if (ivec) { 221 qemu_set_irq(irqs[ivec], level); 222 } 223 } 224 225 /* EBUS (Eight bit bus) bridge */ 226 static ISABus * 227 pci_ebus_init(PCIDevice *pci_dev, qemu_irq *irqs) 228 { 229 qemu_irq *isa_irq; 230 ISABus *isa_bus; 231 232 isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(pci_dev), "isa.0")); 233 isa_irq = qemu_allocate_irqs(isa_irq_handler, irqs, 16); 234 isa_bus_irqs(isa_bus, isa_irq); 235 return isa_bus; 236 } 237 238 static void pci_ebus_realize(PCIDevice *pci_dev, Error **errp) 239 { 240 EbusState *s = DO_UPCAST(EbusState, pci_dev, pci_dev); 241 242 if (!isa_bus_new(DEVICE(pci_dev), get_system_memory(), 243 pci_address_space_io(pci_dev), errp)) { 244 return; 245 } 246 247 pci_dev->config[0x04] = 0x06; // command = bus master, pci mem 248 pci_dev->config[0x05] = 0x00; 249 pci_dev->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error 250 pci_dev->config[0x07] = 0x03; // status = medium devsel 251 pci_dev->config[0x09] = 0x00; // programming i/f 252 pci_dev->config[0x0D] = 0x0a; // latency_timer 253 254 memory_region_init_alias(&s->bar0, OBJECT(s), "bar0", get_system_io(), 255 0, 0x1000000); 256 pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0); 257 memory_region_init_alias(&s->bar1, OBJECT(s), "bar1", get_system_io(), 258 0, 0x4000); 259 pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->bar1); 260 } 261 262 static void ebus_class_init(ObjectClass *klass, void *data) 263 { 264 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 265 266 k->realize = pci_ebus_realize; 267 k->vendor_id = PCI_VENDOR_ID_SUN; 268 k->device_id = PCI_DEVICE_ID_SUN_EBUS; 269 k->revision = 0x01; 270 k->class_id = PCI_CLASS_BRIDGE_OTHER; 271 } 272 273 static const TypeInfo ebus_info = { 274 .name = "ebus", 275 .parent = TYPE_PCI_DEVICE, 276 .instance_size = sizeof(EbusState), 277 .class_init = ebus_class_init, 278 }; 279 280 #define TYPE_OPENPROM "openprom" 281 #define OPENPROM(obj) OBJECT_CHECK(PROMState, (obj), TYPE_OPENPROM) 282 283 typedef struct PROMState { 284 SysBusDevice parent_obj; 285 286 MemoryRegion prom; 287 } PROMState; 288 289 static uint64_t translate_prom_address(void *opaque, uint64_t addr) 290 { 291 hwaddr *base_addr = (hwaddr *)opaque; 292 return addr + *base_addr - PROM_VADDR; 293 } 294 295 /* Boot PROM (OpenBIOS) */ 296 static void prom_init(hwaddr addr, const char *bios_name) 297 { 298 DeviceState *dev; 299 SysBusDevice *s; 300 char *filename; 301 int ret; 302 303 dev = qdev_create(NULL, TYPE_OPENPROM); 304 qdev_init_nofail(dev); 305 s = SYS_BUS_DEVICE(dev); 306 307 sysbus_mmio_map(s, 0, addr); 308 309 /* load boot prom */ 310 if (bios_name == NULL) { 311 bios_name = PROM_FILENAME; 312 } 313 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 314 if (filename) { 315 ret = load_elf(filename, translate_prom_address, &addr, 316 NULL, NULL, NULL, 1, EM_SPARCV9, 0, 0); 317 if (ret < 0 || ret > PROM_SIZE_MAX) { 318 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX); 319 } 320 g_free(filename); 321 } else { 322 ret = -1; 323 } 324 if (ret < 0 || ret > PROM_SIZE_MAX) { 325 fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name); 326 exit(1); 327 } 328 } 329 330 static void prom_init1(Object *obj) 331 { 332 PROMState *s = OPENPROM(obj); 333 SysBusDevice *dev = SYS_BUS_DEVICE(obj); 334 335 memory_region_init_ram_nomigrate(&s->prom, obj, "sun4u.prom", PROM_SIZE_MAX, 336 &error_fatal); 337 vmstate_register_ram_global(&s->prom); 338 memory_region_set_readonly(&s->prom, true); 339 sysbus_init_mmio(dev, &s->prom); 340 } 341 342 static Property prom_properties[] = { 343 {/* end of property list */}, 344 }; 345 346 static void prom_class_init(ObjectClass *klass, void *data) 347 { 348 DeviceClass *dc = DEVICE_CLASS(klass); 349 350 dc->props = prom_properties; 351 } 352 353 static const TypeInfo prom_info = { 354 .name = TYPE_OPENPROM, 355 .parent = TYPE_SYS_BUS_DEVICE, 356 .instance_size = sizeof(PROMState), 357 .class_init = prom_class_init, 358 .instance_init = prom_init1, 359 }; 360 361 362 #define TYPE_SUN4U_MEMORY "memory" 363 #define SUN4U_RAM(obj) OBJECT_CHECK(RamDevice, (obj), TYPE_SUN4U_MEMORY) 364 365 typedef struct RamDevice { 366 SysBusDevice parent_obj; 367 368 MemoryRegion ram; 369 uint64_t size; 370 } RamDevice; 371 372 /* System RAM */ 373 static void ram_realize(DeviceState *dev, Error **errp) 374 { 375 RamDevice *d = SUN4U_RAM(dev); 376 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 377 378 memory_region_init_ram_nomigrate(&d->ram, OBJECT(d), "sun4u.ram", d->size, 379 &error_fatal); 380 vmstate_register_ram_global(&d->ram); 381 sysbus_init_mmio(sbd, &d->ram); 382 } 383 384 static void ram_init(hwaddr addr, ram_addr_t RAM_size) 385 { 386 DeviceState *dev; 387 SysBusDevice *s; 388 RamDevice *d; 389 390 /* allocate RAM */ 391 dev = qdev_create(NULL, TYPE_SUN4U_MEMORY); 392 s = SYS_BUS_DEVICE(dev); 393 394 d = SUN4U_RAM(dev); 395 d->size = RAM_size; 396 qdev_init_nofail(dev); 397 398 sysbus_mmio_map(s, 0, addr); 399 } 400 401 static Property ram_properties[] = { 402 DEFINE_PROP_UINT64("size", RamDevice, size, 0), 403 DEFINE_PROP_END_OF_LIST(), 404 }; 405 406 static void ram_class_init(ObjectClass *klass, void *data) 407 { 408 DeviceClass *dc = DEVICE_CLASS(klass); 409 410 dc->realize = ram_realize; 411 dc->props = ram_properties; 412 } 413 414 static const TypeInfo ram_info = { 415 .name = TYPE_SUN4U_MEMORY, 416 .parent = TYPE_SYS_BUS_DEVICE, 417 .instance_size = sizeof(RamDevice), 418 .class_init = ram_class_init, 419 }; 420 421 static void sun4uv_init(MemoryRegion *address_space_mem, 422 MachineState *machine, 423 const struct hwdef *hwdef) 424 { 425 SPARCCPU *cpu; 426 Nvram *nvram; 427 unsigned int i; 428 uint64_t initrd_addr, initrd_size, kernel_addr, kernel_size, kernel_entry; 429 PCIBus *pci_bus, *pci_busA, *pci_busB; 430 PCIDevice *ebus, *pci_dev; 431 ISABus *isa_bus; 432 SysBusDevice *s; 433 qemu_irq *ivec_irqs, *pbm_irqs; 434 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; 435 DriveInfo *fd[MAX_FD]; 436 DeviceState *dev; 437 FWCfgState *fw_cfg; 438 NICInfo *nd; 439 int onboard_nic_idx; 440 441 /* init CPUs */ 442 cpu = sparc64_cpu_devinit(machine->cpu_model, hwdef->default_cpu_model, 443 hwdef->prom_addr); 444 445 /* set up devices */ 446 ram_init(0, machine->ram_size); 447 448 prom_init(hwdef->prom_addr, bios_name); 449 450 ivec_irqs = qemu_allocate_irqs(sparc64_cpu_set_ivec_irq, cpu, IVEC_MAX); 451 pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, ivec_irqs, &pci_busA, 452 &pci_busB, &pbm_irqs); 453 pci_vga_init(pci_bus); 454 455 /* XXX Should be pci_busA */ 456 ebus = pci_create_simple(pci_bus, -1, "ebus"); 457 isa_bus = pci_ebus_init(ebus, pbm_irqs); 458 459 i = 0; 460 if (hwdef->console_serial_base) { 461 serial_mm_init(address_space_mem, hwdef->console_serial_base, 0, 462 NULL, 115200, serial_hds[i], DEVICE_BIG_ENDIAN); 463 i++; 464 } 465 466 serial_hds_isa_init(isa_bus, i, MAX_SERIAL_PORTS); 467 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); 468 469 onboard_nic_idx = -1; 470 for (i = 0; i < nb_nics; i++) { 471 nd = &nd_table[i]; 472 473 if (onboard_nic_idx == -1 && 474 (!nd->model || strcmp(nd->model, "sunhme") == 0)) { 475 pci_dev = pci_create(pci_bus, -1, "sunhme"); 476 dev = &pci_dev->qdev; 477 qdev_set_nic_properties(dev, nd); 478 qdev_init_nofail(dev); 479 480 onboard_nic_idx = i; 481 } else { 482 pci_nic_init_nofail(nd, pci_bus, "ne2k_pci", NULL); 483 } 484 } 485 onboard_nic_idx = MAX(onboard_nic_idx, 0); 486 487 ide_drive_get(hd, ARRAY_SIZE(hd)); 488 489 pci_cmd646_ide_init(pci_bus, hd, 1); 490 491 isa_create_simple(isa_bus, "i8042"); 492 493 /* Floppy */ 494 for(i = 0; i < MAX_FD; i++) { 495 fd[i] = drive_get(IF_FLOPPY, 0, i); 496 } 497 dev = DEVICE(isa_create(isa_bus, TYPE_ISA_FDC)); 498 if (fd[0]) { 499 qdev_prop_set_drive(dev, "driveA", blk_by_legacy_dinfo(fd[0]), 500 &error_abort); 501 } 502 if (fd[1]) { 503 qdev_prop_set_drive(dev, "driveB", blk_by_legacy_dinfo(fd[1]), 504 &error_abort); 505 } 506 qdev_prop_set_uint32(dev, "dma", -1); 507 qdev_init_nofail(dev); 508 509 /* Map NVRAM into I/O (ebus) space */ 510 nvram = m48t59_init(NULL, 0, 0, NVRAM_SIZE, 1968, 59); 511 s = SYS_BUS_DEVICE(nvram); 512 memory_region_add_subregion(pci_address_space_io(ebus), 0x2000, 513 sysbus_mmio_get_region(s, 0)); 514 515 initrd_size = 0; 516 initrd_addr = 0; 517 kernel_size = sun4u_load_kernel(machine->kernel_filename, 518 machine->initrd_filename, 519 ram_size, &initrd_size, &initrd_addr, 520 &kernel_addr, &kernel_entry); 521 522 sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", machine->ram_size, 523 machine->boot_order, 524 kernel_addr, kernel_size, 525 machine->kernel_cmdline, 526 initrd_addr, initrd_size, 527 /* XXX: need an option to load a NVRAM image */ 528 0, 529 graphic_width, graphic_height, graphic_depth, 530 (uint8_t *)&nd_table[onboard_nic_idx].macaddr); 531 532 dev = qdev_create(NULL, TYPE_FW_CFG_IO); 533 qdev_prop_set_bit(dev, "dma_enabled", false); 534 object_property_add_child(OBJECT(ebus), TYPE_FW_CFG, OBJECT(dev), NULL); 535 qdev_init_nofail(dev); 536 memory_region_add_subregion(pci_address_space_io(ebus), BIOS_CFG_IOPORT, 537 &FW_CFG_IO(dev)->comb_iomem); 538 539 fw_cfg = FW_CFG(dev); 540 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus); 541 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus); 542 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 543 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); 544 fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_entry); 545 fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 546 if (machine->kernel_cmdline) { 547 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 548 strlen(machine->kernel_cmdline) + 1); 549 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline); 550 } else { 551 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0); 552 } 553 fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); 554 fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 555 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]); 556 557 fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_WIDTH, graphic_width); 558 fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_HEIGHT, graphic_height); 559 fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_DEPTH, graphic_depth); 560 561 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); 562 } 563 564 enum { 565 sun4u_id = 0, 566 sun4v_id = 64, 567 }; 568 569 static const struct hwdef hwdefs[] = { 570 /* Sun4u generic PC-like machine */ 571 { 572 .default_cpu_model = "TI UltraSparc IIi", 573 .machine_id = sun4u_id, 574 .prom_addr = 0x1fff0000000ULL, 575 .console_serial_base = 0, 576 }, 577 /* Sun4v generic PC-like machine */ 578 { 579 .default_cpu_model = "Sun UltraSparc T1", 580 .machine_id = sun4v_id, 581 .prom_addr = 0x1fff0000000ULL, 582 .console_serial_base = 0, 583 }, 584 }; 585 586 /* Sun4u hardware initialisation */ 587 static void sun4u_init(MachineState *machine) 588 { 589 sun4uv_init(get_system_memory(), machine, &hwdefs[0]); 590 } 591 592 /* Sun4v hardware initialisation */ 593 static void sun4v_init(MachineState *machine) 594 { 595 sun4uv_init(get_system_memory(), machine, &hwdefs[1]); 596 } 597 598 static void sun4u_class_init(ObjectClass *oc, void *data) 599 { 600 MachineClass *mc = MACHINE_CLASS(oc); 601 602 mc->desc = "Sun4u platform"; 603 mc->init = sun4u_init; 604 mc->block_default_type = IF_IDE; 605 mc->max_cpus = 1; /* XXX for now */ 606 mc->is_default = 1; 607 mc->default_boot_order = "c"; 608 } 609 610 static const TypeInfo sun4u_type = { 611 .name = MACHINE_TYPE_NAME("sun4u"), 612 .parent = TYPE_MACHINE, 613 .class_init = sun4u_class_init, 614 }; 615 616 static void sun4v_class_init(ObjectClass *oc, void *data) 617 { 618 MachineClass *mc = MACHINE_CLASS(oc); 619 620 mc->desc = "Sun4v platform"; 621 mc->init = sun4v_init; 622 mc->block_default_type = IF_IDE; 623 mc->max_cpus = 1; /* XXX for now */ 624 mc->default_boot_order = "c"; 625 } 626 627 static const TypeInfo sun4v_type = { 628 .name = MACHINE_TYPE_NAME("sun4v"), 629 .parent = TYPE_MACHINE, 630 .class_init = sun4v_class_init, 631 }; 632 633 static void sun4u_register_types(void) 634 { 635 type_register_static(&ebus_info); 636 type_register_static(&prom_info); 637 type_register_static(&ram_info); 638 639 type_register_static(&sun4u_type); 640 type_register_static(&sun4v_type); 641 } 642 643 type_init(sun4u_register_types) 644