1 /* 2 * QEMU Sun4u/Sun4v System Emulator 3 * 4 * Copyright (c) 2005 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "qemu/osdep.h" 25 #include "qapi/error.h" 26 #include "qemu-common.h" 27 #include "cpu.h" 28 #include "hw/hw.h" 29 #include "hw/pci/pci.h" 30 #include "hw/pci/pci_bridge.h" 31 #include "hw/pci/pci_bus.h" 32 #include "hw/pci-host/apb.h" 33 #include "hw/i386/pc.h" 34 #include "hw/char/serial.h" 35 #include "hw/timer/m48t59.h" 36 #include "hw/block/fdc.h" 37 #include "net/net.h" 38 #include "qemu/timer.h" 39 #include "sysemu/sysemu.h" 40 #include "hw/boards.h" 41 #include "hw/nvram/sun_nvram.h" 42 #include "hw/nvram/chrp_nvram.h" 43 #include "hw/sparc/sparc64.h" 44 #include "hw/nvram/fw_cfg.h" 45 #include "hw/sysbus.h" 46 #include "hw/ide.h" 47 #include "hw/ide/pci.h" 48 #include "hw/loader.h" 49 #include "elf.h" 50 #include "qemu/cutils.h" 51 52 //#define DEBUG_EBUS 53 54 #ifdef DEBUG_EBUS 55 #define EBUS_DPRINTF(fmt, ...) \ 56 do { printf("EBUS: " fmt , ## __VA_ARGS__); } while (0) 57 #else 58 #define EBUS_DPRINTF(fmt, ...) 59 #endif 60 61 #define KERNEL_LOAD_ADDR 0x00404000 62 #define CMDLINE_ADDR 0x003ff000 63 #define PROM_SIZE_MAX (4 * 1024 * 1024) 64 #define PROM_VADDR 0x000ffd00000ULL 65 #define APB_SPECIAL_BASE 0x1fe00000000ULL 66 #define APB_MEM_BASE 0x1ff00000000ULL 67 #define APB_PCI_IO_BASE (APB_SPECIAL_BASE + 0x02000000ULL) 68 #define PROM_FILENAME "openbios-sparc64" 69 #define NVRAM_SIZE 0x2000 70 #define MAX_IDE_BUS 2 71 #define BIOS_CFG_IOPORT 0x510 72 #define FW_CFG_SPARC64_WIDTH (FW_CFG_ARCH_LOCAL + 0x00) 73 #define FW_CFG_SPARC64_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01) 74 #define FW_CFG_SPARC64_DEPTH (FW_CFG_ARCH_LOCAL + 0x02) 75 76 #define IVEC_MAX 0x40 77 78 struct hwdef { 79 uint16_t machine_id; 80 uint64_t prom_addr; 81 uint64_t console_serial_base; 82 }; 83 84 typedef struct EbusState { 85 /*< private >*/ 86 PCIDevice parent_obj; 87 88 ISABus *isa_bus; 89 uint64_t console_serial_base; 90 MemoryRegion bar0; 91 MemoryRegion bar1; 92 } EbusState; 93 94 #define TYPE_EBUS "ebus" 95 #define EBUS(obj) OBJECT_CHECK(EbusState, (obj), TYPE_EBUS) 96 97 void DMA_init(ISABus *bus, int high_page_enable) 98 { 99 } 100 101 static void fw_cfg_boot_set(void *opaque, const char *boot_device, 102 Error **errp) 103 { 104 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); 105 } 106 107 static int sun4u_NVRAM_set_params(Nvram *nvram, uint16_t NVRAM_size, 108 const char *arch, ram_addr_t RAM_size, 109 const char *boot_devices, 110 uint32_t kernel_image, uint32_t kernel_size, 111 const char *cmdline, 112 uint32_t initrd_image, uint32_t initrd_size, 113 uint32_t NVRAM_image, 114 int width, int height, int depth, 115 const uint8_t *macaddr) 116 { 117 unsigned int i; 118 int sysp_end; 119 uint8_t image[0x1ff0]; 120 NvramClass *k = NVRAM_GET_CLASS(nvram); 121 122 memset(image, '\0', sizeof(image)); 123 124 /* OpenBIOS nvram variables partition */ 125 sysp_end = chrp_nvram_create_system_partition(image, 0); 126 127 /* Free space partition */ 128 chrp_nvram_create_free_partition(&image[sysp_end], 0x1fd0 - sysp_end); 129 130 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80); 131 132 for (i = 0; i < sizeof(image); i++) { 133 (k->write)(nvram, i, image[i]); 134 } 135 136 return 0; 137 } 138 139 static uint64_t sun4u_load_kernel(const char *kernel_filename, 140 const char *initrd_filename, 141 ram_addr_t RAM_size, uint64_t *initrd_size, 142 uint64_t *initrd_addr, uint64_t *kernel_addr, 143 uint64_t *kernel_entry) 144 { 145 int linux_boot; 146 unsigned int i; 147 long kernel_size; 148 uint8_t *ptr; 149 uint64_t kernel_top; 150 151 linux_boot = (kernel_filename != NULL); 152 153 kernel_size = 0; 154 if (linux_boot) { 155 int bswap_needed; 156 157 #ifdef BSWAP_NEEDED 158 bswap_needed = 1; 159 #else 160 bswap_needed = 0; 161 #endif 162 kernel_size = load_elf(kernel_filename, NULL, NULL, kernel_entry, 163 kernel_addr, &kernel_top, 1, EM_SPARCV9, 0, 0); 164 if (kernel_size < 0) { 165 *kernel_addr = KERNEL_LOAD_ADDR; 166 *kernel_entry = KERNEL_LOAD_ADDR; 167 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR, 168 RAM_size - KERNEL_LOAD_ADDR, bswap_needed, 169 TARGET_PAGE_SIZE); 170 } 171 if (kernel_size < 0) { 172 kernel_size = load_image_targphys(kernel_filename, 173 KERNEL_LOAD_ADDR, 174 RAM_size - KERNEL_LOAD_ADDR); 175 } 176 if (kernel_size < 0) { 177 fprintf(stderr, "qemu: could not load kernel '%s'\n", 178 kernel_filename); 179 exit(1); 180 } 181 /* load initrd above kernel */ 182 *initrd_size = 0; 183 if (initrd_filename) { 184 *initrd_addr = TARGET_PAGE_ALIGN(kernel_top); 185 186 *initrd_size = load_image_targphys(initrd_filename, 187 *initrd_addr, 188 RAM_size - *initrd_addr); 189 if ((int)*initrd_size < 0) { 190 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", 191 initrd_filename); 192 exit(1); 193 } 194 } 195 if (*initrd_size > 0) { 196 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { 197 ptr = rom_ptr(*kernel_addr + i); 198 if (ldl_p(ptr + 8) == 0x48647253) { /* HdrS */ 199 stl_p(ptr + 24, *initrd_addr + *kernel_addr); 200 stl_p(ptr + 28, *initrd_size); 201 break; 202 } 203 } 204 } 205 } 206 return kernel_size; 207 } 208 209 typedef struct ResetData { 210 SPARCCPU *cpu; 211 uint64_t prom_addr; 212 } ResetData; 213 214 static void isa_irq_handler(void *opaque, int n, int level) 215 { 216 static const int isa_irq_to_ivec[16] = { 217 [1] = 0x29, /* keyboard */ 218 [4] = 0x2b, /* serial */ 219 [6] = 0x27, /* floppy */ 220 [7] = 0x22, /* parallel */ 221 [12] = 0x2a, /* mouse */ 222 }; 223 qemu_irq *irqs = opaque; 224 int ivec; 225 226 assert(n < ARRAY_SIZE(isa_irq_to_ivec)); 227 ivec = isa_irq_to_ivec[n]; 228 EBUS_DPRINTF("Set ISA IRQ %d level %d -> ivec 0x%x\n", n, level, ivec); 229 if (ivec) { 230 qemu_set_irq(irqs[ivec], level); 231 } 232 } 233 234 /* EBUS (Eight bit bus) bridge */ 235 static void ebus_realize(PCIDevice *pci_dev, Error **errp) 236 { 237 EbusState *s = EBUS(pci_dev); 238 APBState *apb; 239 DeviceState *dev; 240 qemu_irq *isa_irq; 241 DriveInfo *fd[MAX_FD]; 242 int i; 243 244 s->isa_bus = isa_bus_new(DEVICE(pci_dev), get_system_memory(), 245 pci_address_space_io(pci_dev), errp); 246 if (!s->isa_bus) { 247 error_setg(errp, "unable to instantiate EBUS ISA bus"); 248 return; 249 } 250 251 apb = APB_DEVICE(object_resolve_path_type("", TYPE_APB, NULL)); 252 if (!apb) { 253 error_setg(errp, "unable to locate APB PCI host bridge"); 254 return; 255 } 256 257 isa_irq = qemu_allocate_irqs(isa_irq_handler, apb->pbm_irqs, 16); 258 isa_bus_irqs(s->isa_bus, isa_irq); 259 260 /* Serial ports */ 261 i = 0; 262 if (s->console_serial_base) { 263 serial_mm_init(pci_address_space(pci_dev), s->console_serial_base, 264 0, NULL, 115200, serial_hds[i], DEVICE_BIG_ENDIAN); 265 i++; 266 } 267 serial_hds_isa_init(s->isa_bus, i, MAX_SERIAL_PORTS); 268 269 /* Parallel ports */ 270 parallel_hds_isa_init(s->isa_bus, MAX_PARALLEL_PORTS); 271 272 /* Keyboard */ 273 isa_create_simple(s->isa_bus, "i8042"); 274 275 /* Floppy */ 276 for (i = 0; i < MAX_FD; i++) { 277 fd[i] = drive_get(IF_FLOPPY, 0, i); 278 } 279 dev = DEVICE(isa_create(s->isa_bus, TYPE_ISA_FDC)); 280 if (fd[0]) { 281 qdev_prop_set_drive(dev, "driveA", blk_by_legacy_dinfo(fd[0]), 282 &error_abort); 283 } 284 if (fd[1]) { 285 qdev_prop_set_drive(dev, "driveB", blk_by_legacy_dinfo(fd[1]), 286 &error_abort); 287 } 288 qdev_prop_set_uint32(dev, "dma", -1); 289 qdev_init_nofail(dev); 290 291 /* PCI */ 292 pci_dev->config[0x04] = 0x06; // command = bus master, pci mem 293 pci_dev->config[0x05] = 0x00; 294 pci_dev->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error 295 pci_dev->config[0x07] = 0x03; // status = medium devsel 296 pci_dev->config[0x09] = 0x00; // programming i/f 297 pci_dev->config[0x0D] = 0x0a; // latency_timer 298 299 memory_region_init_alias(&s->bar0, OBJECT(s), "bar0", get_system_io(), 300 0, 0x1000000); 301 pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0); 302 memory_region_init_alias(&s->bar1, OBJECT(s), "bar1", get_system_io(), 303 0, 0x4000); 304 pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->bar1); 305 } 306 307 static Property ebus_properties[] = { 308 DEFINE_PROP_UINT64("console-serial-base", EbusState, 309 console_serial_base, 0), 310 DEFINE_PROP_END_OF_LIST(), 311 }; 312 313 static void ebus_class_init(ObjectClass *klass, void *data) 314 { 315 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 316 DeviceClass *dc = DEVICE_CLASS(klass); 317 318 k->realize = ebus_realize; 319 k->vendor_id = PCI_VENDOR_ID_SUN; 320 k->device_id = PCI_DEVICE_ID_SUN_EBUS; 321 k->revision = 0x01; 322 k->class_id = PCI_CLASS_BRIDGE_OTHER; 323 dc->props = ebus_properties; 324 } 325 326 static const TypeInfo ebus_info = { 327 .name = TYPE_EBUS, 328 .parent = TYPE_PCI_DEVICE, 329 .class_init = ebus_class_init, 330 .instance_size = sizeof(EbusState), 331 .interfaces = (InterfaceInfo[]) { 332 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 333 { }, 334 }, 335 }; 336 337 #define TYPE_OPENPROM "openprom" 338 #define OPENPROM(obj) OBJECT_CHECK(PROMState, (obj), TYPE_OPENPROM) 339 340 typedef struct PROMState { 341 SysBusDevice parent_obj; 342 343 MemoryRegion prom; 344 } PROMState; 345 346 static uint64_t translate_prom_address(void *opaque, uint64_t addr) 347 { 348 hwaddr *base_addr = (hwaddr *)opaque; 349 return addr + *base_addr - PROM_VADDR; 350 } 351 352 /* Boot PROM (OpenBIOS) */ 353 static void prom_init(hwaddr addr, const char *bios_name) 354 { 355 DeviceState *dev; 356 SysBusDevice *s; 357 char *filename; 358 int ret; 359 360 dev = qdev_create(NULL, TYPE_OPENPROM); 361 qdev_init_nofail(dev); 362 s = SYS_BUS_DEVICE(dev); 363 364 sysbus_mmio_map(s, 0, addr); 365 366 /* load boot prom */ 367 if (bios_name == NULL) { 368 bios_name = PROM_FILENAME; 369 } 370 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 371 if (filename) { 372 ret = load_elf(filename, translate_prom_address, &addr, 373 NULL, NULL, NULL, 1, EM_SPARCV9, 0, 0); 374 if (ret < 0 || ret > PROM_SIZE_MAX) { 375 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX); 376 } 377 g_free(filename); 378 } else { 379 ret = -1; 380 } 381 if (ret < 0 || ret > PROM_SIZE_MAX) { 382 fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name); 383 exit(1); 384 } 385 } 386 387 static void prom_init1(Object *obj) 388 { 389 PROMState *s = OPENPROM(obj); 390 SysBusDevice *dev = SYS_BUS_DEVICE(obj); 391 392 memory_region_init_ram_nomigrate(&s->prom, obj, "sun4u.prom", PROM_SIZE_MAX, 393 &error_fatal); 394 vmstate_register_ram_global(&s->prom); 395 memory_region_set_readonly(&s->prom, true); 396 sysbus_init_mmio(dev, &s->prom); 397 } 398 399 static Property prom_properties[] = { 400 {/* end of property list */}, 401 }; 402 403 static void prom_class_init(ObjectClass *klass, void *data) 404 { 405 DeviceClass *dc = DEVICE_CLASS(klass); 406 407 dc->props = prom_properties; 408 } 409 410 static const TypeInfo prom_info = { 411 .name = TYPE_OPENPROM, 412 .parent = TYPE_SYS_BUS_DEVICE, 413 .instance_size = sizeof(PROMState), 414 .class_init = prom_class_init, 415 .instance_init = prom_init1, 416 }; 417 418 419 #define TYPE_SUN4U_MEMORY "memory" 420 #define SUN4U_RAM(obj) OBJECT_CHECK(RamDevice, (obj), TYPE_SUN4U_MEMORY) 421 422 typedef struct RamDevice { 423 SysBusDevice parent_obj; 424 425 MemoryRegion ram; 426 uint64_t size; 427 } RamDevice; 428 429 /* System RAM */ 430 static void ram_realize(DeviceState *dev, Error **errp) 431 { 432 RamDevice *d = SUN4U_RAM(dev); 433 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 434 435 memory_region_init_ram_nomigrate(&d->ram, OBJECT(d), "sun4u.ram", d->size, 436 &error_fatal); 437 vmstate_register_ram_global(&d->ram); 438 sysbus_init_mmio(sbd, &d->ram); 439 } 440 441 static void ram_init(hwaddr addr, ram_addr_t RAM_size) 442 { 443 DeviceState *dev; 444 SysBusDevice *s; 445 RamDevice *d; 446 447 /* allocate RAM */ 448 dev = qdev_create(NULL, TYPE_SUN4U_MEMORY); 449 s = SYS_BUS_DEVICE(dev); 450 451 d = SUN4U_RAM(dev); 452 d->size = RAM_size; 453 qdev_init_nofail(dev); 454 455 sysbus_mmio_map(s, 0, addr); 456 } 457 458 static Property ram_properties[] = { 459 DEFINE_PROP_UINT64("size", RamDevice, size, 0), 460 DEFINE_PROP_END_OF_LIST(), 461 }; 462 463 static void ram_class_init(ObjectClass *klass, void *data) 464 { 465 DeviceClass *dc = DEVICE_CLASS(klass); 466 467 dc->realize = ram_realize; 468 dc->props = ram_properties; 469 } 470 471 static const TypeInfo ram_info = { 472 .name = TYPE_SUN4U_MEMORY, 473 .parent = TYPE_SYS_BUS_DEVICE, 474 .instance_size = sizeof(RamDevice), 475 .class_init = ram_class_init, 476 }; 477 478 static void sun4uv_init(MemoryRegion *address_space_mem, 479 MachineState *machine, 480 const struct hwdef *hwdef) 481 { 482 SPARCCPU *cpu; 483 Nvram *nvram; 484 unsigned int i; 485 uint64_t initrd_addr, initrd_size, kernel_addr, kernel_size, kernel_entry; 486 APBState *apb; 487 PCIBus *pci_bus, *pci_busA, *pci_busB; 488 PCIDevice *ebus, *pci_dev; 489 SysBusDevice *s; 490 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; 491 DeviceState *dev; 492 FWCfgState *fw_cfg; 493 NICInfo *nd; 494 MACAddr macaddr; 495 bool onboard_nic; 496 497 /* init CPUs */ 498 cpu = sparc64_cpu_devinit(machine->cpu_type, hwdef->prom_addr); 499 500 /* set up devices */ 501 ram_init(0, machine->ram_size); 502 503 prom_init(hwdef->prom_addr, bios_name); 504 505 apb = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE); 506 507 /* Wire up PCI interrupts to CPU */ 508 for (i = 0; i < IVEC_MAX; i++) { 509 qdev_connect_gpio_out_named(DEVICE(apb), "ivec-irq", i, 510 qdev_get_gpio_in_named(DEVICE(cpu), "ivec-irq", i)); 511 } 512 513 pci_bus = PCI_HOST_BRIDGE(apb)->bus; 514 pci_busA = pci_bridge_get_sec_bus(apb->bridgeA); 515 pci_busB = pci_bridge_get_sec_bus(apb->bridgeB); 516 517 /* Only in-built Simba PBMs can exist on the root bus, slot 0 on busA is 518 reserved (leaving no slots free after on-board devices) however slots 519 0-3 are free on busB */ 520 pci_bus->slot_reserved_mask = 0xfffffffc; 521 pci_busA->slot_reserved_mask = 0xfffffff1; 522 pci_busB->slot_reserved_mask = 0xfffffff0; 523 524 ebus = pci_create_multifunction(pci_busA, PCI_DEVFN(1, 0), true, TYPE_EBUS); 525 qdev_prop_set_uint64(DEVICE(ebus), "console-serial-base", 526 hwdef->console_serial_base); 527 qdev_init_nofail(DEVICE(ebus)); 528 529 pci_dev = pci_create_simple(pci_busA, PCI_DEVFN(2, 0), "VGA"); 530 531 memset(&macaddr, 0, sizeof(MACAddr)); 532 onboard_nic = false; 533 for (i = 0; i < nb_nics; i++) { 534 nd = &nd_table[i]; 535 536 if (!nd->model || strcmp(nd->model, "sunhme") == 0) { 537 if (!onboard_nic) { 538 pci_dev = pci_create_multifunction(pci_busA, PCI_DEVFN(1, 1), 539 true, "sunhme"); 540 memcpy(&macaddr, &nd->macaddr.a, sizeof(MACAddr)); 541 onboard_nic = true; 542 } else { 543 pci_dev = pci_create(pci_busB, -1, "sunhme"); 544 } 545 } else { 546 pci_dev = pci_create(pci_busB, -1, nd->model); 547 } 548 549 dev = &pci_dev->qdev; 550 qdev_set_nic_properties(dev, nd); 551 qdev_init_nofail(dev); 552 } 553 554 /* If we don't have an onboard NIC, grab a default MAC address so that 555 * we have a valid machine id */ 556 if (!onboard_nic) { 557 qemu_macaddr_default_if_unset(&macaddr); 558 } 559 560 ide_drive_get(hd, ARRAY_SIZE(hd)); 561 562 pci_dev = pci_create(pci_busA, PCI_DEVFN(3, 0), "cmd646-ide"); 563 qdev_prop_set_uint32(&pci_dev->qdev, "secondary", 1); 564 qdev_init_nofail(&pci_dev->qdev); 565 pci_ide_create_devs(pci_dev, hd); 566 567 /* Map NVRAM into I/O (ebus) space */ 568 nvram = m48t59_init(NULL, 0, 0, NVRAM_SIZE, 1968, 59); 569 s = SYS_BUS_DEVICE(nvram); 570 memory_region_add_subregion(pci_address_space_io(ebus), 0x2000, 571 sysbus_mmio_get_region(s, 0)); 572 573 initrd_size = 0; 574 initrd_addr = 0; 575 kernel_size = sun4u_load_kernel(machine->kernel_filename, 576 machine->initrd_filename, 577 ram_size, &initrd_size, &initrd_addr, 578 &kernel_addr, &kernel_entry); 579 580 sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", machine->ram_size, 581 machine->boot_order, 582 kernel_addr, kernel_size, 583 machine->kernel_cmdline, 584 initrd_addr, initrd_size, 585 /* XXX: need an option to load a NVRAM image */ 586 0, 587 graphic_width, graphic_height, graphic_depth, 588 (uint8_t *)&macaddr); 589 590 dev = qdev_create(NULL, TYPE_FW_CFG_IO); 591 qdev_prop_set_bit(dev, "dma_enabled", false); 592 object_property_add_child(OBJECT(ebus), TYPE_FW_CFG, OBJECT(dev), NULL); 593 qdev_init_nofail(dev); 594 memory_region_add_subregion(pci_address_space_io(ebus), BIOS_CFG_IOPORT, 595 &FW_CFG_IO(dev)->comb_iomem); 596 597 fw_cfg = FW_CFG(dev); 598 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus); 599 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus); 600 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 601 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); 602 fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_entry); 603 fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 604 if (machine->kernel_cmdline) { 605 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 606 strlen(machine->kernel_cmdline) + 1); 607 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline); 608 } else { 609 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0); 610 } 611 fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); 612 fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 613 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]); 614 615 fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_WIDTH, graphic_width); 616 fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_HEIGHT, graphic_height); 617 fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_DEPTH, graphic_depth); 618 619 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); 620 } 621 622 enum { 623 sun4u_id = 0, 624 sun4v_id = 64, 625 }; 626 627 static const struct hwdef hwdefs[] = { 628 /* Sun4u generic PC-like machine */ 629 { 630 .machine_id = sun4u_id, 631 .prom_addr = 0x1fff0000000ULL, 632 .console_serial_base = 0, 633 }, 634 /* Sun4v generic PC-like machine */ 635 { 636 .machine_id = sun4v_id, 637 .prom_addr = 0x1fff0000000ULL, 638 .console_serial_base = 0, 639 }, 640 }; 641 642 /* Sun4u hardware initialisation */ 643 static void sun4u_init(MachineState *machine) 644 { 645 sun4uv_init(get_system_memory(), machine, &hwdefs[0]); 646 } 647 648 /* Sun4v hardware initialisation */ 649 static void sun4v_init(MachineState *machine) 650 { 651 sun4uv_init(get_system_memory(), machine, &hwdefs[1]); 652 } 653 654 static void sun4u_class_init(ObjectClass *oc, void *data) 655 { 656 MachineClass *mc = MACHINE_CLASS(oc); 657 658 mc->desc = "Sun4u platform"; 659 mc->init = sun4u_init; 660 mc->block_default_type = IF_IDE; 661 mc->max_cpus = 1; /* XXX for now */ 662 mc->is_default = 1; 663 mc->default_boot_order = "c"; 664 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-UltraSparc-IIi"); 665 } 666 667 static const TypeInfo sun4u_type = { 668 .name = MACHINE_TYPE_NAME("sun4u"), 669 .parent = TYPE_MACHINE, 670 .class_init = sun4u_class_init, 671 }; 672 673 static void sun4v_class_init(ObjectClass *oc, void *data) 674 { 675 MachineClass *mc = MACHINE_CLASS(oc); 676 677 mc->desc = "Sun4v platform"; 678 mc->init = sun4v_init; 679 mc->block_default_type = IF_IDE; 680 mc->max_cpus = 1; /* XXX for now */ 681 mc->default_boot_order = "c"; 682 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Sun-UltraSparc-T1"); 683 } 684 685 static const TypeInfo sun4v_type = { 686 .name = MACHINE_TYPE_NAME("sun4v"), 687 .parent = TYPE_MACHINE, 688 .class_init = sun4v_class_init, 689 }; 690 691 static void sun4u_register_types(void) 692 { 693 type_register_static(&ebus_info); 694 type_register_static(&prom_info); 695 type_register_static(&ram_info); 696 697 type_register_static(&sun4u_type); 698 type_register_static(&sun4v_type); 699 } 700 701 type_init(sun4u_register_types) 702