1 /* 2 * QEMU Sun4u/Sun4v System Emulator 3 * 4 * Copyright (c) 2005 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "hw/hw.h" 25 #include "hw/pci/pci.h" 26 #include "hw/pci-host/apb.h" 27 #include "hw/i386/pc.h" 28 #include "hw/char/serial.h" 29 #include "hw/timer/m48t59.h" 30 #include "hw/block/fdc.h" 31 #include "net/net.h" 32 #include "qemu/timer.h" 33 #include "sysemu/sysemu.h" 34 #include "hw/boards.h" 35 #include "hw/nvram/openbios_firmware_abi.h" 36 #include "hw/nvram/fw_cfg.h" 37 #include "hw/sysbus.h" 38 #include "hw/ide.h" 39 #include "hw/loader.h" 40 #include "elf.h" 41 #include "sysemu/block-backend.h" 42 #include "exec/address-spaces.h" 43 44 //#define DEBUG_IRQ 45 //#define DEBUG_EBUS 46 //#define DEBUG_TIMER 47 48 #ifdef DEBUG_IRQ 49 #define CPUIRQ_DPRINTF(fmt, ...) \ 50 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0) 51 #else 52 #define CPUIRQ_DPRINTF(fmt, ...) 53 #endif 54 55 #ifdef DEBUG_EBUS 56 #define EBUS_DPRINTF(fmt, ...) \ 57 do { printf("EBUS: " fmt , ## __VA_ARGS__); } while (0) 58 #else 59 #define EBUS_DPRINTF(fmt, ...) 60 #endif 61 62 #ifdef DEBUG_TIMER 63 #define TIMER_DPRINTF(fmt, ...) \ 64 do { printf("TIMER: " fmt , ## __VA_ARGS__); } while (0) 65 #else 66 #define TIMER_DPRINTF(fmt, ...) 67 #endif 68 69 #define KERNEL_LOAD_ADDR 0x00404000 70 #define CMDLINE_ADDR 0x003ff000 71 #define PROM_SIZE_MAX (4 * 1024 * 1024) 72 #define PROM_VADDR 0x000ffd00000ULL 73 #define APB_SPECIAL_BASE 0x1fe00000000ULL 74 #define APB_MEM_BASE 0x1ff00000000ULL 75 #define APB_PCI_IO_BASE (APB_SPECIAL_BASE + 0x02000000ULL) 76 #define PROM_FILENAME "openbios-sparc64" 77 #define NVRAM_SIZE 0x2000 78 #define MAX_IDE_BUS 2 79 #define BIOS_CFG_IOPORT 0x510 80 #define FW_CFG_SPARC64_WIDTH (FW_CFG_ARCH_LOCAL + 0x00) 81 #define FW_CFG_SPARC64_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01) 82 #define FW_CFG_SPARC64_DEPTH (FW_CFG_ARCH_LOCAL + 0x02) 83 84 #define IVEC_MAX 0x40 85 86 #define TICK_MAX 0x7fffffffffffffffULL 87 88 struct hwdef { 89 const char * const default_cpu_model; 90 uint16_t machine_id; 91 uint64_t prom_addr; 92 uint64_t console_serial_base; 93 }; 94 95 typedef struct EbusState { 96 PCIDevice pci_dev; 97 MemoryRegion bar0; 98 MemoryRegion bar1; 99 } EbusState; 100 101 int DMA_get_channel_mode (int nchan) 102 { 103 return 0; 104 } 105 int DMA_read_memory (int nchan, void *buf, int pos, int size) 106 { 107 return 0; 108 } 109 int DMA_write_memory (int nchan, void *buf, int pos, int size) 110 { 111 return 0; 112 } 113 void DMA_hold_DREQ (int nchan) {} 114 void DMA_release_DREQ (int nchan) {} 115 void DMA_schedule(void) {} 116 117 void DMA_init(int high_page_enable) 118 { 119 } 120 121 void DMA_register_channel (int nchan, 122 DMA_transfer_handler transfer_handler, 123 void *opaque) 124 { 125 } 126 127 static void fw_cfg_boot_set(void *opaque, const char *boot_device, 128 Error **errp) 129 { 130 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); 131 } 132 133 static int sun4u_NVRAM_set_params(Nvram *nvram, uint16_t NVRAM_size, 134 const char *arch, ram_addr_t RAM_size, 135 const char *boot_devices, 136 uint32_t kernel_image, uint32_t kernel_size, 137 const char *cmdline, 138 uint32_t initrd_image, uint32_t initrd_size, 139 uint32_t NVRAM_image, 140 int width, int height, int depth, 141 const uint8_t *macaddr) 142 { 143 unsigned int i; 144 uint32_t start, end; 145 uint8_t image[0x1ff0]; 146 struct OpenBIOS_nvpart_v1 *part_header; 147 NvramClass *k = NVRAM_GET_CLASS(nvram); 148 149 memset(image, '\0', sizeof(image)); 150 151 start = 0; 152 153 // OpenBIOS nvram variables 154 // Variable partition 155 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start]; 156 part_header->signature = OPENBIOS_PART_SYSTEM; 157 pstrcpy(part_header->name, sizeof(part_header->name), "system"); 158 159 end = start + sizeof(struct OpenBIOS_nvpart_v1); 160 for (i = 0; i < nb_prom_envs; i++) 161 end = OpenBIOS_set_var(image, end, prom_envs[i]); 162 163 // End marker 164 image[end++] = '\0'; 165 166 end = start + ((end - start + 15) & ~15); 167 OpenBIOS_finish_partition(part_header, end - start); 168 169 // free partition 170 start = end; 171 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start]; 172 part_header->signature = OPENBIOS_PART_FREE; 173 pstrcpy(part_header->name, sizeof(part_header->name), "free"); 174 175 end = 0x1fd0; 176 OpenBIOS_finish_partition(part_header, end - start); 177 178 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80); 179 180 for (i = 0; i < sizeof(image); i++) { 181 (k->write)(nvram, i, image[i]); 182 } 183 184 return 0; 185 } 186 187 static uint64_t sun4u_load_kernel(const char *kernel_filename, 188 const char *initrd_filename, 189 ram_addr_t RAM_size, uint64_t *initrd_size, 190 uint64_t *initrd_addr, uint64_t *kernel_addr, 191 uint64_t *kernel_entry) 192 { 193 int linux_boot; 194 unsigned int i; 195 long kernel_size; 196 uint8_t *ptr; 197 uint64_t kernel_top; 198 199 linux_boot = (kernel_filename != NULL); 200 201 kernel_size = 0; 202 if (linux_boot) { 203 int bswap_needed; 204 205 #ifdef BSWAP_NEEDED 206 bswap_needed = 1; 207 #else 208 bswap_needed = 0; 209 #endif 210 kernel_size = load_elf(kernel_filename, NULL, NULL, kernel_entry, 211 kernel_addr, &kernel_top, 1, EM_SPARCV9, 0); 212 if (kernel_size < 0) { 213 *kernel_addr = KERNEL_LOAD_ADDR; 214 *kernel_entry = KERNEL_LOAD_ADDR; 215 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR, 216 RAM_size - KERNEL_LOAD_ADDR, bswap_needed, 217 TARGET_PAGE_SIZE); 218 } 219 if (kernel_size < 0) { 220 kernel_size = load_image_targphys(kernel_filename, 221 KERNEL_LOAD_ADDR, 222 RAM_size - KERNEL_LOAD_ADDR); 223 } 224 if (kernel_size < 0) { 225 fprintf(stderr, "qemu: could not load kernel '%s'\n", 226 kernel_filename); 227 exit(1); 228 } 229 /* load initrd above kernel */ 230 *initrd_size = 0; 231 if (initrd_filename) { 232 *initrd_addr = TARGET_PAGE_ALIGN(kernel_top); 233 234 *initrd_size = load_image_targphys(initrd_filename, 235 *initrd_addr, 236 RAM_size - *initrd_addr); 237 if ((int)*initrd_size < 0) { 238 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", 239 initrd_filename); 240 exit(1); 241 } 242 } 243 if (*initrd_size > 0) { 244 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { 245 ptr = rom_ptr(*kernel_addr + i); 246 if (ldl_p(ptr + 8) == 0x48647253) { /* HdrS */ 247 stl_p(ptr + 24, *initrd_addr + *kernel_addr); 248 stl_p(ptr + 28, *initrd_size); 249 break; 250 } 251 } 252 } 253 } 254 return kernel_size; 255 } 256 257 void cpu_check_irqs(CPUSPARCState *env) 258 { 259 CPUState *cs; 260 uint32_t pil = env->pil_in | 261 (env->softint & ~(SOFTINT_TIMER | SOFTINT_STIMER)); 262 263 /* TT_IVEC has a higher priority (16) than TT_EXTINT (31..17) */ 264 if (env->ivec_status & 0x20) { 265 return; 266 } 267 cs = CPU(sparc_env_get_cpu(env)); 268 /* check if TM or SM in SOFTINT are set 269 setting these also causes interrupt 14 */ 270 if (env->softint & (SOFTINT_TIMER | SOFTINT_STIMER)) { 271 pil |= 1 << 14; 272 } 273 274 /* The bit corresponding to psrpil is (1<< psrpil), the next bit 275 is (2 << psrpil). */ 276 if (pil < (2 << env->psrpil)){ 277 if (cs->interrupt_request & CPU_INTERRUPT_HARD) { 278 CPUIRQ_DPRINTF("Reset CPU IRQ (current interrupt %x)\n", 279 env->interrupt_index); 280 env->interrupt_index = 0; 281 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 282 } 283 return; 284 } 285 286 if (cpu_interrupts_enabled(env)) { 287 288 unsigned int i; 289 290 for (i = 15; i > env->psrpil; i--) { 291 if (pil & (1 << i)) { 292 int old_interrupt = env->interrupt_index; 293 int new_interrupt = TT_EXTINT | i; 294 295 if (unlikely(env->tl > 0 && cpu_tsptr(env)->tt > new_interrupt 296 && ((cpu_tsptr(env)->tt & 0x1f0) == TT_EXTINT))) { 297 CPUIRQ_DPRINTF("Not setting CPU IRQ: TL=%d " 298 "current %x >= pending %x\n", 299 env->tl, cpu_tsptr(env)->tt, new_interrupt); 300 } else if (old_interrupt != new_interrupt) { 301 env->interrupt_index = new_interrupt; 302 CPUIRQ_DPRINTF("Set CPU IRQ %d old=%x new=%x\n", i, 303 old_interrupt, new_interrupt); 304 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 305 } 306 break; 307 } 308 } 309 } else if (cs->interrupt_request & CPU_INTERRUPT_HARD) { 310 CPUIRQ_DPRINTF("Interrupts disabled, pil=%08x pil_in=%08x softint=%08x " 311 "current interrupt %x\n", 312 pil, env->pil_in, env->softint, env->interrupt_index); 313 env->interrupt_index = 0; 314 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 315 } 316 } 317 318 static void cpu_kick_irq(SPARCCPU *cpu) 319 { 320 CPUState *cs = CPU(cpu); 321 CPUSPARCState *env = &cpu->env; 322 323 cs->halted = 0; 324 cpu_check_irqs(env); 325 qemu_cpu_kick(cs); 326 } 327 328 static void cpu_set_ivec_irq(void *opaque, int irq, int level) 329 { 330 SPARCCPU *cpu = opaque; 331 CPUSPARCState *env = &cpu->env; 332 CPUState *cs; 333 334 if (level) { 335 if (!(env->ivec_status & 0x20)) { 336 CPUIRQ_DPRINTF("Raise IVEC IRQ %d\n", irq); 337 cs = CPU(cpu); 338 cs->halted = 0; 339 env->interrupt_index = TT_IVEC; 340 env->ivec_status |= 0x20; 341 env->ivec_data[0] = (0x1f << 6) | irq; 342 env->ivec_data[1] = 0; 343 env->ivec_data[2] = 0; 344 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 345 } 346 } else { 347 if (env->ivec_status & 0x20) { 348 CPUIRQ_DPRINTF("Lower IVEC IRQ %d\n", irq); 349 cs = CPU(cpu); 350 env->ivec_status &= ~0x20; 351 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 352 } 353 } 354 } 355 356 typedef struct ResetData { 357 SPARCCPU *cpu; 358 uint64_t prom_addr; 359 } ResetData; 360 361 void cpu_put_timer(QEMUFile *f, CPUTimer *s) 362 { 363 qemu_put_be32s(f, &s->frequency); 364 qemu_put_be32s(f, &s->disabled); 365 qemu_put_be64s(f, &s->disabled_mask); 366 qemu_put_be32s(f, &s->npt); 367 qemu_put_be64s(f, &s->npt_mask); 368 qemu_put_sbe64s(f, &s->clock_offset); 369 370 timer_put(f, s->qtimer); 371 } 372 373 void cpu_get_timer(QEMUFile *f, CPUTimer *s) 374 { 375 qemu_get_be32s(f, &s->frequency); 376 qemu_get_be32s(f, &s->disabled); 377 qemu_get_be64s(f, &s->disabled_mask); 378 qemu_get_be32s(f, &s->npt); 379 qemu_get_be64s(f, &s->npt_mask); 380 qemu_get_sbe64s(f, &s->clock_offset); 381 382 timer_get(f, s->qtimer); 383 } 384 385 static CPUTimer *cpu_timer_create(const char *name, SPARCCPU *cpu, 386 QEMUBHFunc *cb, uint32_t frequency, 387 uint64_t disabled_mask, uint64_t npt_mask) 388 { 389 CPUTimer *timer = g_malloc0(sizeof (CPUTimer)); 390 391 timer->name = name; 392 timer->frequency = frequency; 393 timer->disabled_mask = disabled_mask; 394 timer->npt_mask = npt_mask; 395 396 timer->disabled = 1; 397 timer->npt = 1; 398 timer->clock_offset = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 399 400 timer->qtimer = timer_new_ns(QEMU_CLOCK_VIRTUAL, cb, cpu); 401 402 return timer; 403 } 404 405 static void cpu_timer_reset(CPUTimer *timer) 406 { 407 timer->disabled = 1; 408 timer->clock_offset = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 409 410 timer_del(timer->qtimer); 411 } 412 413 static void main_cpu_reset(void *opaque) 414 { 415 ResetData *s = (ResetData *)opaque; 416 CPUSPARCState *env = &s->cpu->env; 417 static unsigned int nr_resets; 418 419 cpu_reset(CPU(s->cpu)); 420 421 cpu_timer_reset(env->tick); 422 cpu_timer_reset(env->stick); 423 cpu_timer_reset(env->hstick); 424 425 env->gregs[1] = 0; // Memory start 426 env->gregs[2] = ram_size; // Memory size 427 env->gregs[3] = 0; // Machine description XXX 428 if (nr_resets++ == 0) { 429 /* Power on reset */ 430 env->pc = s->prom_addr + 0x20ULL; 431 } else { 432 env->pc = s->prom_addr + 0x40ULL; 433 } 434 env->npc = env->pc + 4; 435 } 436 437 static void tick_irq(void *opaque) 438 { 439 SPARCCPU *cpu = opaque; 440 CPUSPARCState *env = &cpu->env; 441 442 CPUTimer* timer = env->tick; 443 444 if (timer->disabled) { 445 CPUIRQ_DPRINTF("tick_irq: softint disabled\n"); 446 return; 447 } else { 448 CPUIRQ_DPRINTF("tick: fire\n"); 449 } 450 451 env->softint |= SOFTINT_TIMER; 452 cpu_kick_irq(cpu); 453 } 454 455 static void stick_irq(void *opaque) 456 { 457 SPARCCPU *cpu = opaque; 458 CPUSPARCState *env = &cpu->env; 459 460 CPUTimer* timer = env->stick; 461 462 if (timer->disabled) { 463 CPUIRQ_DPRINTF("stick_irq: softint disabled\n"); 464 return; 465 } else { 466 CPUIRQ_DPRINTF("stick: fire\n"); 467 } 468 469 env->softint |= SOFTINT_STIMER; 470 cpu_kick_irq(cpu); 471 } 472 473 static void hstick_irq(void *opaque) 474 { 475 SPARCCPU *cpu = opaque; 476 CPUSPARCState *env = &cpu->env; 477 478 CPUTimer* timer = env->hstick; 479 480 if (timer->disabled) { 481 CPUIRQ_DPRINTF("hstick_irq: softint disabled\n"); 482 return; 483 } else { 484 CPUIRQ_DPRINTF("hstick: fire\n"); 485 } 486 487 env->softint |= SOFTINT_STIMER; 488 cpu_kick_irq(cpu); 489 } 490 491 static int64_t cpu_to_timer_ticks(int64_t cpu_ticks, uint32_t frequency) 492 { 493 return muldiv64(cpu_ticks, get_ticks_per_sec(), frequency); 494 } 495 496 static uint64_t timer_to_cpu_ticks(int64_t timer_ticks, uint32_t frequency) 497 { 498 return muldiv64(timer_ticks, frequency, get_ticks_per_sec()); 499 } 500 501 void cpu_tick_set_count(CPUTimer *timer, uint64_t count) 502 { 503 uint64_t real_count = count & ~timer->npt_mask; 504 uint64_t npt_bit = count & timer->npt_mask; 505 506 int64_t vm_clock_offset = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - 507 cpu_to_timer_ticks(real_count, timer->frequency); 508 509 TIMER_DPRINTF("%s set_count count=0x%016lx (npt %s) p=%p\n", 510 timer->name, real_count, 511 timer->npt ? "disabled" : "enabled", timer); 512 513 timer->npt = npt_bit ? 1 : 0; 514 timer->clock_offset = vm_clock_offset; 515 } 516 517 uint64_t cpu_tick_get_count(CPUTimer *timer) 518 { 519 uint64_t real_count = timer_to_cpu_ticks( 520 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - timer->clock_offset, 521 timer->frequency); 522 523 TIMER_DPRINTF("%s get_count count=0x%016lx (npt %s) p=%p\n", 524 timer->name, real_count, 525 timer->npt ? "disabled" : "enabled", timer); 526 527 if (timer->npt) { 528 real_count |= timer->npt_mask; 529 } 530 531 return real_count; 532 } 533 534 void cpu_tick_set_limit(CPUTimer *timer, uint64_t limit) 535 { 536 int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 537 538 uint64_t real_limit = limit & ~timer->disabled_mask; 539 timer->disabled = (limit & timer->disabled_mask) ? 1 : 0; 540 541 int64_t expires = cpu_to_timer_ticks(real_limit, timer->frequency) + 542 timer->clock_offset; 543 544 if (expires < now) { 545 expires = now + 1; 546 } 547 548 TIMER_DPRINTF("%s set_limit limit=0x%016lx (%s) p=%p " 549 "called with limit=0x%016lx at 0x%016lx (delta=0x%016lx)\n", 550 timer->name, real_limit, 551 timer->disabled?"disabled":"enabled", 552 timer, limit, 553 timer_to_cpu_ticks(now - timer->clock_offset, 554 timer->frequency), 555 timer_to_cpu_ticks(expires - now, timer->frequency)); 556 557 if (!real_limit) { 558 TIMER_DPRINTF("%s set_limit limit=ZERO - not starting timer\n", 559 timer->name); 560 timer_del(timer->qtimer); 561 } else if (timer->disabled) { 562 timer_del(timer->qtimer); 563 } else { 564 timer_mod(timer->qtimer, expires); 565 } 566 } 567 568 static void isa_irq_handler(void *opaque, int n, int level) 569 { 570 static const int isa_irq_to_ivec[16] = { 571 [1] = 0x29, /* keyboard */ 572 [4] = 0x2b, /* serial */ 573 [6] = 0x27, /* floppy */ 574 [7] = 0x22, /* parallel */ 575 [12] = 0x2a, /* mouse */ 576 }; 577 qemu_irq *irqs = opaque; 578 int ivec; 579 580 assert(n < 16); 581 ivec = isa_irq_to_ivec[n]; 582 EBUS_DPRINTF("Set ISA IRQ %d level %d -> ivec 0x%x\n", n, level, ivec); 583 if (ivec) { 584 qemu_set_irq(irqs[ivec], level); 585 } 586 } 587 588 /* EBUS (Eight bit bus) bridge */ 589 static ISABus * 590 pci_ebus_init(PCIBus *bus, int devfn, qemu_irq *irqs) 591 { 592 qemu_irq *isa_irq; 593 PCIDevice *pci_dev; 594 ISABus *isa_bus; 595 596 pci_dev = pci_create_simple(bus, devfn, "ebus"); 597 isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(pci_dev), "isa.0")); 598 isa_irq = qemu_allocate_irqs(isa_irq_handler, irqs, 16); 599 isa_bus_irqs(isa_bus, isa_irq); 600 return isa_bus; 601 } 602 603 static void pci_ebus_realize(PCIDevice *pci_dev, Error **errp) 604 { 605 EbusState *s = DO_UPCAST(EbusState, pci_dev, pci_dev); 606 607 isa_bus_new(DEVICE(pci_dev), get_system_memory(), 608 pci_address_space_io(pci_dev)); 609 610 pci_dev->config[0x04] = 0x06; // command = bus master, pci mem 611 pci_dev->config[0x05] = 0x00; 612 pci_dev->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error 613 pci_dev->config[0x07] = 0x03; // status = medium devsel 614 pci_dev->config[0x09] = 0x00; // programming i/f 615 pci_dev->config[0x0D] = 0x0a; // latency_timer 616 617 memory_region_init_alias(&s->bar0, OBJECT(s), "bar0", get_system_io(), 618 0, 0x1000000); 619 pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0); 620 memory_region_init_alias(&s->bar1, OBJECT(s), "bar1", get_system_io(), 621 0, 0x4000); 622 pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->bar1); 623 } 624 625 static void ebus_class_init(ObjectClass *klass, void *data) 626 { 627 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 628 629 k->realize = pci_ebus_realize; 630 k->vendor_id = PCI_VENDOR_ID_SUN; 631 k->device_id = PCI_DEVICE_ID_SUN_EBUS; 632 k->revision = 0x01; 633 k->class_id = PCI_CLASS_BRIDGE_OTHER; 634 } 635 636 static const TypeInfo ebus_info = { 637 .name = "ebus", 638 .parent = TYPE_PCI_DEVICE, 639 .instance_size = sizeof(EbusState), 640 .class_init = ebus_class_init, 641 }; 642 643 #define TYPE_OPENPROM "openprom" 644 #define OPENPROM(obj) OBJECT_CHECK(PROMState, (obj), TYPE_OPENPROM) 645 646 typedef struct PROMState { 647 SysBusDevice parent_obj; 648 649 MemoryRegion prom; 650 } PROMState; 651 652 static uint64_t translate_prom_address(void *opaque, uint64_t addr) 653 { 654 hwaddr *base_addr = (hwaddr *)opaque; 655 return addr + *base_addr - PROM_VADDR; 656 } 657 658 /* Boot PROM (OpenBIOS) */ 659 static void prom_init(hwaddr addr, const char *bios_name) 660 { 661 DeviceState *dev; 662 SysBusDevice *s; 663 char *filename; 664 int ret; 665 666 dev = qdev_create(NULL, TYPE_OPENPROM); 667 qdev_init_nofail(dev); 668 s = SYS_BUS_DEVICE(dev); 669 670 sysbus_mmio_map(s, 0, addr); 671 672 /* load boot prom */ 673 if (bios_name == NULL) { 674 bios_name = PROM_FILENAME; 675 } 676 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 677 if (filename) { 678 ret = load_elf(filename, translate_prom_address, &addr, 679 NULL, NULL, NULL, 1, EM_SPARCV9, 0); 680 if (ret < 0 || ret > PROM_SIZE_MAX) { 681 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX); 682 } 683 g_free(filename); 684 } else { 685 ret = -1; 686 } 687 if (ret < 0 || ret > PROM_SIZE_MAX) { 688 fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name); 689 exit(1); 690 } 691 } 692 693 static int prom_init1(SysBusDevice *dev) 694 { 695 PROMState *s = OPENPROM(dev); 696 697 memory_region_init_ram(&s->prom, OBJECT(s), "sun4u.prom", PROM_SIZE_MAX, 698 &error_fatal); 699 vmstate_register_ram_global(&s->prom); 700 memory_region_set_readonly(&s->prom, true); 701 sysbus_init_mmio(dev, &s->prom); 702 return 0; 703 } 704 705 static Property prom_properties[] = { 706 {/* end of property list */}, 707 }; 708 709 static void prom_class_init(ObjectClass *klass, void *data) 710 { 711 DeviceClass *dc = DEVICE_CLASS(klass); 712 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 713 714 k->init = prom_init1; 715 dc->props = prom_properties; 716 } 717 718 static const TypeInfo prom_info = { 719 .name = TYPE_OPENPROM, 720 .parent = TYPE_SYS_BUS_DEVICE, 721 .instance_size = sizeof(PROMState), 722 .class_init = prom_class_init, 723 }; 724 725 726 #define TYPE_SUN4U_MEMORY "memory" 727 #define SUN4U_RAM(obj) OBJECT_CHECK(RamDevice, (obj), TYPE_SUN4U_MEMORY) 728 729 typedef struct RamDevice { 730 SysBusDevice parent_obj; 731 732 MemoryRegion ram; 733 uint64_t size; 734 } RamDevice; 735 736 /* System RAM */ 737 static int ram_init1(SysBusDevice *dev) 738 { 739 RamDevice *d = SUN4U_RAM(dev); 740 741 memory_region_init_ram(&d->ram, OBJECT(d), "sun4u.ram", d->size, 742 &error_fatal); 743 vmstate_register_ram_global(&d->ram); 744 sysbus_init_mmio(dev, &d->ram); 745 return 0; 746 } 747 748 static void ram_init(hwaddr addr, ram_addr_t RAM_size) 749 { 750 DeviceState *dev; 751 SysBusDevice *s; 752 RamDevice *d; 753 754 /* allocate RAM */ 755 dev = qdev_create(NULL, TYPE_SUN4U_MEMORY); 756 s = SYS_BUS_DEVICE(dev); 757 758 d = SUN4U_RAM(dev); 759 d->size = RAM_size; 760 qdev_init_nofail(dev); 761 762 sysbus_mmio_map(s, 0, addr); 763 } 764 765 static Property ram_properties[] = { 766 DEFINE_PROP_UINT64("size", RamDevice, size, 0), 767 DEFINE_PROP_END_OF_LIST(), 768 }; 769 770 static void ram_class_init(ObjectClass *klass, void *data) 771 { 772 DeviceClass *dc = DEVICE_CLASS(klass); 773 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 774 775 k->init = ram_init1; 776 dc->props = ram_properties; 777 } 778 779 static const TypeInfo ram_info = { 780 .name = TYPE_SUN4U_MEMORY, 781 .parent = TYPE_SYS_BUS_DEVICE, 782 .instance_size = sizeof(RamDevice), 783 .class_init = ram_class_init, 784 }; 785 786 static SPARCCPU *cpu_devinit(const char *cpu_model, const struct hwdef *hwdef) 787 { 788 SPARCCPU *cpu; 789 CPUSPARCState *env; 790 ResetData *reset_info; 791 792 uint32_t tick_frequency = 100*1000000; 793 uint32_t stick_frequency = 100*1000000; 794 uint32_t hstick_frequency = 100*1000000; 795 796 if (cpu_model == NULL) { 797 cpu_model = hwdef->default_cpu_model; 798 } 799 cpu = cpu_sparc_init(cpu_model); 800 if (cpu == NULL) { 801 fprintf(stderr, "Unable to find Sparc CPU definition\n"); 802 exit(1); 803 } 804 env = &cpu->env; 805 806 env->tick = cpu_timer_create("tick", cpu, tick_irq, 807 tick_frequency, TICK_INT_DIS, 808 TICK_NPT_MASK); 809 810 env->stick = cpu_timer_create("stick", cpu, stick_irq, 811 stick_frequency, TICK_INT_DIS, 812 TICK_NPT_MASK); 813 814 env->hstick = cpu_timer_create("hstick", cpu, hstick_irq, 815 hstick_frequency, TICK_INT_DIS, 816 TICK_NPT_MASK); 817 818 reset_info = g_malloc0(sizeof(ResetData)); 819 reset_info->cpu = cpu; 820 reset_info->prom_addr = hwdef->prom_addr; 821 qemu_register_reset(main_cpu_reset, reset_info); 822 823 return cpu; 824 } 825 826 static void sun4uv_init(MemoryRegion *address_space_mem, 827 MachineState *machine, 828 const struct hwdef *hwdef) 829 { 830 SPARCCPU *cpu; 831 Nvram *nvram; 832 unsigned int i; 833 uint64_t initrd_addr, initrd_size, kernel_addr, kernel_size, kernel_entry; 834 PCIBus *pci_bus, *pci_bus2, *pci_bus3; 835 ISABus *isa_bus; 836 SysBusDevice *s; 837 qemu_irq *ivec_irqs, *pbm_irqs; 838 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; 839 DriveInfo *fd[MAX_FD]; 840 FWCfgState *fw_cfg; 841 842 /* init CPUs */ 843 cpu = cpu_devinit(machine->cpu_model, hwdef); 844 845 /* set up devices */ 846 ram_init(0, machine->ram_size); 847 848 prom_init(hwdef->prom_addr, bios_name); 849 850 ivec_irqs = qemu_allocate_irqs(cpu_set_ivec_irq, cpu, IVEC_MAX); 851 pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, ivec_irqs, &pci_bus2, 852 &pci_bus3, &pbm_irqs); 853 pci_vga_init(pci_bus); 854 855 // XXX Should be pci_bus3 856 isa_bus = pci_ebus_init(pci_bus, -1, pbm_irqs); 857 858 i = 0; 859 if (hwdef->console_serial_base) { 860 serial_mm_init(address_space_mem, hwdef->console_serial_base, 0, 861 NULL, 115200, serial_hds[i], DEVICE_BIG_ENDIAN); 862 i++; 863 } 864 865 serial_hds_isa_init(isa_bus, MAX_SERIAL_PORTS); 866 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); 867 868 for(i = 0; i < nb_nics; i++) 869 pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL); 870 871 ide_drive_get(hd, ARRAY_SIZE(hd)); 872 873 pci_cmd646_ide_init(pci_bus, hd, 1); 874 875 isa_create_simple(isa_bus, "i8042"); 876 for(i = 0; i < MAX_FD; i++) { 877 fd[i] = drive_get(IF_FLOPPY, 0, i); 878 } 879 fdctrl_init_isa(isa_bus, fd); 880 881 /* Map NVRAM into I/O (ebus) space */ 882 nvram = m48t59_init(NULL, 0, 0, NVRAM_SIZE, 1968, 59); 883 s = SYS_BUS_DEVICE(nvram); 884 memory_region_add_subregion(get_system_io(), 0x2000, 885 sysbus_mmio_get_region(s, 0)); 886 887 initrd_size = 0; 888 initrd_addr = 0; 889 kernel_size = sun4u_load_kernel(machine->kernel_filename, 890 machine->initrd_filename, 891 ram_size, &initrd_size, &initrd_addr, 892 &kernel_addr, &kernel_entry); 893 894 sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", machine->ram_size, 895 machine->boot_order, 896 kernel_addr, kernel_size, 897 machine->kernel_cmdline, 898 initrd_addr, initrd_size, 899 /* XXX: need an option to load a NVRAM image */ 900 0, 901 graphic_width, graphic_height, graphic_depth, 902 (uint8_t *)&nd_table[0].macaddr); 903 904 fw_cfg = fw_cfg_init_io(BIOS_CFG_IOPORT); 905 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus); 906 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 907 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); 908 fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_entry); 909 fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 910 if (machine->kernel_cmdline) { 911 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 912 strlen(machine->kernel_cmdline) + 1); 913 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline); 914 } else { 915 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0); 916 } 917 fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); 918 fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 919 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]); 920 921 fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_WIDTH, graphic_width); 922 fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_HEIGHT, graphic_height); 923 fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_DEPTH, graphic_depth); 924 925 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); 926 } 927 928 enum { 929 sun4u_id = 0, 930 sun4v_id = 64, 931 niagara_id, 932 }; 933 934 static const struct hwdef hwdefs[] = { 935 /* Sun4u generic PC-like machine */ 936 { 937 .default_cpu_model = "TI UltraSparc IIi", 938 .machine_id = sun4u_id, 939 .prom_addr = 0x1fff0000000ULL, 940 .console_serial_base = 0, 941 }, 942 /* Sun4v generic PC-like machine */ 943 { 944 .default_cpu_model = "Sun UltraSparc T1", 945 .machine_id = sun4v_id, 946 .prom_addr = 0x1fff0000000ULL, 947 .console_serial_base = 0, 948 }, 949 /* Sun4v generic Niagara machine */ 950 { 951 .default_cpu_model = "Sun UltraSparc T1", 952 .machine_id = niagara_id, 953 .prom_addr = 0xfff0000000ULL, 954 .console_serial_base = 0xfff0c2c000ULL, 955 }, 956 }; 957 958 /* Sun4u hardware initialisation */ 959 static void sun4u_init(MachineState *machine) 960 { 961 sun4uv_init(get_system_memory(), machine, &hwdefs[0]); 962 } 963 964 /* Sun4v hardware initialisation */ 965 static void sun4v_init(MachineState *machine) 966 { 967 sun4uv_init(get_system_memory(), machine, &hwdefs[1]); 968 } 969 970 /* Niagara hardware initialisation */ 971 static void niagara_init(MachineState *machine) 972 { 973 sun4uv_init(get_system_memory(), machine, &hwdefs[2]); 974 } 975 976 static void sun4u_class_init(ObjectClass *oc, void *data) 977 { 978 MachineClass *mc = MACHINE_CLASS(oc); 979 980 mc->desc = "Sun4u platform"; 981 mc->init = sun4u_init; 982 mc->max_cpus = 1; /* XXX for now */ 983 mc->is_default = 1; 984 mc->default_boot_order = "c"; 985 } 986 987 static const TypeInfo sun4u_type = { 988 .name = MACHINE_TYPE_NAME("sun4u"), 989 .parent = TYPE_MACHINE, 990 .class_init = sun4u_class_init, 991 }; 992 993 static void sun4v_class_init(ObjectClass *oc, void *data) 994 { 995 MachineClass *mc = MACHINE_CLASS(oc); 996 997 mc->desc = "Sun4v platform"; 998 mc->init = sun4v_init; 999 mc->max_cpus = 1; /* XXX for now */ 1000 mc->default_boot_order = "c"; 1001 } 1002 1003 static const TypeInfo sun4v_type = { 1004 .name = MACHINE_TYPE_NAME("sun4v"), 1005 .parent = TYPE_MACHINE, 1006 .class_init = sun4v_class_init, 1007 }; 1008 1009 static void niagara_class_init(ObjectClass *oc, void *data) 1010 { 1011 MachineClass *mc = MACHINE_CLASS(oc); 1012 1013 mc->desc = "Sun4v platform, Niagara"; 1014 mc->init = niagara_init; 1015 mc->max_cpus = 1; /* XXX for now */ 1016 mc->default_boot_order = "c"; 1017 } 1018 1019 static const TypeInfo niagara_type = { 1020 .name = MACHINE_TYPE_NAME("Niagara"), 1021 .parent = TYPE_MACHINE, 1022 .class_init = niagara_class_init, 1023 }; 1024 1025 static void sun4u_register_types(void) 1026 { 1027 type_register_static(&ebus_info); 1028 type_register_static(&prom_info); 1029 type_register_static(&ram_info); 1030 } 1031 1032 static void sun4u_machine_init(void) 1033 { 1034 type_register_static(&sun4u_type); 1035 type_register_static(&sun4v_type); 1036 type_register_static(&niagara_type); 1037 } 1038 1039 type_init(sun4u_register_types) 1040 machine_init(sun4u_machine_init) 1041