1 /* 2 * QEMU Sun4u/Sun4v System Emulator common routines 3 * 4 * Copyright (c) 2005 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 26 #include "qemu/osdep.h" 27 #include "cpu.h" 28 #include "hw/boards.h" 29 #include "hw/sparc/sparc64.h" 30 #include "qemu/timer.h" 31 #include "sysemu/reset.h" 32 #include "trace.h" 33 34 35 #define TICK_MAX 0x7fffffffffffffffULL 36 37 void cpu_check_irqs(CPUSPARCState *env) 38 { 39 CPUState *cs; 40 uint32_t pil = env->pil_in | 41 (env->softint & ~(SOFTINT_TIMER | SOFTINT_STIMER)); 42 43 /* We should be holding the BQL before we mess with IRQs */ 44 g_assert(qemu_mutex_iothread_locked()); 45 46 /* TT_IVEC has a higher priority (16) than TT_EXTINT (31..17) */ 47 if (env->ivec_status & 0x20) { 48 return; 49 } 50 cs = env_cpu(env); 51 /* 52 * check if TM or SM in SOFTINT are set 53 * setting these also causes interrupt 14 54 */ 55 if (env->softint & (SOFTINT_TIMER | SOFTINT_STIMER)) { 56 pil |= 1 << 14; 57 } 58 59 /* 60 * The bit corresponding to psrpil is (1<< psrpil), 61 * the next bit is (2 << psrpil). 62 */ 63 if (pil < (2 << env->psrpil)) { 64 if (cs->interrupt_request & CPU_INTERRUPT_HARD) { 65 trace_sparc64_cpu_check_irqs_reset_irq(env->interrupt_index); 66 env->interrupt_index = 0; 67 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 68 } 69 return; 70 } 71 72 if (cpu_interrupts_enabled(env)) { 73 74 unsigned int i; 75 76 for (i = 15; i > env->psrpil; i--) { 77 if (pil & (1 << i)) { 78 int old_interrupt = env->interrupt_index; 79 int new_interrupt = TT_EXTINT | i; 80 81 if (unlikely(env->tl > 0 && cpu_tsptr(env)->tt > new_interrupt 82 && ((cpu_tsptr(env)->tt & 0x1f0) == TT_EXTINT))) { 83 trace_sparc64_cpu_check_irqs_noset_irq(env->tl, 84 cpu_tsptr(env)->tt, 85 new_interrupt); 86 } else if (old_interrupt != new_interrupt) { 87 env->interrupt_index = new_interrupt; 88 trace_sparc64_cpu_check_irqs_set_irq(i, old_interrupt, 89 new_interrupt); 90 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 91 } 92 break; 93 } 94 } 95 } else if (cs->interrupt_request & CPU_INTERRUPT_HARD) { 96 trace_sparc64_cpu_check_irqs_disabled(pil, env->pil_in, env->softint, 97 env->interrupt_index); 98 env->interrupt_index = 0; 99 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 100 } 101 } 102 103 static void cpu_kick_irq(SPARCCPU *cpu) 104 { 105 CPUState *cs = CPU(cpu); 106 CPUSPARCState *env = &cpu->env; 107 108 cs->halted = 0; 109 cpu_check_irqs(env); 110 qemu_cpu_kick(cs); 111 } 112 113 void sparc64_cpu_set_ivec_irq(void *opaque, int irq, int level) 114 { 115 SPARCCPU *cpu = opaque; 116 CPUSPARCState *env = &cpu->env; 117 CPUState *cs; 118 119 if (level) { 120 if (!(env->ivec_status & 0x20)) { 121 trace_sparc64_cpu_ivec_raise_irq(irq); 122 cs = CPU(cpu); 123 cs->halted = 0; 124 env->interrupt_index = TT_IVEC; 125 env->ivec_status |= 0x20; 126 env->ivec_data[0] = (0x1f << 6) | irq; 127 env->ivec_data[1] = 0; 128 env->ivec_data[2] = 0; 129 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 130 } 131 } else { 132 if (env->ivec_status & 0x20) { 133 trace_sparc64_cpu_ivec_lower_irq(irq); 134 cs = CPU(cpu); 135 env->ivec_status &= ~0x20; 136 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 137 } 138 } 139 } 140 141 typedef struct ResetData { 142 SPARCCPU *cpu; 143 uint64_t prom_addr; 144 } ResetData; 145 146 static CPUTimer *cpu_timer_create(const char *name, SPARCCPU *cpu, 147 QEMUBHFunc *cb, uint32_t frequency, 148 uint64_t disabled_mask, uint64_t npt_mask) 149 { 150 CPUTimer *timer = g_malloc0(sizeof(CPUTimer)); 151 152 timer->name = name; 153 timer->frequency = frequency; 154 timer->disabled_mask = disabled_mask; 155 timer->npt_mask = npt_mask; 156 157 timer->disabled = 1; 158 timer->npt = 1; 159 timer->clock_offset = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 160 161 timer->qtimer = timer_new_ns(QEMU_CLOCK_VIRTUAL, cb, cpu); 162 163 return timer; 164 } 165 166 static void cpu_timer_reset(CPUTimer *timer) 167 { 168 timer->disabled = 1; 169 timer->clock_offset = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 170 171 timer_del(timer->qtimer); 172 } 173 174 static void main_cpu_reset(void *opaque) 175 { 176 ResetData *s = (ResetData *)opaque; 177 CPUSPARCState *env = &s->cpu->env; 178 static unsigned int nr_resets; 179 180 cpu_reset(CPU(s->cpu)); 181 182 cpu_timer_reset(env->tick); 183 cpu_timer_reset(env->stick); 184 cpu_timer_reset(env->hstick); 185 186 env->gregs[1] = 0; /* Memory start */ 187 env->gregs[2] = current_machine->ram_size; /* Memory size */ 188 env->gregs[3] = 0; /* Machine description XXX */ 189 if (nr_resets++ == 0) { 190 /* Power on reset */ 191 env->pc = s->prom_addr + 0x20ULL; 192 } else { 193 env->pc = s->prom_addr + 0x40ULL; 194 } 195 env->npc = env->pc + 4; 196 } 197 198 static void tick_irq(void *opaque) 199 { 200 SPARCCPU *cpu = opaque; 201 CPUSPARCState *env = &cpu->env; 202 203 CPUTimer *timer = env->tick; 204 205 if (timer->disabled) { 206 trace_sparc64_cpu_tick_irq_disabled(); 207 return; 208 } else { 209 trace_sparc64_cpu_tick_irq_fire(); 210 } 211 212 env->softint |= SOFTINT_TIMER; 213 cpu_kick_irq(cpu); 214 } 215 216 static void stick_irq(void *opaque) 217 { 218 SPARCCPU *cpu = opaque; 219 CPUSPARCState *env = &cpu->env; 220 221 CPUTimer *timer = env->stick; 222 223 if (timer->disabled) { 224 trace_sparc64_cpu_stick_irq_disabled(); 225 return; 226 } else { 227 trace_sparc64_cpu_stick_irq_fire(); 228 } 229 230 env->softint |= SOFTINT_STIMER; 231 cpu_kick_irq(cpu); 232 } 233 234 static void hstick_irq(void *opaque) 235 { 236 SPARCCPU *cpu = opaque; 237 CPUSPARCState *env = &cpu->env; 238 239 CPUTimer *timer = env->hstick; 240 241 if (timer->disabled) { 242 trace_sparc64_cpu_hstick_irq_disabled(); 243 return; 244 } else { 245 trace_sparc64_cpu_hstick_irq_fire(); 246 } 247 248 env->softint |= SOFTINT_STIMER; 249 cpu_kick_irq(cpu); 250 } 251 252 static int64_t cpu_to_timer_ticks(int64_t cpu_ticks, uint32_t frequency) 253 { 254 return muldiv64(cpu_ticks, NANOSECONDS_PER_SECOND, frequency); 255 } 256 257 static uint64_t timer_to_cpu_ticks(int64_t timer_ticks, uint32_t frequency) 258 { 259 return muldiv64(timer_ticks, frequency, NANOSECONDS_PER_SECOND); 260 } 261 262 void cpu_tick_set_count(CPUTimer *timer, uint64_t count) 263 { 264 uint64_t real_count = count & ~timer->npt_mask; 265 uint64_t npt_bit = count & timer->npt_mask; 266 267 int64_t vm_clock_offset = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - 268 cpu_to_timer_ticks(real_count, timer->frequency); 269 270 trace_sparc64_cpu_tick_set_count(timer->name, real_count, 271 timer->npt ? "disabled" : "enabled", 272 timer); 273 274 timer->npt = npt_bit ? 1 : 0; 275 timer->clock_offset = vm_clock_offset; 276 } 277 278 uint64_t cpu_tick_get_count(CPUTimer *timer) 279 { 280 uint64_t real_count = timer_to_cpu_ticks( 281 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - timer->clock_offset, 282 timer->frequency); 283 284 trace_sparc64_cpu_tick_get_count(timer->name, real_count, 285 timer->npt ? "disabled" : "enabled", 286 timer); 287 288 if (timer->npt) { 289 real_count |= timer->npt_mask; 290 } 291 292 return real_count; 293 } 294 295 void cpu_tick_set_limit(CPUTimer *timer, uint64_t limit) 296 { 297 int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 298 299 uint64_t real_limit = limit & ~timer->disabled_mask; 300 timer->disabled = (limit & timer->disabled_mask) ? 1 : 0; 301 302 int64_t expires = cpu_to_timer_ticks(real_limit, timer->frequency) + 303 timer->clock_offset; 304 305 if (expires < now) { 306 expires = now + 1; 307 } 308 309 trace_sparc64_cpu_tick_set_limit(timer->name, real_limit, 310 timer->disabled ? "disabled" : "enabled", 311 timer, limit, 312 timer_to_cpu_ticks( 313 now - timer->clock_offset, 314 timer->frequency 315 ), 316 timer_to_cpu_ticks( 317 expires - now, timer->frequency 318 )); 319 320 if (!real_limit) { 321 trace_sparc64_cpu_tick_set_limit_zero(timer->name); 322 timer_del(timer->qtimer); 323 } else if (timer->disabled) { 324 timer_del(timer->qtimer); 325 } else { 326 timer_mod(timer->qtimer, expires); 327 } 328 } 329 330 SPARCCPU *sparc64_cpu_devinit(const char *cpu_type, uint64_t prom_addr) 331 { 332 SPARCCPU *cpu; 333 CPUSPARCState *env; 334 ResetData *reset_info; 335 336 uint32_t tick_frequency = 100 * 1000000; 337 uint32_t stick_frequency = 100 * 1000000; 338 uint32_t hstick_frequency = 100 * 1000000; 339 340 cpu = SPARC_CPU(cpu_create(cpu_type)); 341 qdev_init_gpio_in_named(DEVICE(cpu), sparc64_cpu_set_ivec_irq, 342 "ivec-irq", IVEC_MAX); 343 env = &cpu->env; 344 345 env->tick = cpu_timer_create("tick", cpu, tick_irq, 346 tick_frequency, TICK_INT_DIS, 347 TICK_NPT_MASK); 348 349 env->stick = cpu_timer_create("stick", cpu, stick_irq, 350 stick_frequency, TICK_INT_DIS, 351 TICK_NPT_MASK); 352 353 env->hstick = cpu_timer_create("hstick", cpu, hstick_irq, 354 hstick_frequency, TICK_INT_DIS, 355 TICK_NPT_MASK); 356 357 reset_info = g_malloc0(sizeof(ResetData)); 358 reset_info->cpu = cpu; 359 reset_info->prom_addr = prom_addr; 360 qemu_register_reset(main_cpu_reset, reset_info); 361 362 return cpu; 363 } 364