1 /* 2 * QEMU Sun4u/Sun4v System Emulator common routines 3 * 4 * Copyright (c) 2005 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 26 #include "qemu/osdep.h" 27 #include "cpu.h" 28 #include "hw/char/serial.h" 29 #include "hw/sparc/sparc64.h" 30 #include "qemu/timer.h" 31 32 33 //#define DEBUG_IRQ 34 //#define DEBUG_TIMER 35 36 #ifdef DEBUG_IRQ 37 #define CPUIRQ_DPRINTF(fmt, ...) \ 38 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0) 39 #else 40 #define CPUIRQ_DPRINTF(fmt, ...) 41 #endif 42 43 #ifdef DEBUG_TIMER 44 #define TIMER_DPRINTF(fmt, ...) \ 45 do { printf("TIMER: " fmt , ## __VA_ARGS__); } while (0) 46 #else 47 #define TIMER_DPRINTF(fmt, ...) 48 #endif 49 50 #define TICK_MAX 0x7fffffffffffffffULL 51 52 void cpu_check_irqs(CPUSPARCState *env) 53 { 54 CPUState *cs; 55 uint32_t pil = env->pil_in | 56 (env->softint & ~(SOFTINT_TIMER | SOFTINT_STIMER)); 57 58 /* We should be holding the BQL before we mess with IRQs */ 59 g_assert(qemu_mutex_iothread_locked()); 60 61 /* TT_IVEC has a higher priority (16) than TT_EXTINT (31..17) */ 62 if (env->ivec_status & 0x20) { 63 return; 64 } 65 cs = CPU(sparc_env_get_cpu(env)); 66 /* check if TM or SM in SOFTINT are set 67 setting these also causes interrupt 14 */ 68 if (env->softint & (SOFTINT_TIMER | SOFTINT_STIMER)) { 69 pil |= 1 << 14; 70 } 71 72 /* The bit corresponding to psrpil is (1<< psrpil), the next bit 73 is (2 << psrpil). */ 74 if (pil < (2 << env->psrpil)) { 75 if (cs->interrupt_request & CPU_INTERRUPT_HARD) { 76 CPUIRQ_DPRINTF("Reset CPU IRQ (current interrupt %x)\n", 77 env->interrupt_index); 78 env->interrupt_index = 0; 79 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 80 } 81 return; 82 } 83 84 if (cpu_interrupts_enabled(env)) { 85 86 unsigned int i; 87 88 for (i = 15; i > env->psrpil; i--) { 89 if (pil & (1 << i)) { 90 int old_interrupt = env->interrupt_index; 91 int new_interrupt = TT_EXTINT | i; 92 93 if (unlikely(env->tl > 0 && cpu_tsptr(env)->tt > new_interrupt 94 && ((cpu_tsptr(env)->tt & 0x1f0) == TT_EXTINT))) { 95 CPUIRQ_DPRINTF("Not setting CPU IRQ: TL=%d " 96 "current %x >= pending %x\n", 97 env->tl, cpu_tsptr(env)->tt, new_interrupt); 98 } else if (old_interrupt != new_interrupt) { 99 env->interrupt_index = new_interrupt; 100 CPUIRQ_DPRINTF("Set CPU IRQ %d old=%x new=%x\n", i, 101 old_interrupt, new_interrupt); 102 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 103 } 104 break; 105 } 106 } 107 } else if (cs->interrupt_request & CPU_INTERRUPT_HARD) { 108 CPUIRQ_DPRINTF("Interrupts disabled, pil=%08x pil_in=%08x softint=%08x " 109 "current interrupt %x\n", 110 pil, env->pil_in, env->softint, env->interrupt_index); 111 env->interrupt_index = 0; 112 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 113 } 114 } 115 116 static void cpu_kick_irq(SPARCCPU *cpu) 117 { 118 CPUState *cs = CPU(cpu); 119 CPUSPARCState *env = &cpu->env; 120 121 cs->halted = 0; 122 cpu_check_irqs(env); 123 qemu_cpu_kick(cs); 124 } 125 126 void sparc64_cpu_set_ivec_irq(void *opaque, int irq, int level) 127 { 128 SPARCCPU *cpu = opaque; 129 CPUSPARCState *env = &cpu->env; 130 CPUState *cs; 131 132 if (level) { 133 if (!(env->ivec_status & 0x20)) { 134 CPUIRQ_DPRINTF("Raise IVEC IRQ %d\n", irq); 135 cs = CPU(cpu); 136 cs->halted = 0; 137 env->interrupt_index = TT_IVEC; 138 env->ivec_status |= 0x20; 139 env->ivec_data[0] = (0x1f << 6) | irq; 140 env->ivec_data[1] = 0; 141 env->ivec_data[2] = 0; 142 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 143 } 144 } else { 145 if (env->ivec_status & 0x20) { 146 CPUIRQ_DPRINTF("Lower IVEC IRQ %d\n", irq); 147 cs = CPU(cpu); 148 env->ivec_status &= ~0x20; 149 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 150 } 151 } 152 } 153 154 typedef struct ResetData { 155 SPARCCPU *cpu; 156 uint64_t prom_addr; 157 } ResetData; 158 159 static CPUTimer *cpu_timer_create(const char *name, SPARCCPU *cpu, 160 QEMUBHFunc *cb, uint32_t frequency, 161 uint64_t disabled_mask, uint64_t npt_mask) 162 { 163 CPUTimer *timer = g_malloc0(sizeof(CPUTimer)); 164 165 timer->name = name; 166 timer->frequency = frequency; 167 timer->disabled_mask = disabled_mask; 168 timer->npt_mask = npt_mask; 169 170 timer->disabled = 1; 171 timer->npt = 1; 172 timer->clock_offset = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 173 174 timer->qtimer = timer_new_ns(QEMU_CLOCK_VIRTUAL, cb, cpu); 175 176 return timer; 177 } 178 179 static void cpu_timer_reset(CPUTimer *timer) 180 { 181 timer->disabled = 1; 182 timer->clock_offset = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 183 184 timer_del(timer->qtimer); 185 } 186 187 static void main_cpu_reset(void *opaque) 188 { 189 ResetData *s = (ResetData *)opaque; 190 CPUSPARCState *env = &s->cpu->env; 191 static unsigned int nr_resets; 192 193 cpu_reset(CPU(s->cpu)); 194 195 cpu_timer_reset(env->tick); 196 cpu_timer_reset(env->stick); 197 cpu_timer_reset(env->hstick); 198 199 env->gregs[1] = 0; /* Memory start */ 200 env->gregs[2] = ram_size; /* Memory size */ 201 env->gregs[3] = 0; /* Machine description XXX */ 202 if (nr_resets++ == 0) { 203 /* Power on reset */ 204 env->pc = s->prom_addr + 0x20ULL; 205 } else { 206 env->pc = s->prom_addr + 0x40ULL; 207 } 208 env->npc = env->pc + 4; 209 } 210 211 static void tick_irq(void *opaque) 212 { 213 SPARCCPU *cpu = opaque; 214 CPUSPARCState *env = &cpu->env; 215 216 CPUTimer *timer = env->tick; 217 218 if (timer->disabled) { 219 CPUIRQ_DPRINTF("tick_irq: softint disabled\n"); 220 return; 221 } else { 222 CPUIRQ_DPRINTF("tick: fire\n"); 223 } 224 225 env->softint |= SOFTINT_TIMER; 226 cpu_kick_irq(cpu); 227 } 228 229 static void stick_irq(void *opaque) 230 { 231 SPARCCPU *cpu = opaque; 232 CPUSPARCState *env = &cpu->env; 233 234 CPUTimer *timer = env->stick; 235 236 if (timer->disabled) { 237 CPUIRQ_DPRINTF("stick_irq: softint disabled\n"); 238 return; 239 } else { 240 CPUIRQ_DPRINTF("stick: fire\n"); 241 } 242 243 env->softint |= SOFTINT_STIMER; 244 cpu_kick_irq(cpu); 245 } 246 247 static void hstick_irq(void *opaque) 248 { 249 SPARCCPU *cpu = opaque; 250 CPUSPARCState *env = &cpu->env; 251 252 CPUTimer *timer = env->hstick; 253 254 if (timer->disabled) { 255 CPUIRQ_DPRINTF("hstick_irq: softint disabled\n"); 256 return; 257 } else { 258 CPUIRQ_DPRINTF("hstick: fire\n"); 259 } 260 261 env->softint |= SOFTINT_STIMER; 262 cpu_kick_irq(cpu); 263 } 264 265 static int64_t cpu_to_timer_ticks(int64_t cpu_ticks, uint32_t frequency) 266 { 267 return muldiv64(cpu_ticks, NANOSECONDS_PER_SECOND, frequency); 268 } 269 270 static uint64_t timer_to_cpu_ticks(int64_t timer_ticks, uint32_t frequency) 271 { 272 return muldiv64(timer_ticks, frequency, NANOSECONDS_PER_SECOND); 273 } 274 275 void cpu_tick_set_count(CPUTimer *timer, uint64_t count) 276 { 277 uint64_t real_count = count & ~timer->npt_mask; 278 uint64_t npt_bit = count & timer->npt_mask; 279 280 int64_t vm_clock_offset = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - 281 cpu_to_timer_ticks(real_count, timer->frequency); 282 283 TIMER_DPRINTF("%s set_count count=0x%016lx (npt %s) p=%p\n", 284 timer->name, real_count, 285 timer->npt ? "disabled" : "enabled", timer); 286 287 timer->npt = npt_bit ? 1 : 0; 288 timer->clock_offset = vm_clock_offset; 289 } 290 291 uint64_t cpu_tick_get_count(CPUTimer *timer) 292 { 293 uint64_t real_count = timer_to_cpu_ticks( 294 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - timer->clock_offset, 295 timer->frequency); 296 297 TIMER_DPRINTF("%s get_count count=0x%016lx (npt %s) p=%p\n", 298 timer->name, real_count, 299 timer->npt ? "disabled" : "enabled", timer); 300 301 if (timer->npt) { 302 real_count |= timer->npt_mask; 303 } 304 305 return real_count; 306 } 307 308 void cpu_tick_set_limit(CPUTimer *timer, uint64_t limit) 309 { 310 int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 311 312 uint64_t real_limit = limit & ~timer->disabled_mask; 313 timer->disabled = (limit & timer->disabled_mask) ? 1 : 0; 314 315 int64_t expires = cpu_to_timer_ticks(real_limit, timer->frequency) + 316 timer->clock_offset; 317 318 if (expires < now) { 319 expires = now + 1; 320 } 321 322 TIMER_DPRINTF("%s set_limit limit=0x%016lx (%s) p=%p " 323 "called with limit=0x%016lx at 0x%016lx (delta=0x%016lx)\n", 324 timer->name, real_limit, 325 timer->disabled ? "disabled" : "enabled", 326 timer, limit, 327 timer_to_cpu_ticks(now - timer->clock_offset, 328 timer->frequency), 329 timer_to_cpu_ticks(expires - now, timer->frequency)); 330 331 if (!real_limit) { 332 TIMER_DPRINTF("%s set_limit limit=ZERO - not starting timer\n", 333 timer->name); 334 timer_del(timer->qtimer); 335 } else if (timer->disabled) { 336 timer_del(timer->qtimer); 337 } else { 338 timer_mod(timer->qtimer, expires); 339 } 340 } 341 342 SPARCCPU *sparc64_cpu_devinit(const char *cpu_model, 343 const char *default_cpu_model, uint64_t prom_addr) 344 { 345 SPARCCPU *cpu; 346 CPUSPARCState *env; 347 ResetData *reset_info; 348 349 uint32_t tick_frequency = 100 * 1000000; 350 uint32_t stick_frequency = 100 * 1000000; 351 uint32_t hstick_frequency = 100 * 1000000; 352 353 if (cpu_model == NULL) { 354 cpu_model = default_cpu_model; 355 } 356 cpu = SPARC_CPU(cpu_generic_init(TYPE_SPARC_CPU, cpu_model)); 357 if (cpu == NULL) { 358 fprintf(stderr, "Unable to find Sparc CPU definition\n"); 359 exit(1); 360 } 361 env = &cpu->env; 362 363 env->tick = cpu_timer_create("tick", cpu, tick_irq, 364 tick_frequency, TICK_INT_DIS, 365 TICK_NPT_MASK); 366 367 env->stick = cpu_timer_create("stick", cpu, stick_irq, 368 stick_frequency, TICK_INT_DIS, 369 TICK_NPT_MASK); 370 371 env->hstick = cpu_timer_create("hstick", cpu, hstick_irq, 372 hstick_frequency, TICK_INT_DIS, 373 TICK_NPT_MASK); 374 375 reset_info = g_malloc0(sizeof(ResetData)); 376 reset_info->cpu = cpu; 377 reset_info->prom_addr = prom_addr; 378 qemu_register_reset(main_cpu_reset, reset_info); 379 380 return cpu; 381 } 382