1 /* 2 * QEMU Sun4u/Sun4v System Emulator common routines 3 * 4 * Copyright (c) 2005 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 26 #include "qemu/osdep.h" 27 #include "cpu.h" 28 #include "hw/char/serial.h" 29 #include "hw/sparc/sparc64.h" 30 #include "qemu/timer.h" 31 #include "trace.h" 32 33 34 #define TICK_MAX 0x7fffffffffffffffULL 35 36 void cpu_check_irqs(CPUSPARCState *env) 37 { 38 CPUState *cs; 39 uint32_t pil = env->pil_in | 40 (env->softint & ~(SOFTINT_TIMER | SOFTINT_STIMER)); 41 42 /* We should be holding the BQL before we mess with IRQs */ 43 g_assert(qemu_mutex_iothread_locked()); 44 45 /* TT_IVEC has a higher priority (16) than TT_EXTINT (31..17) */ 46 if (env->ivec_status & 0x20) { 47 return; 48 } 49 cs = CPU(sparc_env_get_cpu(env)); 50 /* check if TM or SM in SOFTINT are set 51 setting these also causes interrupt 14 */ 52 if (env->softint & (SOFTINT_TIMER | SOFTINT_STIMER)) { 53 pil |= 1 << 14; 54 } 55 56 /* The bit corresponding to psrpil is (1<< psrpil), the next bit 57 is (2 << psrpil). */ 58 if (pil < (2 << env->psrpil)) { 59 if (cs->interrupt_request & CPU_INTERRUPT_HARD) { 60 trace_sparc64_cpu_check_irqs_reset_irq(env->interrupt_index); 61 env->interrupt_index = 0; 62 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 63 } 64 return; 65 } 66 67 if (cpu_interrupts_enabled(env)) { 68 69 unsigned int i; 70 71 for (i = 15; i > env->psrpil; i--) { 72 if (pil & (1 << i)) { 73 int old_interrupt = env->interrupt_index; 74 int new_interrupt = TT_EXTINT | i; 75 76 if (unlikely(env->tl > 0 && cpu_tsptr(env)->tt > new_interrupt 77 && ((cpu_tsptr(env)->tt & 0x1f0) == TT_EXTINT))) { 78 trace_sparc64_cpu_check_irqs_noset_irq(env->tl, 79 cpu_tsptr(env)->tt, 80 new_interrupt); 81 } else if (old_interrupt != new_interrupt) { 82 env->interrupt_index = new_interrupt; 83 trace_sparc64_cpu_check_irqs_set_irq(i, old_interrupt, 84 new_interrupt); 85 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 86 } 87 break; 88 } 89 } 90 } else if (cs->interrupt_request & CPU_INTERRUPT_HARD) { 91 trace_sparc64_cpu_check_irqs_disabled(pil, env->pil_in, env->softint, 92 env->interrupt_index); 93 env->interrupt_index = 0; 94 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 95 } 96 } 97 98 static void cpu_kick_irq(SPARCCPU *cpu) 99 { 100 CPUState *cs = CPU(cpu); 101 CPUSPARCState *env = &cpu->env; 102 103 cs->halted = 0; 104 cpu_check_irqs(env); 105 qemu_cpu_kick(cs); 106 } 107 108 void sparc64_cpu_set_ivec_irq(void *opaque, int irq, int level) 109 { 110 SPARCCPU *cpu = opaque; 111 CPUSPARCState *env = &cpu->env; 112 CPUState *cs; 113 114 if (level) { 115 if (!(env->ivec_status & 0x20)) { 116 trace_sparc64_cpu_ivec_raise_irq(irq); 117 cs = CPU(cpu); 118 cs->halted = 0; 119 env->interrupt_index = TT_IVEC; 120 env->ivec_status |= 0x20; 121 env->ivec_data[0] = (0x1f << 6) | irq; 122 env->ivec_data[1] = 0; 123 env->ivec_data[2] = 0; 124 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 125 } 126 } else { 127 if (env->ivec_status & 0x20) { 128 trace_sparc64_cpu_ivec_lower_irq(irq); 129 cs = CPU(cpu); 130 env->ivec_status &= ~0x20; 131 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 132 } 133 } 134 } 135 136 typedef struct ResetData { 137 SPARCCPU *cpu; 138 uint64_t prom_addr; 139 } ResetData; 140 141 static CPUTimer *cpu_timer_create(const char *name, SPARCCPU *cpu, 142 QEMUBHFunc *cb, uint32_t frequency, 143 uint64_t disabled_mask, uint64_t npt_mask) 144 { 145 CPUTimer *timer = g_malloc0(sizeof(CPUTimer)); 146 147 timer->name = name; 148 timer->frequency = frequency; 149 timer->disabled_mask = disabled_mask; 150 timer->npt_mask = npt_mask; 151 152 timer->disabled = 1; 153 timer->npt = 1; 154 timer->clock_offset = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 155 156 timer->qtimer = timer_new_ns(QEMU_CLOCK_VIRTUAL, cb, cpu); 157 158 return timer; 159 } 160 161 static void cpu_timer_reset(CPUTimer *timer) 162 { 163 timer->disabled = 1; 164 timer->clock_offset = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 165 166 timer_del(timer->qtimer); 167 } 168 169 static void main_cpu_reset(void *opaque) 170 { 171 ResetData *s = (ResetData *)opaque; 172 CPUSPARCState *env = &s->cpu->env; 173 static unsigned int nr_resets; 174 175 cpu_reset(CPU(s->cpu)); 176 177 cpu_timer_reset(env->tick); 178 cpu_timer_reset(env->stick); 179 cpu_timer_reset(env->hstick); 180 181 env->gregs[1] = 0; /* Memory start */ 182 env->gregs[2] = ram_size; /* Memory size */ 183 env->gregs[3] = 0; /* Machine description XXX */ 184 if (nr_resets++ == 0) { 185 /* Power on reset */ 186 env->pc = s->prom_addr + 0x20ULL; 187 } else { 188 env->pc = s->prom_addr + 0x40ULL; 189 } 190 env->npc = env->pc + 4; 191 } 192 193 static void tick_irq(void *opaque) 194 { 195 SPARCCPU *cpu = opaque; 196 CPUSPARCState *env = &cpu->env; 197 198 CPUTimer *timer = env->tick; 199 200 if (timer->disabled) { 201 trace_sparc64_cpu_tick_irq_disabled(); 202 return; 203 } else { 204 trace_sparc64_cpu_tick_irq_fire(); 205 } 206 207 env->softint |= SOFTINT_TIMER; 208 cpu_kick_irq(cpu); 209 } 210 211 static void stick_irq(void *opaque) 212 { 213 SPARCCPU *cpu = opaque; 214 CPUSPARCState *env = &cpu->env; 215 216 CPUTimer *timer = env->stick; 217 218 if (timer->disabled) { 219 trace_sparc64_cpu_stick_irq_disabled(); 220 return; 221 } else { 222 trace_sparc64_cpu_stick_irq_fire(); 223 } 224 225 env->softint |= SOFTINT_STIMER; 226 cpu_kick_irq(cpu); 227 } 228 229 static void hstick_irq(void *opaque) 230 { 231 SPARCCPU *cpu = opaque; 232 CPUSPARCState *env = &cpu->env; 233 234 CPUTimer *timer = env->hstick; 235 236 if (timer->disabled) { 237 trace_sparc64_cpu_hstick_irq_disabled(); 238 return; 239 } else { 240 trace_sparc64_cpu_hstick_irq_fire(); 241 } 242 243 env->softint |= SOFTINT_STIMER; 244 cpu_kick_irq(cpu); 245 } 246 247 static int64_t cpu_to_timer_ticks(int64_t cpu_ticks, uint32_t frequency) 248 { 249 return muldiv64(cpu_ticks, NANOSECONDS_PER_SECOND, frequency); 250 } 251 252 static uint64_t timer_to_cpu_ticks(int64_t timer_ticks, uint32_t frequency) 253 { 254 return muldiv64(timer_ticks, frequency, NANOSECONDS_PER_SECOND); 255 } 256 257 void cpu_tick_set_count(CPUTimer *timer, uint64_t count) 258 { 259 uint64_t real_count = count & ~timer->npt_mask; 260 uint64_t npt_bit = count & timer->npt_mask; 261 262 int64_t vm_clock_offset = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - 263 cpu_to_timer_ticks(real_count, timer->frequency); 264 265 trace_sparc64_cpu_tick_set_count(timer->name, real_count, 266 timer->npt ? "disabled" : "enabled", 267 timer); 268 269 timer->npt = npt_bit ? 1 : 0; 270 timer->clock_offset = vm_clock_offset; 271 } 272 273 uint64_t cpu_tick_get_count(CPUTimer *timer) 274 { 275 uint64_t real_count = timer_to_cpu_ticks( 276 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - timer->clock_offset, 277 timer->frequency); 278 279 trace_sparc64_cpu_tick_get_count(timer->name, real_count, 280 timer->npt ? "disabled" : "enabled", 281 timer); 282 283 if (timer->npt) { 284 real_count |= timer->npt_mask; 285 } 286 287 return real_count; 288 } 289 290 void cpu_tick_set_limit(CPUTimer *timer, uint64_t limit) 291 { 292 int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 293 294 uint64_t real_limit = limit & ~timer->disabled_mask; 295 timer->disabled = (limit & timer->disabled_mask) ? 1 : 0; 296 297 int64_t expires = cpu_to_timer_ticks(real_limit, timer->frequency) + 298 timer->clock_offset; 299 300 if (expires < now) { 301 expires = now + 1; 302 } 303 304 trace_sparc64_cpu_tick_set_limit(timer->name, real_limit, 305 timer->disabled ? "disabled" : "enabled", 306 timer, limit, 307 timer_to_cpu_ticks( 308 now - timer->clock_offset, 309 timer->frequency 310 ), 311 timer_to_cpu_ticks( 312 expires - now, timer->frequency 313 )); 314 315 if (!real_limit) { 316 trace_sparc64_cpu_tick_set_limit_zero(timer->name); 317 timer_del(timer->qtimer); 318 } else if (timer->disabled) { 319 timer_del(timer->qtimer); 320 } else { 321 timer_mod(timer->qtimer, expires); 322 } 323 } 324 325 SPARCCPU *sparc64_cpu_devinit(const char *cpu_type, uint64_t prom_addr) 326 { 327 SPARCCPU *cpu; 328 CPUSPARCState *env; 329 ResetData *reset_info; 330 331 uint32_t tick_frequency = 100 * 1000000; 332 uint32_t stick_frequency = 100 * 1000000; 333 uint32_t hstick_frequency = 100 * 1000000; 334 335 cpu = SPARC_CPU(cpu_create(cpu_type)); 336 qdev_init_gpio_in_named(DEVICE(cpu), sparc64_cpu_set_ivec_irq, 337 "ivec-irq", IVEC_MAX); 338 env = &cpu->env; 339 340 env->tick = cpu_timer_create("tick", cpu, tick_irq, 341 tick_frequency, TICK_INT_DIS, 342 TICK_NPT_MASK); 343 344 env->stick = cpu_timer_create("stick", cpu, stick_irq, 345 stick_frequency, TICK_INT_DIS, 346 TICK_NPT_MASK); 347 348 env->hstick = cpu_timer_create("hstick", cpu, hstick_irq, 349 hstick_frequency, TICK_INT_DIS, 350 TICK_NPT_MASK); 351 352 reset_info = g_malloc0(sizeof(ResetData)); 353 reset_info->cpu = cpu; 354 reset_info->prom_addr = prom_addr; 355 qemu_register_reset(main_cpu_reset, reset_info); 356 357 return cpu; 358 } 359