1 /* 2 * QEMU Sun4v/Niagara System Emulator 3 * 4 * Copyright (c) 2016 Artyom Tarasenko 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "block/block_int-common.h" 27 #include "qemu/units.h" 28 #include "cpu.h" 29 #include "hw/boards.h" 30 #include "hw/char/serial.h" 31 #include "hw/misc/unimp.h" 32 #include "hw/loader.h" 33 #include "hw/sparc/sparc64.h" 34 #include "hw/rtc/sun4v-rtc.h" 35 #include "sysemu/block-backend.h" 36 #include "qemu/error-report.h" 37 #include "sysemu/qtest.h" 38 #include "sysemu/sysemu.h" 39 #include "qapi/error.h" 40 41 typedef struct NiagaraBoardState { 42 MemoryRegion hv_ram; 43 MemoryRegion nvram; 44 MemoryRegion md_rom; 45 MemoryRegion hv_rom; 46 MemoryRegion vdisk_ram; 47 MemoryRegion prom; 48 } NiagaraBoardState; 49 50 #define NIAGARA_HV_RAM_BASE 0x100000ULL 51 #define NIAGARA_HV_RAM_SIZE 0x3f00000ULL /* 63 MiB */ 52 53 #define NIAGARA_PARTITION_RAM_BASE 0x80000000ULL 54 55 #define NIAGARA_UART_BASE 0x1f10000000ULL 56 57 #define NIAGARA_NVRAM_BASE 0x1f11000000ULL 58 #define NIAGARA_NVRAM_SIZE 0x2000 59 60 #define NIAGARA_MD_ROM_BASE 0x1f12000000ULL 61 #define NIAGARA_MD_ROM_SIZE 0x2000 62 63 #define NIAGARA_HV_ROM_BASE 0x1f12080000ULL 64 #define NIAGARA_HV_ROM_SIZE 0x2000 65 66 #define NIAGARA_IOBBASE 0x9800000000ULL 67 #define NIAGARA_IOBSIZE 0x0100000000ULL 68 69 #define NIAGARA_VDISK_BASE 0x1f40000000ULL 70 #define NIAGARA_RTC_BASE 0xfff0c1fff8ULL 71 72 /* Firmware layout 73 * 74 * |------------------| 75 * | openboot.bin | 76 * |------------------| PROM_ADDR + OBP_OFFSET 77 * | q.bin | 78 * |------------------| PROM_ADDR + Q_OFFSET 79 * | reset.bin | 80 * |------------------| PROM_ADDR 81 */ 82 #define NIAGARA_PROM_BASE 0xfff0000000ULL 83 #define NIAGARA_Q_OFFSET 0x10000ULL 84 #define NIAGARA_OBP_OFFSET 0x80000ULL 85 #define PROM_SIZE_MAX (4 * MiB) 86 87 static void add_rom_or_fail(const char *file, const hwaddr addr) 88 { 89 /* XXX remove qtest_enabled() check once firmware files are 90 * in the qemu tree 91 */ 92 if (!qtest_enabled() && rom_add_file_fixed(file, addr, -1)) { 93 error_report("Unable to load a firmware for -M niagara"); 94 exit(1); 95 } 96 97 } 98 /* Niagara hardware initialisation */ 99 static void niagara_init(MachineState *machine) 100 { 101 NiagaraBoardState *s = g_new(NiagaraBoardState, 1); 102 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 103 MemoryRegion *sysmem = get_system_memory(); 104 105 /* init CPUs */ 106 sparc64_cpu_devinit(machine->cpu_type, NIAGARA_PROM_BASE); 107 /* set up devices */ 108 memory_region_init_ram(&s->hv_ram, NULL, "sun4v-hv.ram", 109 NIAGARA_HV_RAM_SIZE, &error_fatal); 110 memory_region_add_subregion(sysmem, NIAGARA_HV_RAM_BASE, &s->hv_ram); 111 112 memory_region_add_subregion(sysmem, NIAGARA_PARTITION_RAM_BASE, 113 machine->ram); 114 115 memory_region_init_ram(&s->nvram, NULL, "sun4v.nvram", NIAGARA_NVRAM_SIZE, 116 &error_fatal); 117 memory_region_add_subregion(sysmem, NIAGARA_NVRAM_BASE, &s->nvram); 118 memory_region_init_ram(&s->md_rom, NULL, "sun4v-md.rom", 119 NIAGARA_MD_ROM_SIZE, &error_fatal); 120 memory_region_add_subregion(sysmem, NIAGARA_MD_ROM_BASE, &s->md_rom); 121 memory_region_init_ram(&s->hv_rom, NULL, "sun4v-hv.rom", 122 NIAGARA_HV_ROM_SIZE, &error_fatal); 123 memory_region_add_subregion(sysmem, NIAGARA_HV_ROM_BASE, &s->hv_rom); 124 memory_region_init_ram(&s->prom, NULL, "sun4v.prom", PROM_SIZE_MAX, 125 &error_fatal); 126 memory_region_add_subregion(sysmem, NIAGARA_PROM_BASE, &s->prom); 127 128 add_rom_or_fail("nvram1", NIAGARA_NVRAM_BASE); 129 add_rom_or_fail("1up-md.bin", NIAGARA_MD_ROM_BASE); 130 add_rom_or_fail("1up-hv.bin", NIAGARA_HV_ROM_BASE); 131 132 add_rom_or_fail("reset.bin", NIAGARA_PROM_BASE); 133 add_rom_or_fail("q.bin", NIAGARA_PROM_BASE + NIAGARA_Q_OFFSET); 134 add_rom_or_fail("openboot.bin", NIAGARA_PROM_BASE + NIAGARA_OBP_OFFSET); 135 136 /* the virtual ramdisk is kind of initrd, but it resides 137 outside of the partition RAM */ 138 if (dinfo) { 139 BlockBackend *blk = blk_by_legacy_dinfo(dinfo); 140 int size = blk_getlength(blk); 141 if (size > 0) { 142 memory_region_init_ram(&s->vdisk_ram, NULL, "sun4v_vdisk.ram", size, 143 &error_fatal); 144 memory_region_add_subregion(get_system_memory(), 145 NIAGARA_VDISK_BASE, &s->vdisk_ram); 146 dinfo->is_default = 1; 147 rom_add_file_fixed(blk_bs(blk)->filename, NIAGARA_VDISK_BASE, -1); 148 } else { 149 error_report("could not load ram disk '%s'", 150 blk_bs(blk)->filename); 151 exit(1); 152 } 153 } 154 serial_mm_init(sysmem, NIAGARA_UART_BASE, 0, NULL, 155 115200, serial_hd(0), DEVICE_BIG_ENDIAN); 156 create_unimplemented_device("sun4v-iob", NIAGARA_IOBBASE, NIAGARA_IOBSIZE); 157 sun4v_rtc_init(NIAGARA_RTC_BASE); 158 } 159 160 static void niagara_class_init(ObjectClass *oc, void *data) 161 { 162 MachineClass *mc = MACHINE_CLASS(oc); 163 164 mc->desc = "Sun4v platform, Niagara"; 165 mc->init = niagara_init; 166 mc->max_cpus = 1; /* XXX for now */ 167 mc->default_boot_order = "c"; 168 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Sun-UltraSparc-T1"); 169 mc->default_ram_id = "sun4v-partition.ram"; 170 } 171 172 static const TypeInfo niagara_type = { 173 .name = MACHINE_TYPE_NAME("niagara"), 174 .parent = TYPE_MACHINE, 175 .class_init = niagara_class_init, 176 }; 177 178 static void niagara_register_types(void) 179 { 180 type_register_static(&niagara_type); 181 } 182 183 type_init(niagara_register_types) 184