1*d0fb9657SStefano Garzarella# See docs/devel/tracing.rst for syntax documentation. 2f0b9e356SDaniel P. Berrange 3500016e5SMarkus Armbruster# sun4m.c 4f0b9e356SDaniel P. Berrangesun4m_cpu_set_irq_raise(int level) "Raise CPU IRQ %d" 5f0b9e356SDaniel P. Berrangesun4m_cpu_set_irq_lower(int level) "Lower CPU IRQ %d" 6f0b9e356SDaniel P. Berrange 7500016e5SMarkus Armbruster# sun4m_iommu.c 8ba51ef25SMark Cave-Aylandsun4m_iommu_mem_readl(uint64_t addr, uint32_t ret) "read reg[0x%"PRIx64"] = 0x%x" 9ba51ef25SMark Cave-Aylandsun4m_iommu_mem_writel(uint64_t addr, uint32_t val) "write reg[0x%"PRIx64"] = 0x%x" 10ba51ef25SMark Cave-Aylandsun4m_iommu_mem_writel_ctrl(uint64_t iostart) "iostart = 0x%"PRIx64 11ba51ef25SMark Cave-Aylandsun4m_iommu_mem_writel_tlbflush(uint32_t val) "tlb flush 0x%x" 12ba51ef25SMark Cave-Aylandsun4m_iommu_mem_writel_pgflush(uint32_t val) "page flush 0x%x" 13ba51ef25SMark Cave-Aylandsun4m_iommu_page_get_flags(uint64_t pa, uint64_t iopte, uint32_t ret) "get flags addr 0x%"PRIx64" => pte 0x%"PRIx64", *pte = 0x%x" 14ba51ef25SMark Cave-Aylandsun4m_iommu_translate_pa(uint64_t addr, uint64_t pa, uint32_t iopte) "xlate dva 0x%"PRIx64" => pa 0x%"PRIx64" iopte = 0x%x" 15ba51ef25SMark Cave-Aylandsun4m_iommu_bad_addr(uint64_t addr) "bad addr 0x%"PRIx64 16ba51ef25SMark Cave-Ayland 17500016e5SMarkus Armbruster# leon3.c 18f0b9e356SDaniel P. Berrangeleon3_set_irq(int intno) "Set CPU IRQ %d" 19f0b9e356SDaniel P. Berrangeleon3_reset_irq(int intno) "Reset CPU IRQ %d" 2012841199SPhilippe Mathieu-Daudéint_helper_icache_freeze(void) "Instruction cache: freeze" 2112841199SPhilippe Mathieu-Daudéint_helper_dcache_freeze(void) "Data cache: freeze" 22