1 /* 2 * QEMU Sun4m iommu emulation 3 * 4 * Copyright (c) 2003-2005 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "hw/irq.h" 27 #include "hw/sparc/sun4m_iommu.h" 28 #include "hw/sysbus.h" 29 #include "migration/vmstate.h" 30 #include "qemu/module.h" 31 #include "exec/address-spaces.h" 32 #include "trace.h" 33 34 /* 35 * I/O MMU used by Sun4m systems 36 * 37 * Chipset docs: 38 * "Sun-4M System Architecture (revision 2.0) by Chuck Narad", 950-1373-01, 39 * http://mediacast.sun.com/users/Barton808/media/Sun4M_SystemArchitecture_edited2.pdf 40 */ 41 42 #define IOMMU_CTRL (0x0000 >> 2) 43 #define IOMMU_CTRL_IMPL 0xf0000000 /* Implementation */ 44 #define IOMMU_CTRL_VERS 0x0f000000 /* Version */ 45 #define IOMMU_CTRL_RNGE 0x0000001c /* Mapping RANGE */ 46 #define IOMMU_RNGE_16MB 0x00000000 /* 0xff000000 -> 0xffffffff */ 47 #define IOMMU_RNGE_32MB 0x00000004 /* 0xfe000000 -> 0xffffffff */ 48 #define IOMMU_RNGE_64MB 0x00000008 /* 0xfc000000 -> 0xffffffff */ 49 #define IOMMU_RNGE_128MB 0x0000000c /* 0xf8000000 -> 0xffffffff */ 50 #define IOMMU_RNGE_256MB 0x00000010 /* 0xf0000000 -> 0xffffffff */ 51 #define IOMMU_RNGE_512MB 0x00000014 /* 0xe0000000 -> 0xffffffff */ 52 #define IOMMU_RNGE_1GB 0x00000018 /* 0xc0000000 -> 0xffffffff */ 53 #define IOMMU_RNGE_2GB 0x0000001c /* 0x80000000 -> 0xffffffff */ 54 #define IOMMU_CTRL_ENAB 0x00000001 /* IOMMU Enable */ 55 #define IOMMU_CTRL_MASK 0x0000001d 56 57 #define IOMMU_BASE (0x0004 >> 2) 58 #define IOMMU_BASE_MASK 0x07fffc00 59 60 #define IOMMU_TLBFLUSH (0x0014 >> 2) 61 #define IOMMU_TLBFLUSH_MASK 0xffffffff 62 63 #define IOMMU_PGFLUSH (0x0018 >> 2) 64 #define IOMMU_PGFLUSH_MASK 0xffffffff 65 66 #define IOMMU_AFSR (0x1000 >> 2) 67 #define IOMMU_AFSR_ERR 0x80000000 /* LE, TO, or BE asserted */ 68 #define IOMMU_AFSR_LE 0x40000000 /* SBUS reports error after 69 transaction */ 70 #define IOMMU_AFSR_TO 0x20000000 /* Write access took more than 71 12.8 us. */ 72 #define IOMMU_AFSR_BE 0x10000000 /* Write access received error 73 acknowledge */ 74 #define IOMMU_AFSR_SIZE 0x0e000000 /* Size of transaction causing error */ 75 #define IOMMU_AFSR_S 0x01000000 /* Sparc was in supervisor mode */ 76 #define IOMMU_AFSR_RESV 0x00800000 /* Reserved, forced to 0x8 by 77 hardware */ 78 #define IOMMU_AFSR_ME 0x00080000 /* Multiple errors occurred */ 79 #define IOMMU_AFSR_RD 0x00040000 /* A read operation was in progress */ 80 #define IOMMU_AFSR_FAV 0x00020000 /* IOMMU afar has valid contents */ 81 #define IOMMU_AFSR_MASK 0xff0fffff 82 83 #define IOMMU_AFAR (0x1004 >> 2) 84 85 #define IOMMU_AER (0x1008 >> 2) /* Arbiter Enable Register */ 86 #define IOMMU_AER_EN_P0_ARB 0x00000001 /* MBus master 0x8 (Always 1) */ 87 #define IOMMU_AER_EN_P1_ARB 0x00000002 /* MBus master 0x9 */ 88 #define IOMMU_AER_EN_P2_ARB 0x00000004 /* MBus master 0xa */ 89 #define IOMMU_AER_EN_P3_ARB 0x00000008 /* MBus master 0xb */ 90 #define IOMMU_AER_EN_0 0x00010000 /* SBus slot 0 */ 91 #define IOMMU_AER_EN_1 0x00020000 /* SBus slot 1 */ 92 #define IOMMU_AER_EN_2 0x00040000 /* SBus slot 2 */ 93 #define IOMMU_AER_EN_3 0x00080000 /* SBus slot 3 */ 94 #define IOMMU_AER_EN_F 0x00100000 /* SBus on-board */ 95 #define IOMMU_AER_SBW 0x80000000 /* S-to-M asynchronous writes */ 96 #define IOMMU_AER_MASK 0x801f000f 97 98 #define IOMMU_SBCFG0 (0x1010 >> 2) /* SBUS configration per-slot */ 99 #define IOMMU_SBCFG1 (0x1014 >> 2) /* SBUS configration per-slot */ 100 #define IOMMU_SBCFG2 (0x1018 >> 2) /* SBUS configration per-slot */ 101 #define IOMMU_SBCFG3 (0x101c >> 2) /* SBUS configration per-slot */ 102 #define IOMMU_SBCFG_SAB30 0x00010000 /* Phys-address bit 30 when 103 bypass enabled */ 104 #define IOMMU_SBCFG_BA16 0x00000004 /* Slave supports 16 byte bursts */ 105 #define IOMMU_SBCFG_BA8 0x00000002 /* Slave supports 8 byte bursts */ 106 #define IOMMU_SBCFG_BYPASS 0x00000001 /* Bypass IOMMU, treat all addresses 107 produced by this device as pure 108 physical. */ 109 #define IOMMU_SBCFG_MASK 0x00010003 110 111 #define IOMMU_ARBEN (0x2000 >> 2) /* SBUS arbitration enable */ 112 #define IOMMU_ARBEN_MASK 0x001f0000 113 #define IOMMU_MID 0x00000008 114 115 #define IOMMU_MASK_ID (0x3018 >> 2) /* Mask ID */ 116 #define IOMMU_MASK_ID_MASK 0x00ffffff 117 118 #define IOMMU_MSII_MASK 0x26000000 /* microSPARC II mask number */ 119 #define IOMMU_TS_MASK 0x23000000 /* turboSPARC mask number */ 120 121 /* The format of an iopte in the page tables */ 122 #define IOPTE_PAGE 0xffffff00 /* Physical page number (PA[35:12]) */ 123 #define IOPTE_CACHE 0x00000080 /* Cached (in vme IOCACHE or 124 Viking/MXCC) */ 125 #define IOPTE_WRITE 0x00000004 /* Writable */ 126 #define IOPTE_VALID 0x00000002 /* IOPTE is valid */ 127 #define IOPTE_WAZ 0x00000001 /* Write as zeros */ 128 129 #define IOMMU_PAGE_SHIFT 12 130 #define IOMMU_PAGE_SIZE (1 << IOMMU_PAGE_SHIFT) 131 #define IOMMU_PAGE_MASK (~(IOMMU_PAGE_SIZE - 1)) 132 133 static uint64_t iommu_mem_read(void *opaque, hwaddr addr, 134 unsigned size) 135 { 136 IOMMUState *s = opaque; 137 hwaddr saddr; 138 uint32_t ret; 139 140 saddr = addr >> 2; 141 switch (saddr) { 142 default: 143 ret = s->regs[saddr]; 144 break; 145 case IOMMU_AFAR: 146 case IOMMU_AFSR: 147 ret = s->regs[saddr]; 148 qemu_irq_lower(s->irq); 149 break; 150 } 151 trace_sun4m_iommu_mem_readl(saddr, ret); 152 return ret; 153 } 154 155 static void iommu_mem_write(void *opaque, hwaddr addr, 156 uint64_t val, unsigned size) 157 { 158 IOMMUState *s = opaque; 159 hwaddr saddr; 160 161 saddr = addr >> 2; 162 trace_sun4m_iommu_mem_writel(saddr, val); 163 switch (saddr) { 164 case IOMMU_CTRL: 165 switch (val & IOMMU_CTRL_RNGE) { 166 case IOMMU_RNGE_16MB: 167 s->iostart = 0xffffffffff000000ULL; 168 break; 169 case IOMMU_RNGE_32MB: 170 s->iostart = 0xfffffffffe000000ULL; 171 break; 172 case IOMMU_RNGE_64MB: 173 s->iostart = 0xfffffffffc000000ULL; 174 break; 175 case IOMMU_RNGE_128MB: 176 s->iostart = 0xfffffffff8000000ULL; 177 break; 178 case IOMMU_RNGE_256MB: 179 s->iostart = 0xfffffffff0000000ULL; 180 break; 181 case IOMMU_RNGE_512MB: 182 s->iostart = 0xffffffffe0000000ULL; 183 break; 184 case IOMMU_RNGE_1GB: 185 s->iostart = 0xffffffffc0000000ULL; 186 break; 187 default: 188 case IOMMU_RNGE_2GB: 189 s->iostart = 0xffffffff80000000ULL; 190 break; 191 } 192 trace_sun4m_iommu_mem_writel_ctrl(s->iostart); 193 s->regs[saddr] = ((val & IOMMU_CTRL_MASK) | s->version); 194 break; 195 case IOMMU_BASE: 196 s->regs[saddr] = val & IOMMU_BASE_MASK; 197 break; 198 case IOMMU_TLBFLUSH: 199 trace_sun4m_iommu_mem_writel_tlbflush(val); 200 s->regs[saddr] = val & IOMMU_TLBFLUSH_MASK; 201 break; 202 case IOMMU_PGFLUSH: 203 trace_sun4m_iommu_mem_writel_pgflush(val); 204 s->regs[saddr] = val & IOMMU_PGFLUSH_MASK; 205 break; 206 case IOMMU_AFAR: 207 s->regs[saddr] = val; 208 qemu_irq_lower(s->irq); 209 break; 210 case IOMMU_AER: 211 s->regs[saddr] = (val & IOMMU_AER_MASK) | IOMMU_AER_EN_P0_ARB; 212 break; 213 case IOMMU_AFSR: 214 s->regs[saddr] = (val & IOMMU_AFSR_MASK) | IOMMU_AFSR_RESV; 215 qemu_irq_lower(s->irq); 216 break; 217 case IOMMU_SBCFG0: 218 case IOMMU_SBCFG1: 219 case IOMMU_SBCFG2: 220 case IOMMU_SBCFG3: 221 s->regs[saddr] = val & IOMMU_SBCFG_MASK; 222 break; 223 case IOMMU_ARBEN: 224 /* XXX implement SBus probing: fault when reading unmapped 225 addresses, fault cause and address stored to MMU/IOMMU */ 226 s->regs[saddr] = (val & IOMMU_ARBEN_MASK) | IOMMU_MID; 227 break; 228 case IOMMU_MASK_ID: 229 s->regs[saddr] |= val & IOMMU_MASK_ID_MASK; 230 break; 231 default: 232 s->regs[saddr] = val; 233 break; 234 } 235 } 236 237 static const MemoryRegionOps iommu_mem_ops = { 238 .read = iommu_mem_read, 239 .write = iommu_mem_write, 240 .endianness = DEVICE_NATIVE_ENDIAN, 241 .valid = { 242 .min_access_size = 4, 243 .max_access_size = 4, 244 }, 245 }; 246 247 static uint32_t iommu_page_get_flags(IOMMUState *s, hwaddr addr) 248 { 249 uint32_t ret; 250 hwaddr iopte; 251 hwaddr pa = addr; 252 253 iopte = s->regs[IOMMU_BASE] << 4; 254 addr &= ~s->iostart; 255 iopte += (addr >> (IOMMU_PAGE_SHIFT - 2)) & ~3; 256 ret = address_space_ldl_be(&address_space_memory, iopte, 257 MEMTXATTRS_UNSPECIFIED, NULL); 258 trace_sun4m_iommu_page_get_flags(pa, iopte, ret); 259 return ret; 260 } 261 262 static hwaddr iommu_translate_pa(hwaddr addr, 263 uint32_t pte) 264 { 265 hwaddr pa; 266 267 pa = ((pte & IOPTE_PAGE) << 4) + (addr & ~IOMMU_PAGE_MASK); 268 trace_sun4m_iommu_translate_pa(addr, pa, pte); 269 return pa; 270 } 271 272 static void iommu_bad_addr(IOMMUState *s, hwaddr addr, 273 int is_write) 274 { 275 trace_sun4m_iommu_bad_addr(addr); 276 s->regs[IOMMU_AFSR] = IOMMU_AFSR_ERR | IOMMU_AFSR_LE | IOMMU_AFSR_RESV | 277 IOMMU_AFSR_FAV; 278 if (!is_write) { 279 s->regs[IOMMU_AFSR] |= IOMMU_AFSR_RD; 280 } 281 s->regs[IOMMU_AFAR] = addr; 282 qemu_irq_raise(s->irq); 283 } 284 285 /* Called from RCU critical section */ 286 static IOMMUTLBEntry sun4m_translate_iommu(IOMMUMemoryRegion *iommu, 287 hwaddr addr, 288 IOMMUAccessFlags flags, 289 int iommu_idx) 290 { 291 IOMMUState *is = container_of(iommu, IOMMUState, iommu); 292 hwaddr page, pa; 293 int is_write = (flags & IOMMU_WO) ? 1 : 0; 294 uint32_t pte; 295 IOMMUTLBEntry ret = { 296 .target_as = &address_space_memory, 297 .iova = 0, 298 .translated_addr = 0, 299 .addr_mask = ~(hwaddr)0, 300 .perm = IOMMU_NONE, 301 }; 302 303 page = addr & IOMMU_PAGE_MASK; 304 pte = iommu_page_get_flags(is, page); 305 if (!(pte & IOPTE_VALID)) { 306 iommu_bad_addr(is, page, is_write); 307 return ret; 308 } 309 310 pa = iommu_translate_pa(addr, pte); 311 if (is_write && !(pte & IOPTE_WRITE)) { 312 iommu_bad_addr(is, page, is_write); 313 return ret; 314 } 315 316 if (pte & IOPTE_WRITE) { 317 ret.perm = IOMMU_RW; 318 } else { 319 ret.perm = IOMMU_RO; 320 } 321 322 ret.iova = page; 323 ret.translated_addr = pa; 324 ret.addr_mask = ~IOMMU_PAGE_MASK; 325 326 return ret; 327 } 328 329 static const VMStateDescription vmstate_iommu = { 330 .name = "iommu", 331 .version_id = 2, 332 .minimum_version_id = 2, 333 .fields = (VMStateField[]) { 334 VMSTATE_UINT32_ARRAY(regs, IOMMUState, IOMMU_NREGS), 335 VMSTATE_UINT64(iostart, IOMMUState), 336 VMSTATE_END_OF_LIST() 337 } 338 }; 339 340 static void iommu_reset(DeviceState *d) 341 { 342 IOMMUState *s = SUN4M_IOMMU(d); 343 344 memset(s->regs, 0, IOMMU_NREGS * 4); 345 s->iostart = 0; 346 s->regs[IOMMU_CTRL] = s->version; 347 s->regs[IOMMU_ARBEN] = IOMMU_MID; 348 s->regs[IOMMU_AFSR] = IOMMU_AFSR_RESV; 349 s->regs[IOMMU_AER] = IOMMU_AER_EN_P0_ARB | IOMMU_AER_EN_P1_ARB; 350 s->regs[IOMMU_MASK_ID] = IOMMU_TS_MASK; 351 } 352 353 static void iommu_init(Object *obj) 354 { 355 IOMMUState *s = SUN4M_IOMMU(obj); 356 SysBusDevice *dev = SYS_BUS_DEVICE(obj); 357 358 memory_region_init_iommu(&s->iommu, sizeof(s->iommu), 359 TYPE_SUN4M_IOMMU_MEMORY_REGION, OBJECT(dev), 360 "iommu-sun4m", UINT64_MAX); 361 address_space_init(&s->iommu_as, MEMORY_REGION(&s->iommu), "iommu-as"); 362 363 sysbus_init_irq(dev, &s->irq); 364 365 memory_region_init_io(&s->iomem, obj, &iommu_mem_ops, s, "iommu", 366 IOMMU_NREGS * sizeof(uint32_t)); 367 sysbus_init_mmio(dev, &s->iomem); 368 } 369 370 static Property iommu_properties[] = { 371 DEFINE_PROP_UINT32("version", IOMMUState, version, 0), 372 DEFINE_PROP_END_OF_LIST(), 373 }; 374 375 static void iommu_class_init(ObjectClass *klass, void *data) 376 { 377 DeviceClass *dc = DEVICE_CLASS(klass); 378 379 dc->reset = iommu_reset; 380 dc->vmsd = &vmstate_iommu; 381 dc->props = iommu_properties; 382 } 383 384 static const TypeInfo iommu_info = { 385 .name = TYPE_SUN4M_IOMMU, 386 .parent = TYPE_SYS_BUS_DEVICE, 387 .instance_size = sizeof(IOMMUState), 388 .instance_init = iommu_init, 389 .class_init = iommu_class_init, 390 }; 391 392 static void sun4m_iommu_memory_region_class_init(ObjectClass *klass, void *data) 393 { 394 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_CLASS(klass); 395 396 imrc->translate = sun4m_translate_iommu; 397 } 398 399 static const TypeInfo sun4m_iommu_memory_region_info = { 400 .parent = TYPE_IOMMU_MEMORY_REGION, 401 .name = TYPE_SUN4M_IOMMU_MEMORY_REGION, 402 .class_init = sun4m_iommu_memory_region_class_init, 403 }; 404 405 static void iommu_register_types(void) 406 { 407 type_register_static(&iommu_info); 408 type_register_static(&sun4m_iommu_memory_region_info); 409 } 410 411 type_init(iommu_register_types) 412