1 /* 2 * QEMU Sun4m & Sun4d & Sun4c System Emulator 3 * 4 * Copyright (c) 2003-2005 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "hw/sysbus.h" 25 #include "qemu/timer.h" 26 #include "hw/sparc/sun4m.h" 27 #include "hw/timer/m48t59.h" 28 #include "hw/sparc/sparc32_dma.h" 29 #include "hw/block/fdc.h" 30 #include "sysemu/sysemu.h" 31 #include "net/net.h" 32 #include "hw/boards.h" 33 #include "hw/nvram/openbios_firmware_abi.h" 34 #include "hw/scsi/esp.h" 35 #include "hw/i386/pc.h" 36 #include "hw/isa/isa.h" 37 #include "hw/nvram/fw_cfg.h" 38 #include "hw/char/escc.h" 39 #include "hw/empty_slot.h" 40 #include "hw/loader.h" 41 #include "elf.h" 42 #include "sysemu/blockdev.h" 43 #include "trace.h" 44 45 /* 46 * Sun4m architecture was used in the following machines: 47 * 48 * SPARCserver 6xxMP/xx 49 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15), 50 * SPARCclassic X (4/10) 51 * SPARCstation LX/ZX (4/30) 52 * SPARCstation Voyager 53 * SPARCstation 10/xx, SPARCserver 10/xx 54 * SPARCstation 5, SPARCserver 5 55 * SPARCstation 20/xx, SPARCserver 20 56 * SPARCstation 4 57 * 58 * See for example: http://www.sunhelp.org/faq/sunref1.html 59 */ 60 61 #define KERNEL_LOAD_ADDR 0x00004000 62 #define CMDLINE_ADDR 0x007ff000 63 #define INITRD_LOAD_ADDR 0x00800000 64 #define PROM_SIZE_MAX (1024 * 1024) 65 #define PROM_VADDR 0xffd00000 66 #define PROM_FILENAME "openbios-sparc32" 67 #define CFG_ADDR 0xd00000510ULL 68 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00) 69 #define FW_CFG_SUN4M_WIDTH (FW_CFG_ARCH_LOCAL + 0x01) 70 #define FW_CFG_SUN4M_HEIGHT (FW_CFG_ARCH_LOCAL + 0x02) 71 72 #define MAX_CPUS 16 73 #define MAX_PILS 16 74 #define MAX_VSIMMS 4 75 76 #define ESCC_CLOCK 4915200 77 78 struct sun4m_hwdef { 79 hwaddr iommu_base, iommu_pad_base, iommu_pad_len, slavio_base; 80 hwaddr intctl_base, counter_base, nvram_base, ms_kb_base; 81 hwaddr serial_base, fd_base; 82 hwaddr afx_base, idreg_base, dma_base, esp_base, le_base; 83 hwaddr tcx_base, cs_base, apc_base, aux1_base, aux2_base; 84 hwaddr bpp_base, dbri_base, sx_base; 85 struct { 86 hwaddr reg_base, vram_base; 87 } vsimm[MAX_VSIMMS]; 88 hwaddr ecc_base; 89 uint64_t max_mem; 90 const char * const default_cpu_model; 91 uint32_t ecc_version; 92 uint32_t iommu_version; 93 uint16_t machine_id; 94 uint8_t nvram_machine_id; 95 }; 96 97 int DMA_get_channel_mode (int nchan) 98 { 99 return 0; 100 } 101 int DMA_read_memory (int nchan, void *buf, int pos, int size) 102 { 103 return 0; 104 } 105 int DMA_write_memory (int nchan, void *buf, int pos, int size) 106 { 107 return 0; 108 } 109 void DMA_hold_DREQ (int nchan) {} 110 void DMA_release_DREQ (int nchan) {} 111 void DMA_schedule(int nchan) {} 112 113 void DMA_init(int high_page_enable, qemu_irq *cpu_request_exit) 114 { 115 } 116 117 void DMA_register_channel (int nchan, 118 DMA_transfer_handler transfer_handler, 119 void *opaque) 120 { 121 } 122 123 static int fw_cfg_boot_set(void *opaque, const char *boot_device) 124 { 125 fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); 126 return 0; 127 } 128 129 static void nvram_init(M48t59State *nvram, uint8_t *macaddr, 130 const char *cmdline, const char *boot_devices, 131 ram_addr_t RAM_size, uint32_t kernel_size, 132 int width, int height, int depth, 133 int nvram_machine_id, const char *arch) 134 { 135 unsigned int i; 136 uint32_t start, end; 137 uint8_t image[0x1ff0]; 138 struct OpenBIOS_nvpart_v1 *part_header; 139 140 memset(image, '\0', sizeof(image)); 141 142 start = 0; 143 144 // OpenBIOS nvram variables 145 // Variable partition 146 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start]; 147 part_header->signature = OPENBIOS_PART_SYSTEM; 148 pstrcpy(part_header->name, sizeof(part_header->name), "system"); 149 150 end = start + sizeof(struct OpenBIOS_nvpart_v1); 151 for (i = 0; i < nb_prom_envs; i++) 152 end = OpenBIOS_set_var(image, end, prom_envs[i]); 153 154 // End marker 155 image[end++] = '\0'; 156 157 end = start + ((end - start + 15) & ~15); 158 OpenBIOS_finish_partition(part_header, end - start); 159 160 // free partition 161 start = end; 162 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start]; 163 part_header->signature = OPENBIOS_PART_FREE; 164 pstrcpy(part_header->name, sizeof(part_header->name), "free"); 165 166 end = 0x1fd0; 167 OpenBIOS_finish_partition(part_header, end - start); 168 169 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 170 nvram_machine_id); 171 172 for (i = 0; i < sizeof(image); i++) 173 m48t59_write(nvram, i, image[i]); 174 } 175 176 static DeviceState *slavio_intctl; 177 178 void sun4m_pic_info(Monitor *mon, const QDict *qdict) 179 { 180 if (slavio_intctl) 181 slavio_pic_info(mon, slavio_intctl); 182 } 183 184 void sun4m_irq_info(Monitor *mon, const QDict *qdict) 185 { 186 if (slavio_intctl) 187 slavio_irq_info(mon, slavio_intctl); 188 } 189 190 void cpu_check_irqs(CPUSPARCState *env) 191 { 192 CPUState *cs; 193 194 if (env->pil_in && (env->interrupt_index == 0 || 195 (env->interrupt_index & ~15) == TT_EXTINT)) { 196 unsigned int i; 197 198 for (i = 15; i > 0; i--) { 199 if (env->pil_in & (1 << i)) { 200 int old_interrupt = env->interrupt_index; 201 202 env->interrupt_index = TT_EXTINT | i; 203 if (old_interrupt != env->interrupt_index) { 204 cs = CPU(sparc_env_get_cpu(env)); 205 trace_sun4m_cpu_interrupt(i); 206 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 207 } 208 break; 209 } 210 } 211 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) { 212 cs = CPU(sparc_env_get_cpu(env)); 213 trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15); 214 env->interrupt_index = 0; 215 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 216 } 217 } 218 219 static void cpu_kick_irq(SPARCCPU *cpu) 220 { 221 CPUSPARCState *env = &cpu->env; 222 CPUState *cs = CPU(cpu); 223 224 cs->halted = 0; 225 cpu_check_irqs(env); 226 qemu_cpu_kick(cs); 227 } 228 229 static void cpu_set_irq(void *opaque, int irq, int level) 230 { 231 SPARCCPU *cpu = opaque; 232 CPUSPARCState *env = &cpu->env; 233 234 if (level) { 235 trace_sun4m_cpu_set_irq_raise(irq); 236 env->pil_in |= 1 << irq; 237 cpu_kick_irq(cpu); 238 } else { 239 trace_sun4m_cpu_set_irq_lower(irq); 240 env->pil_in &= ~(1 << irq); 241 cpu_check_irqs(env); 242 } 243 } 244 245 static void dummy_cpu_set_irq(void *opaque, int irq, int level) 246 { 247 } 248 249 static void main_cpu_reset(void *opaque) 250 { 251 SPARCCPU *cpu = opaque; 252 CPUState *cs = CPU(cpu); 253 254 cpu_reset(cs); 255 cs->halted = 0; 256 } 257 258 static void secondary_cpu_reset(void *opaque) 259 { 260 SPARCCPU *cpu = opaque; 261 CPUState *cs = CPU(cpu); 262 263 cpu_reset(cs); 264 cs->halted = 1; 265 } 266 267 static void cpu_halt_signal(void *opaque, int irq, int level) 268 { 269 if (level && current_cpu) { 270 cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT); 271 } 272 } 273 274 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 275 { 276 return addr - 0xf0000000ULL; 277 } 278 279 static unsigned long sun4m_load_kernel(const char *kernel_filename, 280 const char *initrd_filename, 281 ram_addr_t RAM_size) 282 { 283 int linux_boot; 284 unsigned int i; 285 long initrd_size, kernel_size; 286 uint8_t *ptr; 287 288 linux_boot = (kernel_filename != NULL); 289 290 kernel_size = 0; 291 if (linux_boot) { 292 int bswap_needed; 293 294 #ifdef BSWAP_NEEDED 295 bswap_needed = 1; 296 #else 297 bswap_needed = 0; 298 #endif 299 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL, 300 NULL, NULL, NULL, 1, ELF_MACHINE, 0); 301 if (kernel_size < 0) 302 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR, 303 RAM_size - KERNEL_LOAD_ADDR, bswap_needed, 304 TARGET_PAGE_SIZE); 305 if (kernel_size < 0) 306 kernel_size = load_image_targphys(kernel_filename, 307 KERNEL_LOAD_ADDR, 308 RAM_size - KERNEL_LOAD_ADDR); 309 if (kernel_size < 0) { 310 fprintf(stderr, "qemu: could not load kernel '%s'\n", 311 kernel_filename); 312 exit(1); 313 } 314 315 /* load initrd */ 316 initrd_size = 0; 317 if (initrd_filename) { 318 initrd_size = load_image_targphys(initrd_filename, 319 INITRD_LOAD_ADDR, 320 RAM_size - INITRD_LOAD_ADDR); 321 if (initrd_size < 0) { 322 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", 323 initrd_filename); 324 exit(1); 325 } 326 } 327 if (initrd_size > 0) { 328 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { 329 ptr = rom_ptr(KERNEL_LOAD_ADDR + i); 330 if (ldl_p(ptr) == 0x48647253) { // HdrS 331 stl_p(ptr + 16, INITRD_LOAD_ADDR); 332 stl_p(ptr + 20, initrd_size); 333 break; 334 } 335 } 336 } 337 } 338 return kernel_size; 339 } 340 341 static void *iommu_init(hwaddr addr, uint32_t version, qemu_irq irq) 342 { 343 DeviceState *dev; 344 SysBusDevice *s; 345 346 dev = qdev_create(NULL, "iommu"); 347 qdev_prop_set_uint32(dev, "version", version); 348 qdev_init_nofail(dev); 349 s = SYS_BUS_DEVICE(dev); 350 sysbus_connect_irq(s, 0, irq); 351 sysbus_mmio_map(s, 0, addr); 352 353 return s; 354 } 355 356 static void *sparc32_dma_init(hwaddr daddr, qemu_irq parent_irq, 357 void *iommu, qemu_irq *dev_irq, int is_ledma) 358 { 359 DeviceState *dev; 360 SysBusDevice *s; 361 362 dev = qdev_create(NULL, "sparc32_dma"); 363 qdev_prop_set_ptr(dev, "iommu_opaque", iommu); 364 qdev_prop_set_uint32(dev, "is_ledma", is_ledma); 365 qdev_init_nofail(dev); 366 s = SYS_BUS_DEVICE(dev); 367 sysbus_connect_irq(s, 0, parent_irq); 368 *dev_irq = qdev_get_gpio_in(dev, 0); 369 sysbus_mmio_map(s, 0, daddr); 370 371 return s; 372 } 373 374 static void lance_init(NICInfo *nd, hwaddr leaddr, 375 void *dma_opaque, qemu_irq irq) 376 { 377 DeviceState *dev; 378 SysBusDevice *s; 379 qemu_irq reset; 380 381 qemu_check_nic_model(&nd_table[0], "lance"); 382 383 dev = qdev_create(NULL, "lance"); 384 qdev_set_nic_properties(dev, nd); 385 qdev_prop_set_ptr(dev, "dma", dma_opaque); 386 qdev_init_nofail(dev); 387 s = SYS_BUS_DEVICE(dev); 388 sysbus_mmio_map(s, 0, leaddr); 389 sysbus_connect_irq(s, 0, irq); 390 reset = qdev_get_gpio_in(dev, 0); 391 qdev_connect_gpio_out(dma_opaque, 0, reset); 392 } 393 394 static DeviceState *slavio_intctl_init(hwaddr addr, 395 hwaddr addrg, 396 qemu_irq **parent_irq) 397 { 398 DeviceState *dev; 399 SysBusDevice *s; 400 unsigned int i, j; 401 402 dev = qdev_create(NULL, "slavio_intctl"); 403 qdev_init_nofail(dev); 404 405 s = SYS_BUS_DEVICE(dev); 406 407 for (i = 0; i < MAX_CPUS; i++) { 408 for (j = 0; j < MAX_PILS; j++) { 409 sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]); 410 } 411 } 412 sysbus_mmio_map(s, 0, addrg); 413 for (i = 0; i < MAX_CPUS; i++) { 414 sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE); 415 } 416 417 return dev; 418 } 419 420 #define SYS_TIMER_OFFSET 0x10000ULL 421 #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu) 422 423 static void slavio_timer_init_all(hwaddr addr, qemu_irq master_irq, 424 qemu_irq *cpu_irqs, unsigned int num_cpus) 425 { 426 DeviceState *dev; 427 SysBusDevice *s; 428 unsigned int i; 429 430 dev = qdev_create(NULL, "slavio_timer"); 431 qdev_prop_set_uint32(dev, "num_cpus", num_cpus); 432 qdev_init_nofail(dev); 433 s = SYS_BUS_DEVICE(dev); 434 sysbus_connect_irq(s, 0, master_irq); 435 sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET); 436 437 for (i = 0; i < MAX_CPUS; i++) { 438 sysbus_mmio_map(s, i + 1, addr + (hwaddr)CPU_TIMER_OFFSET(i)); 439 sysbus_connect_irq(s, i + 1, cpu_irqs[i]); 440 } 441 } 442 443 static qemu_irq slavio_system_powerdown; 444 445 static void slavio_powerdown_req(Notifier *n, void *opaque) 446 { 447 qemu_irq_raise(slavio_system_powerdown); 448 } 449 450 static Notifier slavio_system_powerdown_notifier = { 451 .notify = slavio_powerdown_req 452 }; 453 454 #define MISC_LEDS 0x01600000 455 #define MISC_CFG 0x01800000 456 #define MISC_DIAG 0x01a00000 457 #define MISC_MDM 0x01b00000 458 #define MISC_SYS 0x01f00000 459 460 static void slavio_misc_init(hwaddr base, 461 hwaddr aux1_base, 462 hwaddr aux2_base, qemu_irq irq, 463 qemu_irq fdc_tc) 464 { 465 DeviceState *dev; 466 SysBusDevice *s; 467 468 dev = qdev_create(NULL, "slavio_misc"); 469 qdev_init_nofail(dev); 470 s = SYS_BUS_DEVICE(dev); 471 if (base) { 472 /* 8 bit registers */ 473 /* Slavio control */ 474 sysbus_mmio_map(s, 0, base + MISC_CFG); 475 /* Diagnostics */ 476 sysbus_mmio_map(s, 1, base + MISC_DIAG); 477 /* Modem control */ 478 sysbus_mmio_map(s, 2, base + MISC_MDM); 479 /* 16 bit registers */ 480 /* ss600mp diag LEDs */ 481 sysbus_mmio_map(s, 3, base + MISC_LEDS); 482 /* 32 bit registers */ 483 /* System control */ 484 sysbus_mmio_map(s, 4, base + MISC_SYS); 485 } 486 if (aux1_base) { 487 /* AUX 1 (Misc System Functions) */ 488 sysbus_mmio_map(s, 5, aux1_base); 489 } 490 if (aux2_base) { 491 /* AUX 2 (Software Powerdown Control) */ 492 sysbus_mmio_map(s, 6, aux2_base); 493 } 494 sysbus_connect_irq(s, 0, irq); 495 sysbus_connect_irq(s, 1, fdc_tc); 496 slavio_system_powerdown = qdev_get_gpio_in(dev, 0); 497 qemu_register_powerdown_notifier(&slavio_system_powerdown_notifier); 498 } 499 500 static void ecc_init(hwaddr base, qemu_irq irq, uint32_t version) 501 { 502 DeviceState *dev; 503 SysBusDevice *s; 504 505 dev = qdev_create(NULL, "eccmemctl"); 506 qdev_prop_set_uint32(dev, "version", version); 507 qdev_init_nofail(dev); 508 s = SYS_BUS_DEVICE(dev); 509 sysbus_connect_irq(s, 0, irq); 510 sysbus_mmio_map(s, 0, base); 511 if (version == 0) { // SS-600MP only 512 sysbus_mmio_map(s, 1, base + 0x1000); 513 } 514 } 515 516 static void apc_init(hwaddr power_base, qemu_irq cpu_halt) 517 { 518 DeviceState *dev; 519 SysBusDevice *s; 520 521 dev = qdev_create(NULL, "apc"); 522 qdev_init_nofail(dev); 523 s = SYS_BUS_DEVICE(dev); 524 /* Power management (APC) XXX: not a Slavio device */ 525 sysbus_mmio_map(s, 0, power_base); 526 sysbus_connect_irq(s, 0, cpu_halt); 527 } 528 529 static void tcx_init(hwaddr addr, int vram_size, int width, 530 int height, int depth) 531 { 532 DeviceState *dev; 533 SysBusDevice *s; 534 535 dev = qdev_create(NULL, "SUNW,tcx"); 536 qdev_prop_set_uint32(dev, "vram_size", vram_size); 537 qdev_prop_set_uint16(dev, "width", width); 538 qdev_prop_set_uint16(dev, "height", height); 539 qdev_prop_set_uint16(dev, "depth", depth); 540 qdev_init_nofail(dev); 541 s = SYS_BUS_DEVICE(dev); 542 /* 8-bit plane */ 543 sysbus_mmio_map(s, 0, addr + 0x00800000ULL); 544 /* DAC */ 545 sysbus_mmio_map(s, 1, addr + 0x00200000ULL); 546 /* TEC (dummy) */ 547 sysbus_mmio_map(s, 2, addr + 0x00700000ULL); 548 /* THC 24 bit: NetBSD writes here even with 8-bit display: dummy */ 549 sysbus_mmio_map(s, 3, addr + 0x00301000ULL); 550 if (depth == 24) { 551 /* 24-bit plane */ 552 sysbus_mmio_map(s, 4, addr + 0x02000000ULL); 553 /* Control plane */ 554 sysbus_mmio_map(s, 5, addr + 0x0a000000ULL); 555 } else { 556 /* THC 8 bit (dummy) */ 557 sysbus_mmio_map(s, 4, addr + 0x00300000ULL); 558 } 559 } 560 561 /* NCR89C100/MACIO Internal ID register */ 562 563 #define TYPE_MACIO_ID_REGISTER "macio_idreg" 564 565 static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 }; 566 567 static void idreg_init(hwaddr addr) 568 { 569 DeviceState *dev; 570 SysBusDevice *s; 571 572 dev = qdev_create(NULL, TYPE_MACIO_ID_REGISTER); 573 qdev_init_nofail(dev); 574 s = SYS_BUS_DEVICE(dev); 575 576 sysbus_mmio_map(s, 0, addr); 577 cpu_physical_memory_write_rom(addr, idreg_data, sizeof(idreg_data)); 578 } 579 580 #define MACIO_ID_REGISTER(obj) \ 581 OBJECT_CHECK(IDRegState, (obj), TYPE_MACIO_ID_REGISTER) 582 583 typedef struct IDRegState { 584 SysBusDevice parent_obj; 585 586 MemoryRegion mem; 587 } IDRegState; 588 589 static int idreg_init1(SysBusDevice *dev) 590 { 591 IDRegState *s = MACIO_ID_REGISTER(dev); 592 593 memory_region_init_ram(&s->mem, OBJECT(s), 594 "sun4m.idreg", sizeof(idreg_data)); 595 vmstate_register_ram_global(&s->mem); 596 memory_region_set_readonly(&s->mem, true); 597 sysbus_init_mmio(dev, &s->mem); 598 return 0; 599 } 600 601 static void idreg_class_init(ObjectClass *klass, void *data) 602 { 603 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 604 605 k->init = idreg_init1; 606 } 607 608 static const TypeInfo idreg_info = { 609 .name = TYPE_MACIO_ID_REGISTER, 610 .parent = TYPE_SYS_BUS_DEVICE, 611 .instance_size = sizeof(IDRegState), 612 .class_init = idreg_class_init, 613 }; 614 615 typedef struct AFXState { 616 SysBusDevice busdev; 617 MemoryRegion mem; 618 } AFXState; 619 620 /* SS-5 TCX AFX register */ 621 static void afx_init(hwaddr addr) 622 { 623 DeviceState *dev; 624 SysBusDevice *s; 625 626 dev = qdev_create(NULL, "tcx_afx"); 627 qdev_init_nofail(dev); 628 s = SYS_BUS_DEVICE(dev); 629 630 sysbus_mmio_map(s, 0, addr); 631 } 632 633 static int afx_init1(SysBusDevice *dev) 634 { 635 AFXState *s = FROM_SYSBUS(AFXState, dev); 636 637 memory_region_init_ram(&s->mem, OBJECT(s), "sun4m.afx", 4); 638 vmstate_register_ram_global(&s->mem); 639 sysbus_init_mmio(dev, &s->mem); 640 return 0; 641 } 642 643 static void afx_class_init(ObjectClass *klass, void *data) 644 { 645 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 646 647 k->init = afx_init1; 648 } 649 650 static const TypeInfo afx_info = { 651 .name = "tcx_afx", 652 .parent = TYPE_SYS_BUS_DEVICE, 653 .instance_size = sizeof(AFXState), 654 .class_init = afx_class_init, 655 }; 656 657 typedef struct PROMState { 658 SysBusDevice busdev; 659 MemoryRegion prom; 660 } PROMState; 661 662 /* Boot PROM (OpenBIOS) */ 663 static uint64_t translate_prom_address(void *opaque, uint64_t addr) 664 { 665 hwaddr *base_addr = (hwaddr *)opaque; 666 return addr + *base_addr - PROM_VADDR; 667 } 668 669 static void prom_init(hwaddr addr, const char *bios_name) 670 { 671 DeviceState *dev; 672 SysBusDevice *s; 673 char *filename; 674 int ret; 675 676 dev = qdev_create(NULL, "openprom"); 677 qdev_init_nofail(dev); 678 s = SYS_BUS_DEVICE(dev); 679 680 sysbus_mmio_map(s, 0, addr); 681 682 /* load boot prom */ 683 if (bios_name == NULL) { 684 bios_name = PROM_FILENAME; 685 } 686 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 687 if (filename) { 688 ret = load_elf(filename, translate_prom_address, &addr, NULL, 689 NULL, NULL, 1, ELF_MACHINE, 0); 690 if (ret < 0 || ret > PROM_SIZE_MAX) { 691 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX); 692 } 693 g_free(filename); 694 } else { 695 ret = -1; 696 } 697 if (ret < 0 || ret > PROM_SIZE_MAX) { 698 fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name); 699 exit(1); 700 } 701 } 702 703 static int prom_init1(SysBusDevice *dev) 704 { 705 PROMState *s = FROM_SYSBUS(PROMState, dev); 706 707 memory_region_init_ram(&s->prom, OBJECT(s), "sun4m.prom", PROM_SIZE_MAX); 708 vmstate_register_ram_global(&s->prom); 709 memory_region_set_readonly(&s->prom, true); 710 sysbus_init_mmio(dev, &s->prom); 711 return 0; 712 } 713 714 static Property prom_properties[] = { 715 {/* end of property list */}, 716 }; 717 718 static void prom_class_init(ObjectClass *klass, void *data) 719 { 720 DeviceClass *dc = DEVICE_CLASS(klass); 721 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 722 723 k->init = prom_init1; 724 dc->props = prom_properties; 725 } 726 727 static const TypeInfo prom_info = { 728 .name = "openprom", 729 .parent = TYPE_SYS_BUS_DEVICE, 730 .instance_size = sizeof(PROMState), 731 .class_init = prom_class_init, 732 }; 733 734 typedef struct RamDevice 735 { 736 SysBusDevice busdev; 737 MemoryRegion ram; 738 uint64_t size; 739 } RamDevice; 740 741 /* System RAM */ 742 static int ram_init1(SysBusDevice *dev) 743 { 744 RamDevice *d = FROM_SYSBUS(RamDevice, dev); 745 746 memory_region_init_ram(&d->ram, OBJECT(d), "sun4m.ram", d->size); 747 vmstate_register_ram_global(&d->ram); 748 sysbus_init_mmio(dev, &d->ram); 749 return 0; 750 } 751 752 static void ram_init(hwaddr addr, ram_addr_t RAM_size, 753 uint64_t max_mem) 754 { 755 DeviceState *dev; 756 SysBusDevice *s; 757 RamDevice *d; 758 759 /* allocate RAM */ 760 if ((uint64_t)RAM_size > max_mem) { 761 fprintf(stderr, 762 "qemu: Too much memory for this machine: %d, maximum %d\n", 763 (unsigned int)(RAM_size / (1024 * 1024)), 764 (unsigned int)(max_mem / (1024 * 1024))); 765 exit(1); 766 } 767 dev = qdev_create(NULL, "memory"); 768 s = SYS_BUS_DEVICE(dev); 769 770 d = FROM_SYSBUS(RamDevice, s); 771 d->size = RAM_size; 772 qdev_init_nofail(dev); 773 774 sysbus_mmio_map(s, 0, addr); 775 } 776 777 static Property ram_properties[] = { 778 DEFINE_PROP_UINT64("size", RamDevice, size, 0), 779 DEFINE_PROP_END_OF_LIST(), 780 }; 781 782 static void ram_class_init(ObjectClass *klass, void *data) 783 { 784 DeviceClass *dc = DEVICE_CLASS(klass); 785 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 786 787 k->init = ram_init1; 788 dc->props = ram_properties; 789 } 790 791 static const TypeInfo ram_info = { 792 .name = "memory", 793 .parent = TYPE_SYS_BUS_DEVICE, 794 .instance_size = sizeof(RamDevice), 795 .class_init = ram_class_init, 796 }; 797 798 static void cpu_devinit(const char *cpu_model, unsigned int id, 799 uint64_t prom_addr, qemu_irq **cpu_irqs) 800 { 801 CPUState *cs; 802 SPARCCPU *cpu; 803 CPUSPARCState *env; 804 805 cpu = cpu_sparc_init(cpu_model); 806 if (cpu == NULL) { 807 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n"); 808 exit(1); 809 } 810 env = &cpu->env; 811 812 cpu_sparc_set_id(env, id); 813 if (id == 0) { 814 qemu_register_reset(main_cpu_reset, cpu); 815 } else { 816 qemu_register_reset(secondary_cpu_reset, cpu); 817 cs = CPU(cpu); 818 cs->halted = 1; 819 } 820 *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, cpu, MAX_PILS); 821 env->prom_addr = prom_addr; 822 } 823 824 static void dummy_fdc_tc(void *opaque, int irq, int level) 825 { 826 } 827 828 static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size, 829 const char *boot_device, 830 const char *kernel_filename, 831 const char *kernel_cmdline, 832 const char *initrd_filename, const char *cpu_model) 833 { 834 unsigned int i; 835 void *iommu, *espdma, *ledma, *nvram; 836 qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS], 837 espdma_irq, ledma_irq; 838 qemu_irq esp_reset, dma_enable; 839 qemu_irq fdc_tc; 840 qemu_irq *cpu_halt; 841 unsigned long kernel_size; 842 DriveInfo *fd[MAX_FD]; 843 FWCfgState *fw_cfg; 844 unsigned int num_vsimms; 845 846 /* init CPUs */ 847 if (!cpu_model) 848 cpu_model = hwdef->default_cpu_model; 849 850 for(i = 0; i < smp_cpus; i++) { 851 cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]); 852 } 853 854 for (i = smp_cpus; i < MAX_CPUS; i++) 855 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS); 856 857 858 /* set up devices */ 859 ram_init(0, RAM_size, hwdef->max_mem); 860 /* models without ECC don't trap when missing ram is accessed */ 861 if (!hwdef->ecc_base) { 862 empty_slot_init(RAM_size, hwdef->max_mem - RAM_size); 863 } 864 865 prom_init(hwdef->slavio_base, bios_name); 866 867 slavio_intctl = slavio_intctl_init(hwdef->intctl_base, 868 hwdef->intctl_base + 0x10000ULL, 869 cpu_irqs); 870 871 for (i = 0; i < 32; i++) { 872 slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i); 873 } 874 for (i = 0; i < MAX_CPUS; i++) { 875 slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i); 876 } 877 878 if (hwdef->idreg_base) { 879 idreg_init(hwdef->idreg_base); 880 } 881 882 if (hwdef->afx_base) { 883 afx_init(hwdef->afx_base); 884 } 885 886 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version, 887 slavio_irq[30]); 888 889 if (hwdef->iommu_pad_base) { 890 /* On the real hardware (SS-5, LX) the MMU is not padded, but aliased. 891 Software shouldn't use aliased addresses, neither should it crash 892 when does. Using empty_slot instead of aliasing can help with 893 debugging such accesses */ 894 empty_slot_init(hwdef->iommu_pad_base,hwdef->iommu_pad_len); 895 } 896 897 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[18], 898 iommu, &espdma_irq, 0); 899 900 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL, 901 slavio_irq[16], iommu, &ledma_irq, 1); 902 903 if (graphic_depth != 8 && graphic_depth != 24) { 904 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth); 905 exit (1); 906 } 907 num_vsimms = 0; 908 if (num_vsimms == 0) { 909 tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height, 910 graphic_depth); 911 } 912 913 for (i = num_vsimms; i < MAX_VSIMMS; i++) { 914 /* vsimm registers probed by OBP */ 915 if (hwdef->vsimm[i].reg_base) { 916 empty_slot_init(hwdef->vsimm[i].reg_base, 0x2000); 917 } 918 } 919 920 if (hwdef->sx_base) { 921 empty_slot_init(hwdef->sx_base, 0x2000); 922 } 923 924 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq); 925 926 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 8); 927 928 slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus); 929 930 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[14], 931 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1); 932 /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device 933 Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */ 934 escc_init(hwdef->serial_base, slavio_irq[15], slavio_irq[15], 935 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1); 936 937 cpu_halt = qemu_allocate_irqs(cpu_halt_signal, NULL, 1); 938 if (hwdef->apc_base) { 939 apc_init(hwdef->apc_base, cpu_halt[0]); 940 } 941 942 if (hwdef->fd_base) { 943 /* there is zero or one floppy drive */ 944 memset(fd, 0, sizeof(fd)); 945 fd[0] = drive_get(IF_FLOPPY, 0, 0); 946 sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd, 947 &fdc_tc); 948 } else { 949 fdc_tc = *qemu_allocate_irqs(dummy_fdc_tc, NULL, 1); 950 } 951 952 slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base, 953 slavio_irq[30], fdc_tc); 954 955 if (drive_get_max_bus(IF_SCSI) > 0) { 956 fprintf(stderr, "qemu: too many SCSI bus\n"); 957 exit(1); 958 } 959 960 esp_init(hwdef->esp_base, 2, 961 espdma_memory_read, espdma_memory_write, 962 espdma, espdma_irq, &esp_reset, &dma_enable); 963 964 qdev_connect_gpio_out(espdma, 0, esp_reset); 965 qdev_connect_gpio_out(espdma, 1, dma_enable); 966 967 if (hwdef->cs_base) { 968 sysbus_create_simple("SUNW,CS4231", hwdef->cs_base, 969 slavio_irq[5]); 970 } 971 972 if (hwdef->dbri_base) { 973 /* ISDN chip with attached CS4215 audio codec */ 974 /* prom space */ 975 empty_slot_init(hwdef->dbri_base+0x1000, 0x30); 976 /* reg space */ 977 empty_slot_init(hwdef->dbri_base+0x10000, 0x100); 978 } 979 980 if (hwdef->bpp_base) { 981 /* parallel port */ 982 empty_slot_init(hwdef->bpp_base, 0x20); 983 } 984 985 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename, 986 RAM_size); 987 988 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline, 989 boot_device, RAM_size, kernel_size, graphic_width, 990 graphic_height, graphic_depth, hwdef->nvram_machine_id, 991 "Sun4m"); 992 993 if (hwdef->ecc_base) 994 ecc_init(hwdef->ecc_base, slavio_irq[28], 995 hwdef->ecc_version); 996 997 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2); 998 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus); 999 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1); 1000 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 1001 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); 1002 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth); 1003 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_WIDTH, graphic_width); 1004 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_HEIGHT, graphic_height); 1005 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR); 1006 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 1007 if (kernel_cmdline) { 1008 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR); 1009 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline); 1010 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline); 1011 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 1012 strlen(kernel_cmdline) + 1); 1013 } else { 1014 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0); 1015 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0); 1016 } 1017 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR); 1018 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used 1019 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]); 1020 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); 1021 } 1022 1023 enum { 1024 ss5_id = 32, 1025 vger_id, 1026 lx_id, 1027 ss4_id, 1028 scls_id, 1029 sbook_id, 1030 ss10_id = 64, 1031 ss20_id, 1032 ss600mp_id, 1033 }; 1034 1035 static const struct sun4m_hwdef sun4m_hwdefs[] = { 1036 /* SS-5 */ 1037 { 1038 .iommu_base = 0x10000000, 1039 .iommu_pad_base = 0x10004000, 1040 .iommu_pad_len = 0x0fffb000, 1041 .tcx_base = 0x50000000, 1042 .cs_base = 0x6c000000, 1043 .slavio_base = 0x70000000, 1044 .ms_kb_base = 0x71000000, 1045 .serial_base = 0x71100000, 1046 .nvram_base = 0x71200000, 1047 .fd_base = 0x71400000, 1048 .counter_base = 0x71d00000, 1049 .intctl_base = 0x71e00000, 1050 .idreg_base = 0x78000000, 1051 .dma_base = 0x78400000, 1052 .esp_base = 0x78800000, 1053 .le_base = 0x78c00000, 1054 .apc_base = 0x6a000000, 1055 .afx_base = 0x6e000000, 1056 .aux1_base = 0x71900000, 1057 .aux2_base = 0x71910000, 1058 .nvram_machine_id = 0x80, 1059 .machine_id = ss5_id, 1060 .iommu_version = 0x05000000, 1061 .max_mem = 0x10000000, 1062 .default_cpu_model = "Fujitsu MB86904", 1063 }, 1064 /* SS-10 */ 1065 { 1066 .iommu_base = 0xfe0000000ULL, 1067 .tcx_base = 0xe20000000ULL, 1068 .slavio_base = 0xff0000000ULL, 1069 .ms_kb_base = 0xff1000000ULL, 1070 .serial_base = 0xff1100000ULL, 1071 .nvram_base = 0xff1200000ULL, 1072 .fd_base = 0xff1700000ULL, 1073 .counter_base = 0xff1300000ULL, 1074 .intctl_base = 0xff1400000ULL, 1075 .idreg_base = 0xef0000000ULL, 1076 .dma_base = 0xef0400000ULL, 1077 .esp_base = 0xef0800000ULL, 1078 .le_base = 0xef0c00000ULL, 1079 .apc_base = 0xefa000000ULL, // XXX should not exist 1080 .aux1_base = 0xff1800000ULL, 1081 .aux2_base = 0xff1a01000ULL, 1082 .ecc_base = 0xf00000000ULL, 1083 .ecc_version = 0x10000000, // version 0, implementation 1 1084 .nvram_machine_id = 0x72, 1085 .machine_id = ss10_id, 1086 .iommu_version = 0x03000000, 1087 .max_mem = 0xf00000000ULL, 1088 .default_cpu_model = "TI SuperSparc II", 1089 }, 1090 /* SS-600MP */ 1091 { 1092 .iommu_base = 0xfe0000000ULL, 1093 .tcx_base = 0xe20000000ULL, 1094 .slavio_base = 0xff0000000ULL, 1095 .ms_kb_base = 0xff1000000ULL, 1096 .serial_base = 0xff1100000ULL, 1097 .nvram_base = 0xff1200000ULL, 1098 .counter_base = 0xff1300000ULL, 1099 .intctl_base = 0xff1400000ULL, 1100 .dma_base = 0xef0081000ULL, 1101 .esp_base = 0xef0080000ULL, 1102 .le_base = 0xef0060000ULL, 1103 .apc_base = 0xefa000000ULL, // XXX should not exist 1104 .aux1_base = 0xff1800000ULL, 1105 .aux2_base = 0xff1a01000ULL, // XXX should not exist 1106 .ecc_base = 0xf00000000ULL, 1107 .ecc_version = 0x00000000, // version 0, implementation 0 1108 .nvram_machine_id = 0x71, 1109 .machine_id = ss600mp_id, 1110 .iommu_version = 0x01000000, 1111 .max_mem = 0xf00000000ULL, 1112 .default_cpu_model = "TI SuperSparc II", 1113 }, 1114 /* SS-20 */ 1115 { 1116 .iommu_base = 0xfe0000000ULL, 1117 .tcx_base = 0xe20000000ULL, 1118 .slavio_base = 0xff0000000ULL, 1119 .ms_kb_base = 0xff1000000ULL, 1120 .serial_base = 0xff1100000ULL, 1121 .nvram_base = 0xff1200000ULL, 1122 .fd_base = 0xff1700000ULL, 1123 .counter_base = 0xff1300000ULL, 1124 .intctl_base = 0xff1400000ULL, 1125 .idreg_base = 0xef0000000ULL, 1126 .dma_base = 0xef0400000ULL, 1127 .esp_base = 0xef0800000ULL, 1128 .le_base = 0xef0c00000ULL, 1129 .bpp_base = 0xef4800000ULL, 1130 .apc_base = 0xefa000000ULL, // XXX should not exist 1131 .aux1_base = 0xff1800000ULL, 1132 .aux2_base = 0xff1a01000ULL, 1133 .dbri_base = 0xee0000000ULL, 1134 .sx_base = 0xf80000000ULL, 1135 .vsimm = { 1136 { 1137 .reg_base = 0x9c000000ULL, 1138 .vram_base = 0xfc000000ULL 1139 }, { 1140 .reg_base = 0x90000000ULL, 1141 .vram_base = 0xf0000000ULL 1142 }, { 1143 .reg_base = 0x94000000ULL 1144 }, { 1145 .reg_base = 0x98000000ULL 1146 } 1147 }, 1148 .ecc_base = 0xf00000000ULL, 1149 .ecc_version = 0x20000000, // version 0, implementation 2 1150 .nvram_machine_id = 0x72, 1151 .machine_id = ss20_id, 1152 .iommu_version = 0x13000000, 1153 .max_mem = 0xf00000000ULL, 1154 .default_cpu_model = "TI SuperSparc II", 1155 }, 1156 /* Voyager */ 1157 { 1158 .iommu_base = 0x10000000, 1159 .tcx_base = 0x50000000, 1160 .slavio_base = 0x70000000, 1161 .ms_kb_base = 0x71000000, 1162 .serial_base = 0x71100000, 1163 .nvram_base = 0x71200000, 1164 .fd_base = 0x71400000, 1165 .counter_base = 0x71d00000, 1166 .intctl_base = 0x71e00000, 1167 .idreg_base = 0x78000000, 1168 .dma_base = 0x78400000, 1169 .esp_base = 0x78800000, 1170 .le_base = 0x78c00000, 1171 .apc_base = 0x71300000, // pmc 1172 .aux1_base = 0x71900000, 1173 .aux2_base = 0x71910000, 1174 .nvram_machine_id = 0x80, 1175 .machine_id = vger_id, 1176 .iommu_version = 0x05000000, 1177 .max_mem = 0x10000000, 1178 .default_cpu_model = "Fujitsu MB86904", 1179 }, 1180 /* LX */ 1181 { 1182 .iommu_base = 0x10000000, 1183 .iommu_pad_base = 0x10004000, 1184 .iommu_pad_len = 0x0fffb000, 1185 .tcx_base = 0x50000000, 1186 .slavio_base = 0x70000000, 1187 .ms_kb_base = 0x71000000, 1188 .serial_base = 0x71100000, 1189 .nvram_base = 0x71200000, 1190 .fd_base = 0x71400000, 1191 .counter_base = 0x71d00000, 1192 .intctl_base = 0x71e00000, 1193 .idreg_base = 0x78000000, 1194 .dma_base = 0x78400000, 1195 .esp_base = 0x78800000, 1196 .le_base = 0x78c00000, 1197 .aux1_base = 0x71900000, 1198 .aux2_base = 0x71910000, 1199 .nvram_machine_id = 0x80, 1200 .machine_id = lx_id, 1201 .iommu_version = 0x04000000, 1202 .max_mem = 0x10000000, 1203 .default_cpu_model = "TI MicroSparc I", 1204 }, 1205 /* SS-4 */ 1206 { 1207 .iommu_base = 0x10000000, 1208 .tcx_base = 0x50000000, 1209 .cs_base = 0x6c000000, 1210 .slavio_base = 0x70000000, 1211 .ms_kb_base = 0x71000000, 1212 .serial_base = 0x71100000, 1213 .nvram_base = 0x71200000, 1214 .fd_base = 0x71400000, 1215 .counter_base = 0x71d00000, 1216 .intctl_base = 0x71e00000, 1217 .idreg_base = 0x78000000, 1218 .dma_base = 0x78400000, 1219 .esp_base = 0x78800000, 1220 .le_base = 0x78c00000, 1221 .apc_base = 0x6a000000, 1222 .aux1_base = 0x71900000, 1223 .aux2_base = 0x71910000, 1224 .nvram_machine_id = 0x80, 1225 .machine_id = ss4_id, 1226 .iommu_version = 0x05000000, 1227 .max_mem = 0x10000000, 1228 .default_cpu_model = "Fujitsu MB86904", 1229 }, 1230 /* SPARCClassic */ 1231 { 1232 .iommu_base = 0x10000000, 1233 .tcx_base = 0x50000000, 1234 .slavio_base = 0x70000000, 1235 .ms_kb_base = 0x71000000, 1236 .serial_base = 0x71100000, 1237 .nvram_base = 0x71200000, 1238 .fd_base = 0x71400000, 1239 .counter_base = 0x71d00000, 1240 .intctl_base = 0x71e00000, 1241 .idreg_base = 0x78000000, 1242 .dma_base = 0x78400000, 1243 .esp_base = 0x78800000, 1244 .le_base = 0x78c00000, 1245 .apc_base = 0x6a000000, 1246 .aux1_base = 0x71900000, 1247 .aux2_base = 0x71910000, 1248 .nvram_machine_id = 0x80, 1249 .machine_id = scls_id, 1250 .iommu_version = 0x05000000, 1251 .max_mem = 0x10000000, 1252 .default_cpu_model = "TI MicroSparc I", 1253 }, 1254 /* SPARCbook */ 1255 { 1256 .iommu_base = 0x10000000, 1257 .tcx_base = 0x50000000, // XXX 1258 .slavio_base = 0x70000000, 1259 .ms_kb_base = 0x71000000, 1260 .serial_base = 0x71100000, 1261 .nvram_base = 0x71200000, 1262 .fd_base = 0x71400000, 1263 .counter_base = 0x71d00000, 1264 .intctl_base = 0x71e00000, 1265 .idreg_base = 0x78000000, 1266 .dma_base = 0x78400000, 1267 .esp_base = 0x78800000, 1268 .le_base = 0x78c00000, 1269 .apc_base = 0x6a000000, 1270 .aux1_base = 0x71900000, 1271 .aux2_base = 0x71910000, 1272 .nvram_machine_id = 0x80, 1273 .machine_id = sbook_id, 1274 .iommu_version = 0x05000000, 1275 .max_mem = 0x10000000, 1276 .default_cpu_model = "TI MicroSparc I", 1277 }, 1278 }; 1279 1280 /* SPARCstation 5 hardware initialisation */ 1281 static void ss5_init(QEMUMachineInitArgs *args) 1282 { 1283 ram_addr_t RAM_size = args->ram_size; 1284 const char *cpu_model = args->cpu_model; 1285 const char *kernel_filename = args->kernel_filename; 1286 const char *kernel_cmdline = args->kernel_cmdline; 1287 const char *initrd_filename = args->initrd_filename; 1288 const char *boot_device = args->boot_device; 1289 sun4m_hw_init(&sun4m_hwdefs[0], RAM_size, boot_device, kernel_filename, 1290 kernel_cmdline, initrd_filename, cpu_model); 1291 } 1292 1293 /* SPARCstation 10 hardware initialisation */ 1294 static void ss10_init(QEMUMachineInitArgs *args) 1295 { 1296 ram_addr_t RAM_size = args->ram_size; 1297 const char *cpu_model = args->cpu_model; 1298 const char *kernel_filename = args->kernel_filename; 1299 const char *kernel_cmdline = args->kernel_cmdline; 1300 const char *initrd_filename = args->initrd_filename; 1301 const char *boot_device = args->boot_device; 1302 sun4m_hw_init(&sun4m_hwdefs[1], RAM_size, boot_device, kernel_filename, 1303 kernel_cmdline, initrd_filename, cpu_model); 1304 } 1305 1306 /* SPARCserver 600MP hardware initialisation */ 1307 static void ss600mp_init(QEMUMachineInitArgs *args) 1308 { 1309 ram_addr_t RAM_size = args->ram_size; 1310 const char *cpu_model = args->cpu_model; 1311 const char *kernel_filename = args->kernel_filename; 1312 const char *kernel_cmdline = args->kernel_cmdline; 1313 const char *initrd_filename = args->initrd_filename; 1314 const char *boot_device = args->boot_device; 1315 sun4m_hw_init(&sun4m_hwdefs[2], RAM_size, boot_device, kernel_filename, 1316 kernel_cmdline, initrd_filename, cpu_model); 1317 } 1318 1319 /* SPARCstation 20 hardware initialisation */ 1320 static void ss20_init(QEMUMachineInitArgs *args) 1321 { 1322 ram_addr_t RAM_size = args->ram_size; 1323 const char *cpu_model = args->cpu_model; 1324 const char *kernel_filename = args->kernel_filename; 1325 const char *kernel_cmdline = args->kernel_cmdline; 1326 const char *initrd_filename = args->initrd_filename; 1327 const char *boot_device = args->boot_device; 1328 sun4m_hw_init(&sun4m_hwdefs[3], RAM_size, boot_device, kernel_filename, 1329 kernel_cmdline, initrd_filename, cpu_model); 1330 } 1331 1332 /* SPARCstation Voyager hardware initialisation */ 1333 static void vger_init(QEMUMachineInitArgs *args) 1334 { 1335 ram_addr_t RAM_size = args->ram_size; 1336 const char *cpu_model = args->cpu_model; 1337 const char *kernel_filename = args->kernel_filename; 1338 const char *kernel_cmdline = args->kernel_cmdline; 1339 const char *initrd_filename = args->initrd_filename; 1340 const char *boot_device = args->boot_device; 1341 sun4m_hw_init(&sun4m_hwdefs[4], RAM_size, boot_device, kernel_filename, 1342 kernel_cmdline, initrd_filename, cpu_model); 1343 } 1344 1345 /* SPARCstation LX hardware initialisation */ 1346 static void ss_lx_init(QEMUMachineInitArgs *args) 1347 { 1348 ram_addr_t RAM_size = args->ram_size; 1349 const char *cpu_model = args->cpu_model; 1350 const char *kernel_filename = args->kernel_filename; 1351 const char *kernel_cmdline = args->kernel_cmdline; 1352 const char *initrd_filename = args->initrd_filename; 1353 const char *boot_device = args->boot_device; 1354 sun4m_hw_init(&sun4m_hwdefs[5], RAM_size, boot_device, kernel_filename, 1355 kernel_cmdline, initrd_filename, cpu_model); 1356 } 1357 1358 /* SPARCstation 4 hardware initialisation */ 1359 static void ss4_init(QEMUMachineInitArgs *args) 1360 { 1361 ram_addr_t RAM_size = args->ram_size; 1362 const char *cpu_model = args->cpu_model; 1363 const char *kernel_filename = args->kernel_filename; 1364 const char *kernel_cmdline = args->kernel_cmdline; 1365 const char *initrd_filename = args->initrd_filename; 1366 const char *boot_device = args->boot_device; 1367 sun4m_hw_init(&sun4m_hwdefs[6], RAM_size, boot_device, kernel_filename, 1368 kernel_cmdline, initrd_filename, cpu_model); 1369 } 1370 1371 /* SPARCClassic hardware initialisation */ 1372 static void scls_init(QEMUMachineInitArgs *args) 1373 { 1374 ram_addr_t RAM_size = args->ram_size; 1375 const char *cpu_model = args->cpu_model; 1376 const char *kernel_filename = args->kernel_filename; 1377 const char *kernel_cmdline = args->kernel_cmdline; 1378 const char *initrd_filename = args->initrd_filename; 1379 const char *boot_device = args->boot_device; 1380 sun4m_hw_init(&sun4m_hwdefs[7], RAM_size, boot_device, kernel_filename, 1381 kernel_cmdline, initrd_filename, cpu_model); 1382 } 1383 1384 /* SPARCbook hardware initialisation */ 1385 static void sbook_init(QEMUMachineInitArgs *args) 1386 { 1387 ram_addr_t RAM_size = args->ram_size; 1388 const char *cpu_model = args->cpu_model; 1389 const char *kernel_filename = args->kernel_filename; 1390 const char *kernel_cmdline = args->kernel_cmdline; 1391 const char *initrd_filename = args->initrd_filename; 1392 const char *boot_device = args->boot_device; 1393 sun4m_hw_init(&sun4m_hwdefs[8], RAM_size, boot_device, kernel_filename, 1394 kernel_cmdline, initrd_filename, cpu_model); 1395 } 1396 1397 static QEMUMachine ss5_machine = { 1398 .name = "SS-5", 1399 .desc = "Sun4m platform, SPARCstation 5", 1400 .init = ss5_init, 1401 .block_default_type = IF_SCSI, 1402 .is_default = 1, 1403 DEFAULT_MACHINE_OPTIONS, 1404 }; 1405 1406 static QEMUMachine ss10_machine = { 1407 .name = "SS-10", 1408 .desc = "Sun4m platform, SPARCstation 10", 1409 .init = ss10_init, 1410 .block_default_type = IF_SCSI, 1411 .max_cpus = 4, 1412 DEFAULT_MACHINE_OPTIONS, 1413 }; 1414 1415 static QEMUMachine ss600mp_machine = { 1416 .name = "SS-600MP", 1417 .desc = "Sun4m platform, SPARCserver 600MP", 1418 .init = ss600mp_init, 1419 .block_default_type = IF_SCSI, 1420 .max_cpus = 4, 1421 DEFAULT_MACHINE_OPTIONS, 1422 }; 1423 1424 static QEMUMachine ss20_machine = { 1425 .name = "SS-20", 1426 .desc = "Sun4m platform, SPARCstation 20", 1427 .init = ss20_init, 1428 .block_default_type = IF_SCSI, 1429 .max_cpus = 4, 1430 DEFAULT_MACHINE_OPTIONS, 1431 }; 1432 1433 static QEMUMachine voyager_machine = { 1434 .name = "Voyager", 1435 .desc = "Sun4m platform, SPARCstation Voyager", 1436 .init = vger_init, 1437 .block_default_type = IF_SCSI, 1438 DEFAULT_MACHINE_OPTIONS, 1439 }; 1440 1441 static QEMUMachine ss_lx_machine = { 1442 .name = "LX", 1443 .desc = "Sun4m platform, SPARCstation LX", 1444 .init = ss_lx_init, 1445 .block_default_type = IF_SCSI, 1446 DEFAULT_MACHINE_OPTIONS, 1447 }; 1448 1449 static QEMUMachine ss4_machine = { 1450 .name = "SS-4", 1451 .desc = "Sun4m platform, SPARCstation 4", 1452 .init = ss4_init, 1453 .block_default_type = IF_SCSI, 1454 DEFAULT_MACHINE_OPTIONS, 1455 }; 1456 1457 static QEMUMachine scls_machine = { 1458 .name = "SPARCClassic", 1459 .desc = "Sun4m platform, SPARCClassic", 1460 .init = scls_init, 1461 .block_default_type = IF_SCSI, 1462 DEFAULT_MACHINE_OPTIONS, 1463 }; 1464 1465 static QEMUMachine sbook_machine = { 1466 .name = "SPARCbook", 1467 .desc = "Sun4m platform, SPARCbook", 1468 .init = sbook_init, 1469 .block_default_type = IF_SCSI, 1470 DEFAULT_MACHINE_OPTIONS, 1471 }; 1472 1473 static void sun4m_register_types(void) 1474 { 1475 type_register_static(&idreg_info); 1476 type_register_static(&afx_info); 1477 type_register_static(&prom_info); 1478 type_register_static(&ram_info); 1479 } 1480 1481 static void sun4m_machine_init(void) 1482 { 1483 qemu_register_machine(&ss5_machine); 1484 qemu_register_machine(&ss10_machine); 1485 qemu_register_machine(&ss600mp_machine); 1486 qemu_register_machine(&ss20_machine); 1487 qemu_register_machine(&voyager_machine); 1488 qemu_register_machine(&ss_lx_machine); 1489 qemu_register_machine(&ss4_machine); 1490 qemu_register_machine(&scls_machine); 1491 qemu_register_machine(&sbook_machine); 1492 } 1493 1494 type_init(sun4m_register_types) 1495 machine_init(sun4m_machine_init); 1496