1 /* 2 * QEMU Sun4m & Sun4d & Sun4c System Emulator 3 * 4 * Copyright (c) 2003-2005 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "qapi/error.h" 28 #include "qemu/datadir.h" 29 #include "qemu-common.h" 30 #include "cpu.h" 31 #include "hw/sysbus.h" 32 #include "qemu/error-report.h" 33 #include "qemu/timer.h" 34 #include "hw/sparc/sun4m_iommu.h" 35 #include "hw/rtc/m48t59.h" 36 #include "migration/vmstate.h" 37 #include "hw/sparc/sparc32_dma.h" 38 #include "hw/block/fdc.h" 39 #include "sysemu/reset.h" 40 #include "sysemu/runstate.h" 41 #include "sysemu/sysemu.h" 42 #include "net/net.h" 43 #include "hw/boards.h" 44 #include "hw/scsi/esp.h" 45 #include "hw/nvram/sun_nvram.h" 46 #include "hw/qdev-properties.h" 47 #include "hw/nvram/chrp_nvram.h" 48 #include "hw/nvram/fw_cfg.h" 49 #include "hw/char/escc.h" 50 #include "hw/misc/empty_slot.h" 51 #include "hw/misc/unimp.h" 52 #include "hw/irq.h" 53 #include "hw/or-irq.h" 54 #include "hw/loader.h" 55 #include "elf.h" 56 #include "trace.h" 57 #include "qom/object.h" 58 59 /* 60 * Sun4m architecture was used in the following machines: 61 * 62 * SPARCserver 6xxMP/xx 63 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15), 64 * SPARCclassic X (4/10) 65 * SPARCstation LX/ZX (4/30) 66 * SPARCstation Voyager 67 * SPARCstation 10/xx, SPARCserver 10/xx 68 * SPARCstation 5, SPARCserver 5 69 * SPARCstation 20/xx, SPARCserver 20 70 * SPARCstation 4 71 * 72 * See for example: http://www.sunhelp.org/faq/sunref1.html 73 */ 74 75 #define KERNEL_LOAD_ADDR 0x00004000 76 #define CMDLINE_ADDR 0x007ff000 77 #define INITRD_LOAD_ADDR 0x00800000 78 #define PROM_SIZE_MAX (1 * MiB) 79 #define PROM_VADDR 0xffd00000 80 #define PROM_FILENAME "openbios-sparc32" 81 #define CFG_ADDR 0xd00000510ULL 82 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00) 83 #define FW_CFG_SUN4M_WIDTH (FW_CFG_ARCH_LOCAL + 0x01) 84 #define FW_CFG_SUN4M_HEIGHT (FW_CFG_ARCH_LOCAL + 0x02) 85 86 #define MAX_CPUS 16 87 #define MAX_PILS 16 88 #define MAX_VSIMMS 4 89 90 #define ESCC_CLOCK 4915200 91 92 struct sun4m_hwdef { 93 hwaddr iommu_base, iommu_pad_base, iommu_pad_len, slavio_base; 94 hwaddr intctl_base, counter_base, nvram_base, ms_kb_base; 95 hwaddr serial_base, fd_base; 96 hwaddr afx_base, idreg_base, dma_base, esp_base, le_base; 97 hwaddr tcx_base, cs_base, apc_base, aux1_base, aux2_base; 98 hwaddr bpp_base, dbri_base, sx_base; 99 struct { 100 hwaddr reg_base, vram_base; 101 } vsimm[MAX_VSIMMS]; 102 hwaddr ecc_base; 103 uint64_t max_mem; 104 uint32_t ecc_version; 105 uint32_t iommu_version; 106 uint16_t machine_id; 107 uint8_t nvram_machine_id; 108 }; 109 110 struct Sun4mMachineClass { 111 /*< private >*/ 112 MachineClass parent_obj; 113 /*< public >*/ 114 const struct sun4m_hwdef *hwdef; 115 }; 116 typedef struct Sun4mMachineClass Sun4mMachineClass; 117 118 #define TYPE_SUN4M_MACHINE MACHINE_TYPE_NAME("sun4m-common") 119 DECLARE_CLASS_CHECKERS(Sun4mMachineClass, SUN4M_MACHINE, TYPE_SUN4M_MACHINE) 120 121 const char *fw_cfg_arch_key_name(uint16_t key) 122 { 123 static const struct { 124 uint16_t key; 125 const char *name; 126 } fw_cfg_arch_wellknown_keys[] = { 127 {FW_CFG_SUN4M_DEPTH, "depth"}, 128 {FW_CFG_SUN4M_WIDTH, "width"}, 129 {FW_CFG_SUN4M_HEIGHT, "height"}, 130 }; 131 132 for (size_t i = 0; i < ARRAY_SIZE(fw_cfg_arch_wellknown_keys); i++) { 133 if (fw_cfg_arch_wellknown_keys[i].key == key) { 134 return fw_cfg_arch_wellknown_keys[i].name; 135 } 136 } 137 return NULL; 138 } 139 140 static void fw_cfg_boot_set(void *opaque, const char *boot_device, 141 Error **errp) 142 { 143 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); 144 } 145 146 static void nvram_init(Nvram *nvram, uint8_t *macaddr, 147 const char *cmdline, const char *boot_devices, 148 ram_addr_t RAM_size, uint32_t kernel_size, 149 int width, int height, int depth, 150 int nvram_machine_id, const char *arch) 151 { 152 unsigned int i; 153 int sysp_end; 154 uint8_t image[0x1ff0]; 155 NvramClass *k = NVRAM_GET_CLASS(nvram); 156 157 memset(image, '\0', sizeof(image)); 158 159 /* OpenBIOS nvram variables partition */ 160 sysp_end = chrp_nvram_create_system_partition(image, 0, 0x1fd0); 161 162 /* Free space partition */ 163 chrp_nvram_create_free_partition(&image[sysp_end], 0x1fd0 - sysp_end); 164 165 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 166 nvram_machine_id); 167 168 for (i = 0; i < sizeof(image); i++) { 169 (k->write)(nvram, i, image[i]); 170 } 171 } 172 173 void cpu_check_irqs(CPUSPARCState *env) 174 { 175 CPUState *cs; 176 177 /* We should be holding the BQL before we mess with IRQs */ 178 g_assert(qemu_mutex_iothread_locked()); 179 180 if (env->pil_in && (env->interrupt_index == 0 || 181 (env->interrupt_index & ~15) == TT_EXTINT)) { 182 unsigned int i; 183 184 for (i = 15; i > 0; i--) { 185 if (env->pil_in & (1 << i)) { 186 int old_interrupt = env->interrupt_index; 187 188 env->interrupt_index = TT_EXTINT | i; 189 if (old_interrupt != env->interrupt_index) { 190 cs = env_cpu(env); 191 trace_sun4m_cpu_interrupt(i); 192 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 193 } 194 break; 195 } 196 } 197 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) { 198 cs = env_cpu(env); 199 trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15); 200 env->interrupt_index = 0; 201 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 202 } 203 } 204 205 static void cpu_kick_irq(SPARCCPU *cpu) 206 { 207 CPUSPARCState *env = &cpu->env; 208 CPUState *cs = CPU(cpu); 209 210 cs->halted = 0; 211 cpu_check_irqs(env); 212 qemu_cpu_kick(cs); 213 } 214 215 static void cpu_set_irq(void *opaque, int irq, int level) 216 { 217 SPARCCPU *cpu = opaque; 218 CPUSPARCState *env = &cpu->env; 219 220 if (level) { 221 trace_sun4m_cpu_set_irq_raise(irq); 222 env->pil_in |= 1 << irq; 223 cpu_kick_irq(cpu); 224 } else { 225 trace_sun4m_cpu_set_irq_lower(irq); 226 env->pil_in &= ~(1 << irq); 227 cpu_check_irqs(env); 228 } 229 } 230 231 static void dummy_cpu_set_irq(void *opaque, int irq, int level) 232 { 233 } 234 235 static void sun4m_cpu_reset(void *opaque) 236 { 237 SPARCCPU *cpu = opaque; 238 CPUState *cs = CPU(cpu); 239 240 cpu_reset(cs); 241 } 242 243 static void cpu_halt_signal(void *opaque, int irq, int level) 244 { 245 if (level && current_cpu) { 246 cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT); 247 } 248 } 249 250 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 251 { 252 return addr - 0xf0000000ULL; 253 } 254 255 static unsigned long sun4m_load_kernel(const char *kernel_filename, 256 const char *initrd_filename, 257 ram_addr_t RAM_size, 258 uint32_t *initrd_size) 259 { 260 int linux_boot; 261 unsigned int i; 262 long kernel_size; 263 uint8_t *ptr; 264 265 linux_boot = (kernel_filename != NULL); 266 267 kernel_size = 0; 268 if (linux_boot) { 269 int bswap_needed; 270 271 #ifdef BSWAP_NEEDED 272 bswap_needed = 1; 273 #else 274 bswap_needed = 0; 275 #endif 276 kernel_size = load_elf(kernel_filename, NULL, 277 translate_kernel_address, NULL, 278 NULL, NULL, NULL, NULL, 1, EM_SPARC, 0, 0); 279 if (kernel_size < 0) 280 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR, 281 RAM_size - KERNEL_LOAD_ADDR, bswap_needed, 282 TARGET_PAGE_SIZE); 283 if (kernel_size < 0) 284 kernel_size = load_image_targphys(kernel_filename, 285 KERNEL_LOAD_ADDR, 286 RAM_size - KERNEL_LOAD_ADDR); 287 if (kernel_size < 0) { 288 error_report("could not load kernel '%s'", kernel_filename); 289 exit(1); 290 } 291 292 /* load initrd */ 293 *initrd_size = 0; 294 if (initrd_filename) { 295 *initrd_size = load_image_targphys(initrd_filename, 296 INITRD_LOAD_ADDR, 297 RAM_size - INITRD_LOAD_ADDR); 298 if ((int)*initrd_size < 0) { 299 error_report("could not load initial ram disk '%s'", 300 initrd_filename); 301 exit(1); 302 } 303 } 304 if (*initrd_size > 0) { 305 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { 306 ptr = rom_ptr(KERNEL_LOAD_ADDR + i, 24); 307 if (ptr && ldl_p(ptr) == 0x48647253) { /* HdrS */ 308 stl_p(ptr + 16, INITRD_LOAD_ADDR); 309 stl_p(ptr + 20, *initrd_size); 310 break; 311 } 312 } 313 } 314 } 315 return kernel_size; 316 } 317 318 static void *iommu_init(hwaddr addr, uint32_t version, qemu_irq irq) 319 { 320 DeviceState *dev; 321 SysBusDevice *s; 322 323 dev = qdev_new(TYPE_SUN4M_IOMMU); 324 qdev_prop_set_uint32(dev, "version", version); 325 s = SYS_BUS_DEVICE(dev); 326 sysbus_realize_and_unref(s, &error_fatal); 327 sysbus_connect_irq(s, 0, irq); 328 sysbus_mmio_map(s, 0, addr); 329 330 return s; 331 } 332 333 static void *sparc32_dma_init(hwaddr dma_base, 334 hwaddr esp_base, qemu_irq espdma_irq, 335 hwaddr le_base, qemu_irq ledma_irq, NICInfo *nd) 336 { 337 DeviceState *dma; 338 ESPDMADeviceState *espdma; 339 LEDMADeviceState *ledma; 340 SysBusESPState *esp; 341 SysBusPCNetState *lance; 342 343 dma = qdev_new(TYPE_SPARC32_DMA); 344 espdma = SPARC32_ESPDMA_DEVICE(object_resolve_path_component( 345 OBJECT(dma), "espdma")); 346 sysbus_connect_irq(SYS_BUS_DEVICE(espdma), 0, espdma_irq); 347 348 esp = SYSBUS_ESP(object_resolve_path_component(OBJECT(espdma), "esp")); 349 350 ledma = SPARC32_LEDMA_DEVICE(object_resolve_path_component( 351 OBJECT(dma), "ledma")); 352 sysbus_connect_irq(SYS_BUS_DEVICE(ledma), 0, ledma_irq); 353 354 lance = SYSBUS_PCNET(object_resolve_path_component( 355 OBJECT(ledma), "lance")); 356 qdev_set_nic_properties(DEVICE(lance), nd); 357 358 sysbus_realize_and_unref(SYS_BUS_DEVICE(dma), &error_fatal); 359 sysbus_mmio_map(SYS_BUS_DEVICE(dma), 0, dma_base); 360 361 sysbus_mmio_map(SYS_BUS_DEVICE(esp), 0, esp_base); 362 scsi_bus_legacy_handle_cmdline(&esp->esp.bus); 363 364 sysbus_mmio_map(SYS_BUS_DEVICE(lance), 0, le_base); 365 366 return dma; 367 } 368 369 static DeviceState *slavio_intctl_init(hwaddr addr, 370 hwaddr addrg, 371 qemu_irq **parent_irq) 372 { 373 DeviceState *dev; 374 SysBusDevice *s; 375 unsigned int i, j; 376 377 dev = qdev_new("slavio_intctl"); 378 379 s = SYS_BUS_DEVICE(dev); 380 sysbus_realize_and_unref(s, &error_fatal); 381 382 for (i = 0; i < MAX_CPUS; i++) { 383 for (j = 0; j < MAX_PILS; j++) { 384 sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]); 385 } 386 } 387 sysbus_mmio_map(s, 0, addrg); 388 for (i = 0; i < MAX_CPUS; i++) { 389 sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE); 390 } 391 392 return dev; 393 } 394 395 #define SYS_TIMER_OFFSET 0x10000ULL 396 #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu) 397 398 static void slavio_timer_init_all(hwaddr addr, qemu_irq master_irq, 399 qemu_irq *cpu_irqs, unsigned int num_cpus) 400 { 401 DeviceState *dev; 402 SysBusDevice *s; 403 unsigned int i; 404 405 dev = qdev_new("slavio_timer"); 406 qdev_prop_set_uint32(dev, "num_cpus", num_cpus); 407 s = SYS_BUS_DEVICE(dev); 408 sysbus_realize_and_unref(s, &error_fatal); 409 sysbus_connect_irq(s, 0, master_irq); 410 sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET); 411 412 for (i = 0; i < MAX_CPUS; i++) { 413 sysbus_mmio_map(s, i + 1, addr + (hwaddr)CPU_TIMER_OFFSET(i)); 414 sysbus_connect_irq(s, i + 1, cpu_irqs[i]); 415 } 416 } 417 418 static qemu_irq slavio_system_powerdown; 419 420 static void slavio_powerdown_req(Notifier *n, void *opaque) 421 { 422 qemu_irq_raise(slavio_system_powerdown); 423 } 424 425 static Notifier slavio_system_powerdown_notifier = { 426 .notify = slavio_powerdown_req 427 }; 428 429 #define MISC_LEDS 0x01600000 430 #define MISC_CFG 0x01800000 431 #define MISC_DIAG 0x01a00000 432 #define MISC_MDM 0x01b00000 433 #define MISC_SYS 0x01f00000 434 435 static void slavio_misc_init(hwaddr base, 436 hwaddr aux1_base, 437 hwaddr aux2_base, qemu_irq irq, 438 qemu_irq fdc_tc) 439 { 440 DeviceState *dev; 441 SysBusDevice *s; 442 443 dev = qdev_new("slavio_misc"); 444 s = SYS_BUS_DEVICE(dev); 445 sysbus_realize_and_unref(s, &error_fatal); 446 if (base) { 447 /* 8 bit registers */ 448 /* Slavio control */ 449 sysbus_mmio_map(s, 0, base + MISC_CFG); 450 /* Diagnostics */ 451 sysbus_mmio_map(s, 1, base + MISC_DIAG); 452 /* Modem control */ 453 sysbus_mmio_map(s, 2, base + MISC_MDM); 454 /* 16 bit registers */ 455 /* ss600mp diag LEDs */ 456 sysbus_mmio_map(s, 3, base + MISC_LEDS); 457 /* 32 bit registers */ 458 /* System control */ 459 sysbus_mmio_map(s, 4, base + MISC_SYS); 460 } 461 if (aux1_base) { 462 /* AUX 1 (Misc System Functions) */ 463 sysbus_mmio_map(s, 5, aux1_base); 464 } 465 if (aux2_base) { 466 /* AUX 2 (Software Powerdown Control) */ 467 sysbus_mmio_map(s, 6, aux2_base); 468 } 469 sysbus_connect_irq(s, 0, irq); 470 sysbus_connect_irq(s, 1, fdc_tc); 471 slavio_system_powerdown = qdev_get_gpio_in(dev, 0); 472 qemu_register_powerdown_notifier(&slavio_system_powerdown_notifier); 473 } 474 475 static void ecc_init(hwaddr base, qemu_irq irq, uint32_t version) 476 { 477 DeviceState *dev; 478 SysBusDevice *s; 479 480 dev = qdev_new("eccmemctl"); 481 qdev_prop_set_uint32(dev, "version", version); 482 s = SYS_BUS_DEVICE(dev); 483 sysbus_realize_and_unref(s, &error_fatal); 484 sysbus_connect_irq(s, 0, irq); 485 sysbus_mmio_map(s, 0, base); 486 if (version == 0) { // SS-600MP only 487 sysbus_mmio_map(s, 1, base + 0x1000); 488 } 489 } 490 491 static void apc_init(hwaddr power_base, qemu_irq cpu_halt) 492 { 493 DeviceState *dev; 494 SysBusDevice *s; 495 496 dev = qdev_new("apc"); 497 s = SYS_BUS_DEVICE(dev); 498 sysbus_realize_and_unref(s, &error_fatal); 499 /* Power management (APC) XXX: not a Slavio device */ 500 sysbus_mmio_map(s, 0, power_base); 501 sysbus_connect_irq(s, 0, cpu_halt); 502 } 503 504 static void tcx_init(hwaddr addr, qemu_irq irq, int vram_size, int width, 505 int height, int depth) 506 { 507 DeviceState *dev; 508 SysBusDevice *s; 509 510 dev = qdev_new("sun-tcx"); 511 qdev_prop_set_uint32(dev, "vram_size", vram_size); 512 qdev_prop_set_uint16(dev, "width", width); 513 qdev_prop_set_uint16(dev, "height", height); 514 qdev_prop_set_uint16(dev, "depth", depth); 515 s = SYS_BUS_DEVICE(dev); 516 sysbus_realize_and_unref(s, &error_fatal); 517 518 /* 10/ROM : FCode ROM */ 519 sysbus_mmio_map(s, 0, addr); 520 /* 2/STIP : Stipple */ 521 sysbus_mmio_map(s, 1, addr + 0x04000000ULL); 522 /* 3/BLIT : Blitter */ 523 sysbus_mmio_map(s, 2, addr + 0x06000000ULL); 524 /* 5/RSTIP : Raw Stipple */ 525 sysbus_mmio_map(s, 3, addr + 0x0c000000ULL); 526 /* 6/RBLIT : Raw Blitter */ 527 sysbus_mmio_map(s, 4, addr + 0x0e000000ULL); 528 /* 7/TEC : Transform Engine */ 529 sysbus_mmio_map(s, 5, addr + 0x00700000ULL); 530 /* 8/CMAP : DAC */ 531 sysbus_mmio_map(s, 6, addr + 0x00200000ULL); 532 /* 9/THC : */ 533 if (depth == 8) { 534 sysbus_mmio_map(s, 7, addr + 0x00300000ULL); 535 } else { 536 sysbus_mmio_map(s, 7, addr + 0x00301000ULL); 537 } 538 /* 11/DHC : */ 539 sysbus_mmio_map(s, 8, addr + 0x00240000ULL); 540 /* 12/ALT : */ 541 sysbus_mmio_map(s, 9, addr + 0x00280000ULL); 542 /* 0/DFB8 : 8-bit plane */ 543 sysbus_mmio_map(s, 10, addr + 0x00800000ULL); 544 /* 1/DFB24 : 24bit plane */ 545 sysbus_mmio_map(s, 11, addr + 0x02000000ULL); 546 /* 4/RDFB32: Raw framebuffer. Control plane */ 547 sysbus_mmio_map(s, 12, addr + 0x0a000000ULL); 548 /* 9/THC24bits : NetBSD writes here even with 8-bit display: dummy */ 549 if (depth == 8) { 550 sysbus_mmio_map(s, 13, addr + 0x00301000ULL); 551 } 552 553 sysbus_connect_irq(s, 0, irq); 554 } 555 556 static void cg3_init(hwaddr addr, qemu_irq irq, int vram_size, int width, 557 int height, int depth) 558 { 559 DeviceState *dev; 560 SysBusDevice *s; 561 562 dev = qdev_new("cgthree"); 563 qdev_prop_set_uint32(dev, "vram-size", vram_size); 564 qdev_prop_set_uint16(dev, "width", width); 565 qdev_prop_set_uint16(dev, "height", height); 566 qdev_prop_set_uint16(dev, "depth", depth); 567 s = SYS_BUS_DEVICE(dev); 568 sysbus_realize_and_unref(s, &error_fatal); 569 570 /* FCode ROM */ 571 sysbus_mmio_map(s, 0, addr); 572 /* DAC */ 573 sysbus_mmio_map(s, 1, addr + 0x400000ULL); 574 /* 8-bit plane */ 575 sysbus_mmio_map(s, 2, addr + 0x800000ULL); 576 577 sysbus_connect_irq(s, 0, irq); 578 } 579 580 /* NCR89C100/MACIO Internal ID register */ 581 582 #define TYPE_MACIO_ID_REGISTER "macio_idreg" 583 584 static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 }; 585 586 static void idreg_init(hwaddr addr) 587 { 588 DeviceState *dev; 589 SysBusDevice *s; 590 591 dev = qdev_new(TYPE_MACIO_ID_REGISTER); 592 s = SYS_BUS_DEVICE(dev); 593 sysbus_realize_and_unref(s, &error_fatal); 594 595 sysbus_mmio_map(s, 0, addr); 596 address_space_write_rom(&address_space_memory, addr, 597 MEMTXATTRS_UNSPECIFIED, 598 idreg_data, sizeof(idreg_data)); 599 } 600 601 OBJECT_DECLARE_SIMPLE_TYPE(IDRegState, MACIO_ID_REGISTER) 602 603 struct IDRegState { 604 SysBusDevice parent_obj; 605 606 MemoryRegion mem; 607 }; 608 609 static void idreg_realize(DeviceState *ds, Error **errp) 610 { 611 IDRegState *s = MACIO_ID_REGISTER(ds); 612 SysBusDevice *dev = SYS_BUS_DEVICE(ds); 613 Error *local_err = NULL; 614 615 memory_region_init_ram_nomigrate(&s->mem, OBJECT(ds), "sun4m.idreg", 616 sizeof(idreg_data), &local_err); 617 if (local_err) { 618 error_propagate(errp, local_err); 619 return; 620 } 621 622 vmstate_register_ram_global(&s->mem); 623 memory_region_set_readonly(&s->mem, true); 624 sysbus_init_mmio(dev, &s->mem); 625 } 626 627 static void idreg_class_init(ObjectClass *oc, void *data) 628 { 629 DeviceClass *dc = DEVICE_CLASS(oc); 630 631 dc->realize = idreg_realize; 632 } 633 634 static const TypeInfo idreg_info = { 635 .name = TYPE_MACIO_ID_REGISTER, 636 .parent = TYPE_SYS_BUS_DEVICE, 637 .instance_size = sizeof(IDRegState), 638 .class_init = idreg_class_init, 639 }; 640 641 #define TYPE_TCX_AFX "tcx_afx" 642 OBJECT_DECLARE_SIMPLE_TYPE(AFXState, TCX_AFX) 643 644 struct AFXState { 645 SysBusDevice parent_obj; 646 647 MemoryRegion mem; 648 }; 649 650 /* SS-5 TCX AFX register */ 651 static void afx_init(hwaddr addr) 652 { 653 DeviceState *dev; 654 SysBusDevice *s; 655 656 dev = qdev_new(TYPE_TCX_AFX); 657 s = SYS_BUS_DEVICE(dev); 658 sysbus_realize_and_unref(s, &error_fatal); 659 660 sysbus_mmio_map(s, 0, addr); 661 } 662 663 static void afx_realize(DeviceState *ds, Error **errp) 664 { 665 AFXState *s = TCX_AFX(ds); 666 SysBusDevice *dev = SYS_BUS_DEVICE(ds); 667 Error *local_err = NULL; 668 669 memory_region_init_ram_nomigrate(&s->mem, OBJECT(ds), "sun4m.afx", 4, 670 &local_err); 671 if (local_err) { 672 error_propagate(errp, local_err); 673 return; 674 } 675 676 vmstate_register_ram_global(&s->mem); 677 sysbus_init_mmio(dev, &s->mem); 678 } 679 680 static void afx_class_init(ObjectClass *oc, void *data) 681 { 682 DeviceClass *dc = DEVICE_CLASS(oc); 683 684 dc->realize = afx_realize; 685 } 686 687 static const TypeInfo afx_info = { 688 .name = TYPE_TCX_AFX, 689 .parent = TYPE_SYS_BUS_DEVICE, 690 .instance_size = sizeof(AFXState), 691 .class_init = afx_class_init, 692 }; 693 694 #define TYPE_OPENPROM "openprom" 695 typedef struct PROMState PROMState; 696 DECLARE_INSTANCE_CHECKER(PROMState, OPENPROM, 697 TYPE_OPENPROM) 698 699 struct PROMState { 700 SysBusDevice parent_obj; 701 702 MemoryRegion prom; 703 }; 704 705 /* Boot PROM (OpenBIOS) */ 706 static uint64_t translate_prom_address(void *opaque, uint64_t addr) 707 { 708 hwaddr *base_addr = (hwaddr *)opaque; 709 return addr + *base_addr - PROM_VADDR; 710 } 711 712 static void prom_init(hwaddr addr, const char *bios_name) 713 { 714 DeviceState *dev; 715 SysBusDevice *s; 716 char *filename; 717 int ret; 718 719 dev = qdev_new(TYPE_OPENPROM); 720 s = SYS_BUS_DEVICE(dev); 721 sysbus_realize_and_unref(s, &error_fatal); 722 723 sysbus_mmio_map(s, 0, addr); 724 725 /* load boot prom */ 726 if (bios_name == NULL) { 727 bios_name = PROM_FILENAME; 728 } 729 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 730 if (filename) { 731 ret = load_elf(filename, NULL, 732 translate_prom_address, &addr, NULL, 733 NULL, NULL, NULL, 1, EM_SPARC, 0, 0); 734 if (ret < 0 || ret > PROM_SIZE_MAX) { 735 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX); 736 } 737 g_free(filename); 738 } else { 739 ret = -1; 740 } 741 if (ret < 0 || ret > PROM_SIZE_MAX) { 742 error_report("could not load prom '%s'", bios_name); 743 exit(1); 744 } 745 } 746 747 static void prom_realize(DeviceState *ds, Error **errp) 748 { 749 PROMState *s = OPENPROM(ds); 750 SysBusDevice *dev = SYS_BUS_DEVICE(ds); 751 Error *local_err = NULL; 752 753 memory_region_init_ram_nomigrate(&s->prom, OBJECT(ds), "sun4m.prom", 754 PROM_SIZE_MAX, &local_err); 755 if (local_err) { 756 error_propagate(errp, local_err); 757 return; 758 } 759 760 vmstate_register_ram_global(&s->prom); 761 memory_region_set_readonly(&s->prom, true); 762 sysbus_init_mmio(dev, &s->prom); 763 } 764 765 static Property prom_properties[] = { 766 {/* end of property list */}, 767 }; 768 769 static void prom_class_init(ObjectClass *klass, void *data) 770 { 771 DeviceClass *dc = DEVICE_CLASS(klass); 772 773 device_class_set_props(dc, prom_properties); 774 dc->realize = prom_realize; 775 } 776 777 static const TypeInfo prom_info = { 778 .name = TYPE_OPENPROM, 779 .parent = TYPE_SYS_BUS_DEVICE, 780 .instance_size = sizeof(PROMState), 781 .class_init = prom_class_init, 782 }; 783 784 #define TYPE_SUN4M_MEMORY "memory" 785 typedef struct RamDevice RamDevice; 786 DECLARE_INSTANCE_CHECKER(RamDevice, SUN4M_RAM, 787 TYPE_SUN4M_MEMORY) 788 789 struct RamDevice { 790 SysBusDevice parent_obj; 791 HostMemoryBackend *memdev; 792 }; 793 794 /* System RAM */ 795 static void ram_realize(DeviceState *dev, Error **errp) 796 { 797 RamDevice *d = SUN4M_RAM(dev); 798 MemoryRegion *ram = host_memory_backend_get_memory(d->memdev); 799 800 sysbus_init_mmio(SYS_BUS_DEVICE(dev), ram); 801 } 802 803 static void ram_initfn(Object *obj) 804 { 805 RamDevice *d = SUN4M_RAM(obj); 806 object_property_add_link(obj, "memdev", TYPE_MEMORY_BACKEND, 807 (Object **)&d->memdev, 808 object_property_allow_set_link, 809 OBJ_PROP_LINK_STRONG); 810 object_property_set_description(obj, "memdev", "Set RAM backend" 811 "Valid value is ID of a hostmem backend"); 812 } 813 814 static void ram_class_init(ObjectClass *klass, void *data) 815 { 816 DeviceClass *dc = DEVICE_CLASS(klass); 817 818 dc->realize = ram_realize; 819 } 820 821 static const TypeInfo ram_info = { 822 .name = TYPE_SUN4M_MEMORY, 823 .parent = TYPE_SYS_BUS_DEVICE, 824 .instance_size = sizeof(RamDevice), 825 .instance_init = ram_initfn, 826 .class_init = ram_class_init, 827 }; 828 829 static void cpu_devinit(const char *cpu_type, unsigned int id, 830 uint64_t prom_addr, qemu_irq **cpu_irqs) 831 { 832 SPARCCPU *cpu; 833 CPUSPARCState *env; 834 835 cpu = SPARC_CPU(object_new(cpu_type)); 836 env = &cpu->env; 837 838 cpu_sparc_set_id(env, id); 839 qemu_register_reset(sun4m_cpu_reset, cpu); 840 object_property_set_bool(OBJECT(cpu), "start-powered-off", id != 0, 841 &error_fatal); 842 qdev_realize_and_unref(DEVICE(cpu), NULL, &error_fatal); 843 *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, cpu, MAX_PILS); 844 env->prom_addr = prom_addr; 845 } 846 847 static void dummy_fdc_tc(void *opaque, int irq, int level) 848 { 849 } 850 851 static void sun4m_hw_init(MachineState *machine) 852 { 853 const struct sun4m_hwdef *hwdef = SUN4M_MACHINE_GET_CLASS(machine)->hwdef; 854 DeviceState *slavio_intctl; 855 unsigned int i; 856 Nvram *nvram; 857 qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS]; 858 qemu_irq fdc_tc; 859 unsigned long kernel_size; 860 uint32_t initrd_size; 861 DriveInfo *fd[MAX_FD]; 862 FWCfgState *fw_cfg; 863 DeviceState *dev, *ms_kb_orgate, *serial_orgate; 864 SysBusDevice *s; 865 unsigned int smp_cpus = machine->smp.cpus; 866 unsigned int max_cpus = machine->smp.max_cpus; 867 Object *ram_memdev = object_resolve_path_type(machine->ram_memdev_id, 868 TYPE_MEMORY_BACKEND, NULL); 869 NICInfo *nd = &nd_table[0]; 870 871 if (machine->ram_size > hwdef->max_mem) { 872 error_report("Too much memory for this machine: %" PRId64 "," 873 " maximum %" PRId64, 874 machine->ram_size / MiB, hwdef->max_mem / MiB); 875 exit(1); 876 } 877 878 /* init CPUs */ 879 for(i = 0; i < smp_cpus; i++) { 880 cpu_devinit(machine->cpu_type, i, hwdef->slavio_base, &cpu_irqs[i]); 881 } 882 883 for (i = smp_cpus; i < MAX_CPUS; i++) 884 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS); 885 886 /* Create and map RAM frontend */ 887 dev = qdev_new("memory"); 888 object_property_set_link(OBJECT(dev), "memdev", ram_memdev, &error_fatal); 889 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 890 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0); 891 892 /* models without ECC don't trap when missing ram is accessed */ 893 if (!hwdef->ecc_base) { 894 empty_slot_init("ecc", machine->ram_size, 895 hwdef->max_mem - machine->ram_size); 896 } 897 898 prom_init(hwdef->slavio_base, machine->firmware); 899 900 slavio_intctl = slavio_intctl_init(hwdef->intctl_base, 901 hwdef->intctl_base + 0x10000ULL, 902 cpu_irqs); 903 904 for (i = 0; i < 32; i++) { 905 slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i); 906 } 907 for (i = 0; i < MAX_CPUS; i++) { 908 slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i); 909 } 910 911 if (hwdef->idreg_base) { 912 idreg_init(hwdef->idreg_base); 913 } 914 915 if (hwdef->afx_base) { 916 afx_init(hwdef->afx_base); 917 } 918 919 iommu_init(hwdef->iommu_base, hwdef->iommu_version, slavio_irq[30]); 920 921 if (hwdef->iommu_pad_base) { 922 /* On the real hardware (SS-5, LX) the MMU is not padded, but aliased. 923 Software shouldn't use aliased addresses, neither should it crash 924 when does. Using empty_slot instead of aliasing can help with 925 debugging such accesses */ 926 empty_slot_init("iommu.alias", 927 hwdef->iommu_pad_base, hwdef->iommu_pad_len); 928 } 929 930 qemu_check_nic_model(nd, TYPE_LANCE); 931 sparc32_dma_init(hwdef->dma_base, 932 hwdef->esp_base, slavio_irq[18], 933 hwdef->le_base, slavio_irq[16], nd); 934 935 if (graphic_depth != 8 && graphic_depth != 24) { 936 error_report("Unsupported depth: %d", graphic_depth); 937 exit (1); 938 } 939 if (vga_interface_type != VGA_NONE) { 940 if (vga_interface_type == VGA_CG3) { 941 if (graphic_depth != 8) { 942 error_report("Unsupported depth: %d", graphic_depth); 943 exit(1); 944 } 945 946 if (!(graphic_width == 1024 && graphic_height == 768) && 947 !(graphic_width == 1152 && graphic_height == 900)) { 948 error_report("Unsupported resolution: %d x %d", graphic_width, 949 graphic_height); 950 exit(1); 951 } 952 953 /* sbus irq 5 */ 954 cg3_init(hwdef->tcx_base, slavio_irq[11], 0x00100000, 955 graphic_width, graphic_height, graphic_depth); 956 } else { 957 /* If no display specified, default to TCX */ 958 if (graphic_depth != 8 && graphic_depth != 24) { 959 error_report("Unsupported depth: %d", graphic_depth); 960 exit(1); 961 } 962 963 if (!(graphic_width == 1024 && graphic_height == 768)) { 964 error_report("Unsupported resolution: %d x %d", 965 graphic_width, graphic_height); 966 exit(1); 967 } 968 969 tcx_init(hwdef->tcx_base, slavio_irq[11], 0x00100000, 970 graphic_width, graphic_height, graphic_depth); 971 } 972 } 973 974 for (i = 0; i < MAX_VSIMMS; i++) { 975 /* vsimm registers probed by OBP */ 976 if (hwdef->vsimm[i].reg_base) { 977 char *name = g_strdup_printf("vsimm[%d]", i); 978 empty_slot_init(name, hwdef->vsimm[i].reg_base, 0x2000); 979 g_free(name); 980 } 981 } 982 983 if (hwdef->sx_base) { 984 create_unimplemented_device("sun-sx", hwdef->sx_base, 0x2000); 985 } 986 987 dev = qdev_new("sysbus-m48t08"); 988 qdev_prop_set_int32(dev, "base-year", 1968); 989 s = SYS_BUS_DEVICE(dev); 990 sysbus_realize_and_unref(s, &error_fatal); 991 sysbus_connect_irq(s, 0, slavio_irq[0]); 992 sysbus_mmio_map(s, 0, hwdef->nvram_base); 993 nvram = NVRAM(dev); 994 995 slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus); 996 997 /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device 998 Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */ 999 dev = qdev_new(TYPE_ESCC); 1000 qdev_prop_set_uint32(dev, "disabled", !machine->enable_graphics); 1001 qdev_prop_set_uint32(dev, "frequency", ESCC_CLOCK); 1002 qdev_prop_set_uint32(dev, "it_shift", 1); 1003 qdev_prop_set_chr(dev, "chrB", NULL); 1004 qdev_prop_set_chr(dev, "chrA", NULL); 1005 qdev_prop_set_uint32(dev, "chnBtype", escc_mouse); 1006 qdev_prop_set_uint32(dev, "chnAtype", escc_kbd); 1007 s = SYS_BUS_DEVICE(dev); 1008 sysbus_realize_and_unref(s, &error_fatal); 1009 sysbus_mmio_map(s, 0, hwdef->ms_kb_base); 1010 1011 /* Logically OR both its IRQs together */ 1012 ms_kb_orgate = DEVICE(object_new(TYPE_OR_IRQ)); 1013 object_property_set_int(OBJECT(ms_kb_orgate), "num-lines", 2, &error_fatal); 1014 qdev_realize_and_unref(ms_kb_orgate, NULL, &error_fatal); 1015 sysbus_connect_irq(s, 0, qdev_get_gpio_in(ms_kb_orgate, 0)); 1016 sysbus_connect_irq(s, 1, qdev_get_gpio_in(ms_kb_orgate, 1)); 1017 qdev_connect_gpio_out(DEVICE(ms_kb_orgate), 0, slavio_irq[14]); 1018 1019 dev = qdev_new(TYPE_ESCC); 1020 qdev_prop_set_uint32(dev, "disabled", 0); 1021 qdev_prop_set_uint32(dev, "frequency", ESCC_CLOCK); 1022 qdev_prop_set_uint32(dev, "it_shift", 1); 1023 qdev_prop_set_chr(dev, "chrB", serial_hd(1)); 1024 qdev_prop_set_chr(dev, "chrA", serial_hd(0)); 1025 qdev_prop_set_uint32(dev, "chnBtype", escc_serial); 1026 qdev_prop_set_uint32(dev, "chnAtype", escc_serial); 1027 1028 s = SYS_BUS_DEVICE(dev); 1029 sysbus_realize_and_unref(s, &error_fatal); 1030 sysbus_mmio_map(s, 0, hwdef->serial_base); 1031 1032 /* Logically OR both its IRQs together */ 1033 serial_orgate = DEVICE(object_new(TYPE_OR_IRQ)); 1034 object_property_set_int(OBJECT(serial_orgate), "num-lines", 2, 1035 &error_fatal); 1036 qdev_realize_and_unref(serial_orgate, NULL, &error_fatal); 1037 sysbus_connect_irq(s, 0, qdev_get_gpio_in(serial_orgate, 0)); 1038 sysbus_connect_irq(s, 1, qdev_get_gpio_in(serial_orgate, 1)); 1039 qdev_connect_gpio_out(DEVICE(serial_orgate), 0, slavio_irq[15]); 1040 1041 if (hwdef->apc_base) { 1042 apc_init(hwdef->apc_base, qemu_allocate_irq(cpu_halt_signal, NULL, 0)); 1043 } 1044 1045 if (hwdef->fd_base) { 1046 /* there is zero or one floppy drive */ 1047 memset(fd, 0, sizeof(fd)); 1048 fd[0] = drive_get(IF_FLOPPY, 0, 0); 1049 sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd, 1050 &fdc_tc); 1051 } else { 1052 fdc_tc = qemu_allocate_irq(dummy_fdc_tc, NULL, 0); 1053 } 1054 1055 slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base, 1056 slavio_irq[30], fdc_tc); 1057 1058 if (hwdef->cs_base) { 1059 sysbus_create_simple("sun-CS4231", hwdef->cs_base, 1060 slavio_irq[5]); 1061 } 1062 1063 if (hwdef->dbri_base) { 1064 /* ISDN chip with attached CS4215 audio codec */ 1065 /* prom space */ 1066 create_unimplemented_device("sun-DBRI.prom", 1067 hwdef->dbri_base + 0x1000, 0x30); 1068 /* reg space */ 1069 create_unimplemented_device("sun-DBRI", 1070 hwdef->dbri_base + 0x10000, 0x100); 1071 } 1072 1073 if (hwdef->bpp_base) { 1074 /* parallel port */ 1075 create_unimplemented_device("sun-bpp", hwdef->bpp_base, 0x20); 1076 } 1077 1078 initrd_size = 0; 1079 kernel_size = sun4m_load_kernel(machine->kernel_filename, 1080 machine->initrd_filename, 1081 machine->ram_size, &initrd_size); 1082 1083 nvram_init(nvram, (uint8_t *)&nd->macaddr, machine->kernel_cmdline, 1084 machine->boot_order, machine->ram_size, kernel_size, 1085 graphic_width, graphic_height, graphic_depth, 1086 hwdef->nvram_machine_id, "Sun4m"); 1087 1088 if (hwdef->ecc_base) 1089 ecc_init(hwdef->ecc_base, slavio_irq[28], 1090 hwdef->ecc_version); 1091 1092 dev = qdev_new(TYPE_FW_CFG_MEM); 1093 fw_cfg = FW_CFG(dev); 1094 qdev_prop_set_uint32(dev, "data_width", 1); 1095 qdev_prop_set_bit(dev, "dma_enabled", false); 1096 object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG, 1097 OBJECT(fw_cfg)); 1098 s = SYS_BUS_DEVICE(dev); 1099 sysbus_realize_and_unref(s, &error_fatal); 1100 sysbus_mmio_map(s, 0, CFG_ADDR); 1101 sysbus_mmio_map(s, 1, CFG_ADDR + 2); 1102 1103 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus); 1104 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus); 1105 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)machine->ram_size); 1106 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); 1107 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth); 1108 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_WIDTH, graphic_width); 1109 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_HEIGHT, graphic_height); 1110 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR); 1111 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 1112 if (machine->kernel_cmdline) { 1113 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR); 1114 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, 1115 machine->kernel_cmdline); 1116 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline); 1117 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 1118 strlen(machine->kernel_cmdline) + 1); 1119 } else { 1120 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0); 1121 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0); 1122 } 1123 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR); 1124 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 1125 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]); 1126 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); 1127 } 1128 1129 enum { 1130 ss5_id = 32, 1131 vger_id, 1132 lx_id, 1133 ss4_id, 1134 scls_id, 1135 sbook_id, 1136 ss10_id = 64, 1137 ss20_id, 1138 ss600mp_id, 1139 }; 1140 1141 static void sun4m_machine_class_init(ObjectClass *oc, void *data) 1142 { 1143 MachineClass *mc = MACHINE_CLASS(oc); 1144 1145 mc->init = sun4m_hw_init; 1146 mc->block_default_type = IF_SCSI; 1147 mc->default_boot_order = "c"; 1148 mc->default_display = "tcx"; 1149 mc->default_ram_id = "sun4m.ram"; 1150 } 1151 1152 static void ss5_class_init(ObjectClass *oc, void *data) 1153 { 1154 MachineClass *mc = MACHINE_CLASS(oc); 1155 Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); 1156 static const struct sun4m_hwdef ss5_hwdef = { 1157 .iommu_base = 0x10000000, 1158 .iommu_pad_base = 0x10004000, 1159 .iommu_pad_len = 0x0fffb000, 1160 .tcx_base = 0x50000000, 1161 .cs_base = 0x6c000000, 1162 .slavio_base = 0x70000000, 1163 .ms_kb_base = 0x71000000, 1164 .serial_base = 0x71100000, 1165 .nvram_base = 0x71200000, 1166 .fd_base = 0x71400000, 1167 .counter_base = 0x71d00000, 1168 .intctl_base = 0x71e00000, 1169 .idreg_base = 0x78000000, 1170 .dma_base = 0x78400000, 1171 .esp_base = 0x78800000, 1172 .le_base = 0x78c00000, 1173 .apc_base = 0x6a000000, 1174 .afx_base = 0x6e000000, 1175 .aux1_base = 0x71900000, 1176 .aux2_base = 0x71910000, 1177 .nvram_machine_id = 0x80, 1178 .machine_id = ss5_id, 1179 .iommu_version = 0x05000000, 1180 .max_mem = 0x10000000, 1181 }; 1182 1183 mc->desc = "Sun4m platform, SPARCstation 5"; 1184 mc->is_default = true; 1185 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904"); 1186 smc->hwdef = &ss5_hwdef; 1187 } 1188 1189 static void ss10_class_init(ObjectClass *oc, void *data) 1190 { 1191 MachineClass *mc = MACHINE_CLASS(oc); 1192 Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); 1193 static const struct sun4m_hwdef ss10_hwdef = { 1194 .iommu_base = 0xfe0000000ULL, 1195 .tcx_base = 0xe20000000ULL, 1196 .slavio_base = 0xff0000000ULL, 1197 .ms_kb_base = 0xff1000000ULL, 1198 .serial_base = 0xff1100000ULL, 1199 .nvram_base = 0xff1200000ULL, 1200 .fd_base = 0xff1700000ULL, 1201 .counter_base = 0xff1300000ULL, 1202 .intctl_base = 0xff1400000ULL, 1203 .idreg_base = 0xef0000000ULL, 1204 .dma_base = 0xef0400000ULL, 1205 .esp_base = 0xef0800000ULL, 1206 .le_base = 0xef0c00000ULL, 1207 .apc_base = 0xefa000000ULL, /* XXX should not exist */ 1208 .aux1_base = 0xff1800000ULL, 1209 .aux2_base = 0xff1a01000ULL, 1210 .ecc_base = 0xf00000000ULL, 1211 .ecc_version = 0x10000000, /* version 0, implementation 1 */ 1212 .nvram_machine_id = 0x72, 1213 .machine_id = ss10_id, 1214 .iommu_version = 0x03000000, 1215 .max_mem = 0xf00000000ULL, 1216 }; 1217 1218 mc->desc = "Sun4m platform, SPARCstation 10"; 1219 mc->max_cpus = 4; 1220 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II"); 1221 smc->hwdef = &ss10_hwdef; 1222 } 1223 1224 static void ss600mp_class_init(ObjectClass *oc, void *data) 1225 { 1226 MachineClass *mc = MACHINE_CLASS(oc); 1227 Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); 1228 static const struct sun4m_hwdef ss600mp_hwdef = { 1229 .iommu_base = 0xfe0000000ULL, 1230 .tcx_base = 0xe20000000ULL, 1231 .slavio_base = 0xff0000000ULL, 1232 .ms_kb_base = 0xff1000000ULL, 1233 .serial_base = 0xff1100000ULL, 1234 .nvram_base = 0xff1200000ULL, 1235 .counter_base = 0xff1300000ULL, 1236 .intctl_base = 0xff1400000ULL, 1237 .dma_base = 0xef0081000ULL, 1238 .esp_base = 0xef0080000ULL, 1239 .le_base = 0xef0060000ULL, 1240 .apc_base = 0xefa000000ULL, /* XXX should not exist */ 1241 .aux1_base = 0xff1800000ULL, 1242 .aux2_base = 0xff1a01000ULL, /* XXX should not exist */ 1243 .ecc_base = 0xf00000000ULL, 1244 .ecc_version = 0x00000000, /* version 0, implementation 0 */ 1245 .nvram_machine_id = 0x71, 1246 .machine_id = ss600mp_id, 1247 .iommu_version = 0x01000000, 1248 .max_mem = 0xf00000000ULL, 1249 }; 1250 1251 mc->desc = "Sun4m platform, SPARCserver 600MP"; 1252 mc->max_cpus = 4; 1253 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II"); 1254 smc->hwdef = &ss600mp_hwdef; 1255 } 1256 1257 static void ss20_class_init(ObjectClass *oc, void *data) 1258 { 1259 MachineClass *mc = MACHINE_CLASS(oc); 1260 Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); 1261 static const struct sun4m_hwdef ss20_hwdef = { 1262 .iommu_base = 0xfe0000000ULL, 1263 .tcx_base = 0xe20000000ULL, 1264 .slavio_base = 0xff0000000ULL, 1265 .ms_kb_base = 0xff1000000ULL, 1266 .serial_base = 0xff1100000ULL, 1267 .nvram_base = 0xff1200000ULL, 1268 .fd_base = 0xff1700000ULL, 1269 .counter_base = 0xff1300000ULL, 1270 .intctl_base = 0xff1400000ULL, 1271 .idreg_base = 0xef0000000ULL, 1272 .dma_base = 0xef0400000ULL, 1273 .esp_base = 0xef0800000ULL, 1274 .le_base = 0xef0c00000ULL, 1275 .bpp_base = 0xef4800000ULL, 1276 .apc_base = 0xefa000000ULL, /* XXX should not exist */ 1277 .aux1_base = 0xff1800000ULL, 1278 .aux2_base = 0xff1a01000ULL, 1279 .dbri_base = 0xee0000000ULL, 1280 .sx_base = 0xf80000000ULL, 1281 .vsimm = { 1282 { 1283 .reg_base = 0x9c000000ULL, 1284 .vram_base = 0xfc000000ULL 1285 }, { 1286 .reg_base = 0x90000000ULL, 1287 .vram_base = 0xf0000000ULL 1288 }, { 1289 .reg_base = 0x94000000ULL 1290 }, { 1291 .reg_base = 0x98000000ULL 1292 } 1293 }, 1294 .ecc_base = 0xf00000000ULL, 1295 .ecc_version = 0x20000000, /* version 0, implementation 2 */ 1296 .nvram_machine_id = 0x72, 1297 .machine_id = ss20_id, 1298 .iommu_version = 0x13000000, 1299 .max_mem = 0xf00000000ULL, 1300 }; 1301 1302 mc->desc = "Sun4m platform, SPARCstation 20"; 1303 mc->max_cpus = 4; 1304 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II"); 1305 smc->hwdef = &ss20_hwdef; 1306 } 1307 1308 static void voyager_class_init(ObjectClass *oc, void *data) 1309 { 1310 MachineClass *mc = MACHINE_CLASS(oc); 1311 Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); 1312 static const struct sun4m_hwdef voyager_hwdef = { 1313 .iommu_base = 0x10000000, 1314 .tcx_base = 0x50000000, 1315 .slavio_base = 0x70000000, 1316 .ms_kb_base = 0x71000000, 1317 .serial_base = 0x71100000, 1318 .nvram_base = 0x71200000, 1319 .fd_base = 0x71400000, 1320 .counter_base = 0x71d00000, 1321 .intctl_base = 0x71e00000, 1322 .idreg_base = 0x78000000, 1323 .dma_base = 0x78400000, 1324 .esp_base = 0x78800000, 1325 .le_base = 0x78c00000, 1326 .apc_base = 0x71300000, /* pmc */ 1327 .aux1_base = 0x71900000, 1328 .aux2_base = 0x71910000, 1329 .nvram_machine_id = 0x80, 1330 .machine_id = vger_id, 1331 .iommu_version = 0x05000000, 1332 .max_mem = 0x10000000, 1333 }; 1334 1335 mc->desc = "Sun4m platform, SPARCstation Voyager"; 1336 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904"); 1337 smc->hwdef = &voyager_hwdef; 1338 } 1339 1340 static void ss_lx_class_init(ObjectClass *oc, void *data) 1341 { 1342 MachineClass *mc = MACHINE_CLASS(oc); 1343 Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); 1344 static const struct sun4m_hwdef ss_lx_hwdef = { 1345 .iommu_base = 0x10000000, 1346 .iommu_pad_base = 0x10004000, 1347 .iommu_pad_len = 0x0fffb000, 1348 .tcx_base = 0x50000000, 1349 .slavio_base = 0x70000000, 1350 .ms_kb_base = 0x71000000, 1351 .serial_base = 0x71100000, 1352 .nvram_base = 0x71200000, 1353 .fd_base = 0x71400000, 1354 .counter_base = 0x71d00000, 1355 .intctl_base = 0x71e00000, 1356 .idreg_base = 0x78000000, 1357 .dma_base = 0x78400000, 1358 .esp_base = 0x78800000, 1359 .le_base = 0x78c00000, 1360 .aux1_base = 0x71900000, 1361 .aux2_base = 0x71910000, 1362 .nvram_machine_id = 0x80, 1363 .machine_id = lx_id, 1364 .iommu_version = 0x04000000, 1365 .max_mem = 0x10000000, 1366 }; 1367 1368 mc->desc = "Sun4m platform, SPARCstation LX"; 1369 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I"); 1370 smc->hwdef = &ss_lx_hwdef; 1371 } 1372 1373 static void ss4_class_init(ObjectClass *oc, void *data) 1374 { 1375 MachineClass *mc = MACHINE_CLASS(oc); 1376 Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); 1377 static const struct sun4m_hwdef ss4_hwdef = { 1378 .iommu_base = 0x10000000, 1379 .tcx_base = 0x50000000, 1380 .cs_base = 0x6c000000, 1381 .slavio_base = 0x70000000, 1382 .ms_kb_base = 0x71000000, 1383 .serial_base = 0x71100000, 1384 .nvram_base = 0x71200000, 1385 .fd_base = 0x71400000, 1386 .counter_base = 0x71d00000, 1387 .intctl_base = 0x71e00000, 1388 .idreg_base = 0x78000000, 1389 .dma_base = 0x78400000, 1390 .esp_base = 0x78800000, 1391 .le_base = 0x78c00000, 1392 .apc_base = 0x6a000000, 1393 .aux1_base = 0x71900000, 1394 .aux2_base = 0x71910000, 1395 .nvram_machine_id = 0x80, 1396 .machine_id = ss4_id, 1397 .iommu_version = 0x05000000, 1398 .max_mem = 0x10000000, 1399 }; 1400 1401 mc->desc = "Sun4m platform, SPARCstation 4"; 1402 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904"); 1403 smc->hwdef = &ss4_hwdef; 1404 } 1405 1406 static void scls_class_init(ObjectClass *oc, void *data) 1407 { 1408 MachineClass *mc = MACHINE_CLASS(oc); 1409 Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); 1410 static const struct sun4m_hwdef scls_hwdef = { 1411 .iommu_base = 0x10000000, 1412 .tcx_base = 0x50000000, 1413 .slavio_base = 0x70000000, 1414 .ms_kb_base = 0x71000000, 1415 .serial_base = 0x71100000, 1416 .nvram_base = 0x71200000, 1417 .fd_base = 0x71400000, 1418 .counter_base = 0x71d00000, 1419 .intctl_base = 0x71e00000, 1420 .idreg_base = 0x78000000, 1421 .dma_base = 0x78400000, 1422 .esp_base = 0x78800000, 1423 .le_base = 0x78c00000, 1424 .apc_base = 0x6a000000, 1425 .aux1_base = 0x71900000, 1426 .aux2_base = 0x71910000, 1427 .nvram_machine_id = 0x80, 1428 .machine_id = scls_id, 1429 .iommu_version = 0x05000000, 1430 .max_mem = 0x10000000, 1431 }; 1432 1433 mc->desc = "Sun4m platform, SPARCClassic"; 1434 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I"); 1435 smc->hwdef = &scls_hwdef; 1436 } 1437 1438 static void sbook_class_init(ObjectClass *oc, void *data) 1439 { 1440 MachineClass *mc = MACHINE_CLASS(oc); 1441 Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); 1442 static const struct sun4m_hwdef sbook_hwdef = { 1443 .iommu_base = 0x10000000, 1444 .tcx_base = 0x50000000, /* XXX */ 1445 .slavio_base = 0x70000000, 1446 .ms_kb_base = 0x71000000, 1447 .serial_base = 0x71100000, 1448 .nvram_base = 0x71200000, 1449 .fd_base = 0x71400000, 1450 .counter_base = 0x71d00000, 1451 .intctl_base = 0x71e00000, 1452 .idreg_base = 0x78000000, 1453 .dma_base = 0x78400000, 1454 .esp_base = 0x78800000, 1455 .le_base = 0x78c00000, 1456 .apc_base = 0x6a000000, 1457 .aux1_base = 0x71900000, 1458 .aux2_base = 0x71910000, 1459 .nvram_machine_id = 0x80, 1460 .machine_id = sbook_id, 1461 .iommu_version = 0x05000000, 1462 .max_mem = 0x10000000, 1463 }; 1464 1465 mc->desc = "Sun4m platform, SPARCbook"; 1466 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I"); 1467 smc->hwdef = &sbook_hwdef; 1468 } 1469 1470 static const TypeInfo sun4m_machine_types[] = { 1471 { 1472 .name = MACHINE_TYPE_NAME("SS-5"), 1473 .parent = TYPE_SUN4M_MACHINE, 1474 .class_init = ss5_class_init, 1475 }, { 1476 .name = MACHINE_TYPE_NAME("SS-10"), 1477 .parent = TYPE_SUN4M_MACHINE, 1478 .class_init = ss10_class_init, 1479 }, { 1480 .name = MACHINE_TYPE_NAME("SS-600MP"), 1481 .parent = TYPE_SUN4M_MACHINE, 1482 .class_init = ss600mp_class_init, 1483 }, { 1484 .name = MACHINE_TYPE_NAME("SS-20"), 1485 .parent = TYPE_SUN4M_MACHINE, 1486 .class_init = ss20_class_init, 1487 }, { 1488 .name = MACHINE_TYPE_NAME("Voyager"), 1489 .parent = TYPE_SUN4M_MACHINE, 1490 .class_init = voyager_class_init, 1491 }, { 1492 .name = MACHINE_TYPE_NAME("LX"), 1493 .parent = TYPE_SUN4M_MACHINE, 1494 .class_init = ss_lx_class_init, 1495 }, { 1496 .name = MACHINE_TYPE_NAME("SS-4"), 1497 .parent = TYPE_SUN4M_MACHINE, 1498 .class_init = ss4_class_init, 1499 }, { 1500 .name = MACHINE_TYPE_NAME("SPARCClassic"), 1501 .parent = TYPE_SUN4M_MACHINE, 1502 .class_init = scls_class_init, 1503 }, { 1504 .name = MACHINE_TYPE_NAME("SPARCbook"), 1505 .parent = TYPE_SUN4M_MACHINE, 1506 .class_init = sbook_class_init, 1507 }, { 1508 .name = TYPE_SUN4M_MACHINE, 1509 .parent = TYPE_MACHINE, 1510 .class_size = sizeof(Sun4mMachineClass), 1511 .class_init = sun4m_machine_class_init, 1512 .abstract = true, 1513 } 1514 }; 1515 1516 DEFINE_TYPES(sun4m_machine_types) 1517 1518 static void sun4m_register_types(void) 1519 { 1520 type_register_static(&idreg_info); 1521 type_register_static(&afx_info); 1522 type_register_static(&prom_info); 1523 type_register_static(&ram_info); 1524 } 1525 1526 type_init(sun4m_register_types) 1527